summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
blob: f221e17b67e780f4733e265d7a7f7c85e40fe0ca (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef _SMU7_HWMGR_H
#define _SMU7_HWMGR_H

#include "hwmgr.h"
#include "ppatomctrl.h"

#define SMU7_MAX_HARDWARE_POWERLEVELS   2

#define SMU7_VOLTAGE_CONTROL_NONE                   0x0
#define SMU7_VOLTAGE_CONTROL_BY_GPIO                0x1
#define SMU7_VOLTAGE_CONTROL_BY_SVID2               0x2
#define SMU7_VOLTAGE_CONTROL_MERGED                 0x3

#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
#define DPMTABLE_UPDATE_SCLK        0x00000004
#define DPMTABLE_UPDATE_MCLK        0x00000008

enum gpu_pt_config_reg_type {
	GPU_CONFIGREG_MMR = 0,
	GPU_CONFIGREG_SMC_IND,
	GPU_CONFIGREG_DIDT_IND,
	GPU_CONFIGREG_GC_CAC_IND,
	GPU_CONFIGREG_CACHE,
	GPU_CONFIGREG_MAX
};

struct gpu_pt_config_reg {
	uint32_t                           offset;
	uint32_t                           mask;
	uint32_t                           shift;
	uint32_t                           value;
	enum gpu_pt_config_reg_type       type;
};

struct smu7_performance_level {
	uint32_t  memory_clock;
	uint32_t  engine_clock;
	uint16_t  pcie_gen;
	uint16_t  pcie_lane;
};

struct smu7_thermal_temperature_setting {
	long temperature_low;
	long temperature_high;
	long temperature_shutdown;
};

struct smu7_uvd_clocks {
	uint32_t  vclk;
	uint32_t  dclk;
};

struct smu7_vce_clocks {
	uint32_t  evclk;
	uint32_t  ecclk;
};

struct smu7_power_state {
	uint32_t                  magic;
	struct smu7_uvd_clocks    uvd_clks;
	struct smu7_vce_clocks    vce_clks;
	uint32_t                  sam_clk;
	uint16_t                  performance_level_count;
	bool                      dc_compatible;
	uint32_t                  sclk_threshold;
	struct smu7_performance_level  performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS];
};

struct smu7_dpm_level {
	bool	enabled;
	uint32_t	value;
	uint32_t	param1;
};

#define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5
#define MAX_REGULAR_DPM_NUMBER 8
#define SMU7_MINIMUM_ENGINE_CLOCK 2500

struct smu7_single_dpm_table {
	uint32_t		count;
	struct smu7_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
};

struct smu7_dpm_table {
	struct smu7_single_dpm_table  sclk_table;
	struct smu7_single_dpm_table  mclk_table;
	struct smu7_single_dpm_table  pcie_speed_table;
	struct smu7_single_dpm_table  vddc_table;
	struct smu7_single_dpm_table  vddci_table;
	struct smu7_single_dpm_table  mvdd_table;
};

struct smu7_clock_registers {
	uint32_t  vCG_SPLL_FUNC_CNTL;
	uint32_t  vCG_SPLL_FUNC_CNTL_2;
	uint32_t  vCG_SPLL_FUNC_CNTL_3;
	uint32_t  vCG_SPLL_FUNC_CNTL_4;
	uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
	uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
	uint32_t  vDLL_CNTL;
	uint32_t  vMCLK_PWRMGT_CNTL;
	uint32_t  vMPLL_AD_FUNC_CNTL;
	uint32_t  vMPLL_DQ_FUNC_CNTL;
	uint32_t  vMPLL_FUNC_CNTL;
	uint32_t  vMPLL_FUNC_CNTL_1;
	uint32_t  vMPLL_FUNC_CNTL_2;
	uint32_t  vMPLL_SS1;
	uint32_t  vMPLL_SS2;
};

#define DISABLE_MC_LOADMICROCODE   1
#define DISABLE_MC_CFGPROGRAMMING  2

struct smu7_voltage_smio_registers {
	uint32_t vS0_VID_LOWER_SMIO_CNTL;
};

#define SMU7_MAX_LEAKAGE_COUNT  8

struct smu7_leakage_voltage {
	uint16_t  count;
	uint16_t  leakage_id[SMU7_MAX_LEAKAGE_COUNT];
	uint16_t  actual_voltage[SMU7_MAX_LEAKAGE_COUNT];
};

struct smu7_vbios_boot_state {
	uint16_t    mvdd_bootup_value;
	uint16_t    vddc_bootup_value;
	uint16_t    vddci_bootup_value;
	uint16_t    vddgfx_bootup_value;
	uint32_t    sclk_bootup_value;
	uint32_t    mclk_bootup_value;
	uint16_t    pcie_gen_bootup_value;
	uint16_t    pcie_lane_bootup_value;
};

struct smu7_display_timing {
	uint32_t  min_clock_in_sr;
	uint32_t  num_existing_displays;
};

struct smu7_dpmlevel_enable_mask {
	uint32_t  uvd_dpm_enable_mask;
	uint32_t  vce_dpm_enable_mask;
	uint32_t  acp_dpm_enable_mask;
	uint32_t  samu_dpm_enable_mask;
	uint32_t  sclk_dpm_enable_mask;
	uint32_t  mclk_dpm_enable_mask;
	uint32_t  pcie_dpm_enable_mask;
};

struct smu7_pcie_perf_range {
	uint16_t  max;
	uint16_t  min;
};

struct smu7_hwmgr {
	struct smu7_dpm_table			dpm_table;
	struct smu7_dpm_table			golden_dpm_table;

	uint32_t						voting_rights_clients0;
	uint32_t						voting_rights_clients1;
	uint32_t						voting_rights_clients2;
	uint32_t						voting_rights_clients3;
	uint32_t						voting_rights_clients4;
	uint32_t						voting_rights_clients5;
	uint32_t						voting_rights_clients6;
	uint32_t						voting_rights_clients7;
	uint32_t						static_screen_threshold_unit;
	uint32_t						static_screen_threshold;
	uint32_t						voltage_control;
	uint32_t						vdd_gfx_control;
	uint32_t						vddc_vddgfx_delta;
	uint32_t						active_auto_throttle_sources;

	struct smu7_clock_registers            clock_registers;

	bool                           is_memory_gddr5;
	uint16_t                       acpi_vddc;
	bool                           pspp_notify_required;
	uint16_t                       force_pcie_gen;
	uint16_t                       acpi_pcie_gen;
	uint32_t                       pcie_gen_cap;
	uint32_t                       pcie_lane_cap;
	uint32_t                       pcie_spc_cap;
	struct smu7_leakage_voltage          vddc_leakage;
	struct smu7_leakage_voltage          vddci_leakage;
	struct smu7_leakage_voltage          vddcgfx_leakage;

	uint32_t                             mvdd_control;
	uint32_t                             vddc_mask_low;
	uint32_t                             mvdd_mask_low;
	uint16_t                            max_vddc_in_pptable;
	uint16_t                            min_vddc_in_pptable;
	uint16_t                            max_vddci_in_pptable;
	uint16_t                            min_vddci_in_pptable;
	bool                                is_uvd_enabled;
	struct smu7_vbios_boot_state        vbios_boot_state;

	bool                           pcie_performance_request;
	bool                           battery_state;
	bool                           is_tlu_enabled;
	bool                           disable_handshake;
	bool                           smc_voltage_control_enabled;
	bool                           vbi_time_out_support;

	uint32_t                       soft_regs_start;
	/* ---- Stuff originally coming from Evergreen ---- */
	uint32_t                             vddci_control;
	struct pp_atomctrl_voltage_table     vddc_voltage_table;
	struct pp_atomctrl_voltage_table     vddci_voltage_table;
	struct pp_atomctrl_voltage_table     mvdd_voltage_table;
	struct pp_atomctrl_voltage_table     vddgfx_voltage_table;

	uint32_t                             mgcg_cgtt_local2;
	uint32_t                             mgcg_cgtt_local3;
	uint32_t                             gpio_debug;
	uint32_t                             mc_micro_code_feature;
	uint32_t                             highest_mclk;
	uint16_t                             acpi_vddci;
	uint8_t                              mvdd_high_index;
	uint8_t                              mvdd_low_index;
	bool                                 dll_default_on;
	bool                                 performance_request_registered;

	/* ---- Low Power Features ---- */
	bool                           ulv_supported;

	/* ---- CAC Stuff ---- */
	uint32_t                       cac_table_start;
	bool                           cac_configuration_required;
	bool                           driver_calculate_cac_leakage;
	bool                           cac_enabled;

	/* ---- DPM2 Parameters ---- */
	uint32_t                       power_containment_features;
	bool                           enable_dte_feature;
	bool                           enable_tdc_limit_feature;
	bool                           enable_pkg_pwr_tracking_feature;
	bool                           disable_uvd_power_tune_feature;


	uint32_t                       dte_tj_offset;
	uint32_t                       fast_watermark_threshold;

	/* ---- Phase Shedding ---- */
	uint8_t                           vddc_phase_shed_control;

	/* ---- DI/DT ---- */
	struct smu7_display_timing        display_timing;

	/* ---- Thermal Temperature Setting ---- */
	struct smu7_thermal_temperature_setting  thermal_temp_setting;
	struct smu7_dpmlevel_enable_mask     dpm_level_enable_mask;
	uint32_t                                  need_update_smu7_dpm_table;
	uint32_t                                  sclk_dpm_key_disabled;
	uint32_t                                  mclk_dpm_key_disabled;
	uint32_t                                  pcie_dpm_key_disabled;
	uint32_t                                  min_engine_clocks;
	struct smu7_pcie_perf_range          pcie_gen_performance;
	struct smu7_pcie_perf_range          pcie_lane_performance;
	struct smu7_pcie_perf_range          pcie_gen_power_saving;
	struct smu7_pcie_perf_range          pcie_lane_power_saving;
	bool                                      use_pcie_performance_levels;
	bool                                      use_pcie_power_saving_levels;
	uint32_t                                  mclk_activity_target;
	uint32_t                                  mclk_dpm0_activity_target;
	uint32_t                                  low_sclk_interrupt_threshold;
	uint32_t                                  last_mclk_dpm_enable_mask;
	bool                                      uvd_enabled;

	/* ---- Power Gating States ---- */
	bool                           uvd_power_gated;
	bool                           vce_power_gated;
	bool                           samu_power_gated;
	bool                           need_long_memory_training;

	/* Application power optimization parameters */
	bool                               update_up_hyst;
	bool                               update_down_hyst;
	uint32_t                           down_hyst;
	uint32_t                           up_hyst;
	uint32_t disable_dpm_mask;
	bool apply_optimized_settings;

	uint32_t                              avfs_vdroop_override_setting;
	bool                                  apply_avfs_cks_off_voltage;
	uint32_t                              frame_time_x2;
	uint16_t                              mem_latency_high;
	uint16_t                              mem_latency_low;
};

/* To convert to Q8.8 format for firmware */
#define SMU7_Q88_FORMAT_CONVERSION_UNIT             256

enum SMU7_I2CLineID {
	SMU7_I2CLineID_DDC1 = 0x90,
	SMU7_I2CLineID_DDC2 = 0x91,
	SMU7_I2CLineID_DDC3 = 0x92,
	SMU7_I2CLineID_DDC4 = 0x93,
	SMU7_I2CLineID_DDC5 = 0x94,
	SMU7_I2CLineID_DDC6 = 0x95,
	SMU7_I2CLineID_SCLSDA = 0x96,
	SMU7_I2CLineID_DDCVGA = 0x97
};

#define SMU7_I2C_DDC1DATA          0
#define SMU7_I2C_DDC1CLK           1
#define SMU7_I2C_DDC2DATA          2
#define SMU7_I2C_DDC2CLK           3
#define SMU7_I2C_DDC3DATA          4
#define SMU7_I2C_DDC3CLK           5
#define SMU7_I2C_SDA               40
#define SMU7_I2C_SCL               41
#define SMU7_I2C_DDC4DATA          65
#define SMU7_I2C_DDC4CLK           66
#define SMU7_I2C_DDC5DATA          0x48
#define SMU7_I2C_DDC5CLK           0x49
#define SMU7_I2C_DDC6DATA          0x4a
#define SMU7_I2C_DDC6CLK           0x4b
#define SMU7_I2C_DDCVGADATA        0x4c
#define SMU7_I2C_DDCVGACLK         0x4d

#define SMU7_UNUSED_GPIO_PIN       0x7F
uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
		uint32_t clock_insr);
#endif