blob: 38e32cce5174049a350254e18fa1935a28fbdba2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2023 Intel Corporation
*/
#ifndef __I9XX_WM_H__
#define __I9XX_WM_H__
#include <linux/types.h>
struct drm_i915_private;
struct intel_crtc_state;
struct intel_plane_state;
int ilk_wm_max_level(const struct drm_i915_private *i915);
void g4x_wm_get_hw_state(struct drm_i915_private *i915);
void vlv_wm_get_hw_state(struct drm_i915_private *i915);
void ilk_wm_get_hw_state(struct drm_i915_private *i915);
void g4x_wm_sanitize(struct drm_i915_private *i915);
void vlv_wm_sanitize(struct drm_i915_private *i915);
bool ilk_disable_lp_wm(struct drm_i915_private *i915);
bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable);
void i9xx_wm_init(struct drm_i915_private *i915);
#endif /* __I9XX_WM_H__ */
|
