path: root/drivers/net/dsa/mv88e6xxx/pcs-639x.c

#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/mii.h>

#include "chip.h"
#include "global2.h"
#include "phy.h"
#include "port.h"
#include "serdes.h"

struct mv88e639x_pcs {
	struct mdio_device mdio;
	struct phylink_pcs sgmii_pcs;
	struct phylink_pcs xg_pcs;
	unsigned int irq;
	char name[64];
	irqreturn_t (*handle_irq)(struct mv88e639x_pcs *mpcs);
	struct mv88e6xxx_port *port;
};

static int mv88e639x_read(struct mv88e639x_pcs *mpcs, u16 regnum, u16 *val)
{
	u32 reg_c45 = mdiobus_c45_addr(MDIO_MMD_PHYXS, regnum);
	int err;

	err = mdiodev_read(&mpcs->mdio, reg_c45);
	if (err < 0)
		return err;

	*val = err;

	return 0;
}

static int mv88e639x_write(struct mv88e639x_pcs *mpcs, u16 regnum, u16 val)
{
	u32 reg_c45 = mdiobus_c45_addr(MDIO_MMD_PHYXS, regnum);

	return mdiodev_write(&mpcs->mdio, reg_c45, val);
}

static int mv88e639x_modify(struct mv88e639x_pcs *mpcs, u16 regnum, u16 mask,
			    u16 val)
{
	u32 reg_c45 = mdiobus_c45_addr(MDIO_MMD_PHYXS, regnum);

	return mdiodev_modify(&mpcs->mdio, reg_c45, mask, val);
}

static int mv88e639x_modify_changed(struct mv88e639x_pcs *mpcs, u16 regnum,
				    u16 mask, u16 set)
{
	u32 reg_c45 = mdiobus_c45_addr(MDIO_MMD_PHYXS, regnum);

	return mdiodev_modify_changed(&mpcs->mdio, reg_c45, mask, set);
}


static struct mv88e639x_pcs *
mv88e639x_pcs_alloc(struct device *dev, struct mii_bus *bus, unsigned int addr,
		    int port)
{
	struct mv88e639x_pcs *mpcs;

	mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
	if (!mpcs)
		return NULL;

	/* we never initialise or register mpcs->mdio.dev with the
	 * driver model, so devm_kzalloc() above is safe.
	 */
	mpcs->mdio.dev.parent = dev;
	mpcs->mdio.bus = bus;
	mpcs->mdio.addr = addr;

	snprintf(mpcs->name, sizeof(mpcs->name),
		 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port);

	return mpcs;
}

static irqreturn_t mv88e639x_pcs_handle_irq(int irq, void *dev_id)
{
	struct mv88e639x_pcs *mpcs = dev_id;
	irqreturn_t (*handler)(struct mv88e639x_pcs *);

	handler = READ_ONCE(mpcs->handle_irq);
	if (!handler)
		return IRQ_NONE;

	return handler(mpcs);
}

static int mv88e639x_pcs_setup_irq(struct mv88e639x_pcs *mpcs,
				   struct mv88e6xxx_chip *chip, int port)
{
	unsigned int irq;

	irq = mv88e6xxx_serdes_irq_mapping(chip, port);
	if (!irq) {
		/* Use polling mode */
		mpcs->sgmii_pcs.poll = true;
		mpcs->xg_pcs.poll = true;
		return 0;
	}

	mpcs->irq = irq;

	return request_threaded_irq(irq, NULL, mv88e639x_pcs_handle_irq,
				    IRQF_ONESHOT, mpcs->name, mpcs);
}

void mv88e639x_pcs_teardown(struct mv88e6xxx_chip *chip, int port)
{
	struct mv88e639x_pcs *mpcs = chip->ports[port].pcs_private;

	if (mpcs && mpcs->irq)
		free_irq(mpcs->irq, mpcs);
}

static void mv88e639x_pcs_link_change(struct mv88e639x_pcs *mpcs,
				      bool link_down)
{
	struct mv88e6xxx_port *port = mpcs->port;

	dsa_port_phylink_mac_change(port->chip->ds, port->port, !link_down);
}

static struct mv88e639x_pcs *sgmii_pcs_to_mv88e639x_pcs(struct phylink_pcs *pcs)
{
	return container_of(pcs, struct mv88e639x_pcs, sgmii_pcs);
}

static irqreturn_t mv88e639x_sgmii_handle_irq(struct mv88e639x_pcs *mpcs)
{
	u16 int_status;
	bool link_down;
	int err;

	err = mv88e639x_read(mpcs, MV88E6390_SGMII_INT_STATUS, &int_status);
	if (err)
		return IRQ_NONE;

	if (int_status & (MV88E6390_SGMII_INT_LINK_DOWN |
			  MV88E6390_SGMII_INT_LINK_UP)) {
		link_down = !!(int_status & MV88E6390_SGMII_INT_LINK_DOWN);

		mv88e639x_pcs_link_change(mpcs, link_down);

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int mv88e639x_sgmii_pcs_control_irq(struct mv88e639x_pcs *mpcs,
					   bool enable)
{
	u16 val = 0;

	if (enable)
		val |= MV88E6390_SGMII_INT_LINK_DOWN |
		       MV88E6390_SGMII_INT_LINK_UP;

	return mv88e639x_modify(mpcs, MV88E6390_SGMII_INT_ENABLE,
				MV88E6390_SGMII_INT_LINK_DOWN |
				MV88E6390_SGMII_INT_LINK_UP, val);
}

static int mv88e639x_sgmii_pcs_enable(struct phylink_pcs *pcs)
{
	struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs);
	int err;

	err = mv88e639x_modify(mpcs, MV88E6390_SGMII_BMCR,
			       BMCR_RESET | BMCR_LOOPBACK | BMCR_PDOWN, 0);
	if (err)
		return err;

	mpcs->handle_irq = mv88e639x_sgmii_handle_irq;

	return mv88e639x_sgmii_pcs_control_irq(mpcs, !!mpcs->irq);
}

static void mv88e639x_sgmii_pcs_disable(struct phylink_pcs *pcs)
{
	struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs);

	mv88e639x_sgmii_pcs_control_irq(mpcs, false);
	mv88e639x_modify(mpcs, MV88E6390_SGMII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
}

static void mv88e639x_sgmii_pcs_get_state(struct phylink_pcs *pcs,
					  struct phylink_link_state *state)
{
	struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs);
	u16 bmsr, lpa, status;
	int err;

	err = mv88e639x_read(mpcs, MV88E6390_SGMII_BMSR, &bmsr);
	if (err) {
		dev_err(mpcs->mdio.dev.parent,
			"can't read Serdes PHY %s: %pe\n",
			"BMSR", ERR_PTR(err));
		state->link = false;
		return;
	}

	err = mv88e639x_read(mpcs, MV88E6390_SGMII_LPA, &lpa);
	if (err) {
		dev_err(mpcs->mdio.dev.parent,
			"can't read Serdes PHY %s: %pe\n",
			"LPA", ERR_PTR(err));
		state->link = false;
		return;
	}

	err = mv88e639x_read(mpcs, MV88E6390_SGMII_PHY_STATUS, &status);
	if (err) {
		dev_err(mpcs->mdio.dev.parent,
			"can't read Serdes PHY %s: %pe\n",
			"status", ERR_PTR(err));
		state->link = false;
		return;
	}

	mv88e6xxx_pcs_decode_state(mpcs->mdio.dev.parent, bmsr, lpa, status,
				   state);
}

static int mv88e639x_sgmii_pcs_config(struct phylink_pcs *pcs,
				      unsigned int mode,
				      phy_interface_t interface,
				      const unsigned long *advertising,
				      bool permit_pause_to_mac)
{
	struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs);
	u16 val, bmcr;
	bool changed;
	int adv, err;

	adv = phylink_mii_c22_pcs_encode_advertisement(interface, advertising);
	if (adv < 0)
		return 0;

	err = mv88e639x_modify_changed(mpcs, MV88E6390_SGMII_ADVERTISE,
				       0xffff, adv);
	if (err < 0)
		return err;

	changed = err > 0;

	err = mv88e639x_read(mpcs, MV88E6390_SGMII_BMCR, &val);
	if (err)
		return err;

	if (phylink_autoneg_inband(mode))
		bmcr = val | BMCR_ANENABLE;
	else
		bmcr = val & ~BMCR_ANENABLE;

	/* setting ANENABLE triggers a restart of negotiation */
	if (bmcr == val)
		return changed;

	return mv88e639x_write(mpcs, MV88E6390_SGMII_BMCR, bmcr);
}

static void mv88e639x_sgmii_pcs_an_restart(struct phylink_pcs *pcs)
{
	struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs);

	mv88e639x_modify(mpcs, MV88E6390_SGMII_BMCR,
			 BMCR_ANRESTART, BMCR_ANRESTART);
}

static void mv88e639x_sgmii_pcs_link_up(struct phylink_pcs *pcs,
					unsigned int mode,
					phy_interface_t interface,
					int speed, int duplex)
{
	struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs);
	u16 bmcr;
	int err;

	if (phylink_autoneg_inband(mode))
		return;

	switch (speed) {
	case SPEED_2500:
	case SPEED_1000:
		bmcr = BMCR_SPEED1000;
		break;

	case SPEED_100:
		bmcr = BMCR_SPEED100;
		break;

	case SPEED_10:
	default:
		bmcr = 0;
		break;
	}

	if (duplex == DUPLEX_FULL)
		bmcr |= BMCR_FULLDPLX;

	err = mv88e639x_modify(mpcs, MV88E6390_SGMII_BMCR,
			       BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX,
			       bmcr);
	if (err)
		dev_err(mpcs->mdio.dev.parent,
			"can't access Serdes PHY %s: %pe\n",
			"BMCR", ERR_PTR(err));
}

static const struct phylink_pcs_ops mv88e639x_sgmii_pcs_ops = {
	.pcs_enable = mv88e639x_sgmii_pcs_enable,
	.pcs_disable = mv88e639x_sgmii_pcs_disable,
	.pcs_get_state = mv88e639x_sgmii_pcs_get_state,
	.pcs_an_restart = mv88e639x_sgmii_pcs_an_restart,
	.pcs_config = mv88e639x_sgmii_pcs_config,
	.pcs_link_up = mv88e639x_sgmii_pcs_link_up,
};

static struct mv88e639x_pcs *xg_pcs_to_mv88e639x_pcs(struct phylink_pcs *pcs)
{
	return container_of(pcs, struct mv88e639x_pcs, xg_pcs);
}

static int mv88e639x_xg_pcs_enable(struct mv88e639x_pcs *mpcs)
{
	return mv88e639x_modify(mpcs, MV88E6390_10G_CTRL1,
				MDIO_CTRL1_RESET | MDIO_PCS_CTRL1_LOOPBACK |
				MDIO_CTRL1_LPOWER, 0);
}

static void mv88e639x_xg_pcs_disable(struct mv88e639x_pcs *mpcs)
{
	mv88e639x_modify(mpcs, MV88E6390_10G_CTRL1, MDIO_CTRL1_LPOWER,
			 MDIO_CTRL1_LPOWER);
}

static void mv88e639x_xg_pcs_get_state(struct phylink_pcs *pcs,
				      struct phylink_link_state *state)
{
	struct mv88e639x_pcs *mpcs = xg_pcs_to_mv88e639x_pcs(pcs);
	u16 status;
	int err;

	state->link = false;

	err = mv88e639x_read(mpcs, MV88E6390_10G_STAT1, &status);
	if (err) {
		dev_err(mpcs->mdio.dev.parent,
			"can't access Serdes PHY %s: %pe\n",
			"STAT1", ERR_PTR(err));
		return;
	}

	state->link = !!(status & MDIO_STAT1_LSTATUS);
	if (state->link) {
		switch (state->interface) {
		case PHY_INTERFACE_MODE_5GBASER:
			state->speed = SPEED_5000;
			break;

		case PHY_INTERFACE_MODE_10GBASER:
		case PHY_INTERFACE_MODE_RXAUI:
		case PHY_INTERFACE_MODE_XAUI:
			state->speed = SPEED_10000;
			break;

		default:
			state->link = false;
			return;
		}

		state->duplex = DUPLEX_FULL;
	}
}

static int mv88e639x_xg_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
				  phy_interface_t interface,
				  const unsigned long *advertising,
				  bool permit_pause_to_mac)
{
	return 0;
}

struct phylink_pcs *mv88e639x_pcs_select(struct mv88e6xxx_chip *chip, int port,
					 phy_interface_t mode)
{
	struct mv88e639x_pcs *mpcs;
	struct mv88e6xxx_port *p;

	p = &chip->ports[port];
	mpcs = p->pcs_private;
	if (!mpcs)
		return NULL;

	switch (mode) {
	case PHY_INTERFACE_MODE_SGMII:
	case PHY_INTERFACE_MODE_1000BASEX:
	case PHY_INTERFACE_MODE_2500BASEX:
		return &mpcs->sgmii_pcs;

	case PHY_INTERFACE_MODE_10GBASER:
	case PHY_INTERFACE_MODE_XAUI:
	case PHY_INTERFACE_MODE_RXAUI:
		return &mpcs->xg_pcs;

	default:
		return NULL;
	}
}


/* Marvell 88E6390 Specific support */

static irqreturn_t mv88e6390_xg_handle_irq(struct mv88e639x_pcs *mpcs)
{
	u16 int_status;
	bool link_down;
	int err;

	err = mv88e639x_read(mpcs, MV88E6390_10G_INT_STATUS, &int_status);
	if (err)
		return IRQ_NONE;

	if (int_status & (MV88E6390_10G_INT_LINK_DOWN |
			  MV88E6390_10G_INT_LINK_UP)) {
		link_down = !!(int_status & MV88E6390_10G_INT_LINK_DOWN);

		mv88e639x_pcs_link_change(mpcs, link_down);

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int mv88e6390_xg_control_irq(struct mv88e639x_pcs *mpcs, bool enable)
{
	u16 val = 0;

	if (enable)
		val = MV88E6390_10G_INT_LINK_DOWN | MV88E6390_10G_INT_LINK_UP;

	return mv88e639x_modify(mpcs, MV88E6390_10G_INT_ENABLE,
				MV88E6390_10G_INT_LINK_DOWN |
				MV88E6390_10G_INT_LINK_UP, val);
}

static int mv88e6390_xg_pcs_enable(struct phylink_pcs *pcs)
{
	struct mv88e639x_pcs *mpcs = xg_pcs_to_mv88e639x_pcs(pcs);
	int err;

	err = mv88e639x_xg_pcs_enable(mpcs);
	if (err)
		return err;

	mpcs->handle_irq = mv88e6390_xg_handle_irq;

	return mv88e6390_xg_control_irq(mpcs, !!mpcs->irq);
}

static void mv88e6390_xg_pcs_disable(struct phylink_pcs *pcs)
{
	struct mv88e639x_pcs *mpcs = xg_pcs_to_mv88e639x_pcs(pcs);

	mv88e6390_xg_control_irq(mpcs, false);
	mv88e639x_xg_pcs_disable(mpcs);
}

static const struct phylink_pcs_ops mv88e6390_xg_pcs_ops = {
	.pcs_enable = mv88e6390_xg_pcs_enable,
	.pcs_disable = mv88e6390_xg_pcs_disable,
	.pcs_get_state = mv88e639x_xg_pcs_get_state,
	.pcs_config = mv88e639x_xg_pcs_config,
};

static int mv88e6390_pcs_enable_checker(struct mv88e639x_pcs *mpcs)
{
	return mv88e639x_modify(mpcs, MV88E6390_PG_CONTROL,
				MV88E6390_PG_CONTROL_ENABLE_PC,
				MV88E6390_PG_CONTROL_ENABLE_PC);
}

int mv88e6390_pcs_init(struct mv88e6xxx_chip *chip, int port)
{
	struct mv88e639x_pcs *mpcs;
	struct mii_bus *bus;
	struct device *dev;
	int lane, err;

	lane = mv88e6xxx_serdes_get_lane(chip, port);
	if (lane < 0)
		return 0;

	bus = mv88e6xxx_default_mdio_bus(chip);
	dev = chip->dev;

	mpcs = mv88e639x_pcs_alloc(dev, bus, lane, port);
	if (!mpcs)
		return -ENOMEM;

	mpcs->port = &chip->ports[port];
	mpcs->sgmii_pcs.ops = &mv88e639x_sgmii_pcs_ops;
	mpcs->xg_pcs.ops = &mv88e6390_xg_pcs_ops;

	err = mv88e639x_pcs_setup_irq(mpcs, chip, port);
	if (err)
		return err;

	/* 6390 and 6380x has the checker, 6393 doesn't appear to? */
	/* This is to enable gathering the statistics. Maybe this
	 * should call out to a helper? Or we could do this at init time.
	 */
	err = mv88e6390_pcs_enable_checker(mpcs);
	if (err)
		return err;

	mpcs->port->pcs_private = mpcs;

	return 0;
}


/* Marvell 88E6393X Specific support */

static irqreturn_t mv88e6393x_xg_handle_irq(struct mv88e639x_pcs *mpcs)
{
	u16 int_status, stat1;
	bool link_down;
	int err;

	err = mv88e639x_read(mpcs, MV88E6393X_10G_INT_STATUS, &int_status);
	if (err)
		return IRQ_NONE;

	if (int_status & MV88E6393X_10G_INT_LINK_CHANGE) {
		err = mv88e639x_read(mpcs, MV88E6390_10G_STAT1, &stat1);
		if (err)
			return IRQ_NONE;

		link_down = !(stat1 & MDIO_STAT1_LSTATUS);

		mv88e639x_pcs_link_change(mpcs, link_down);

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int mv88e6393x_xg_control_irq(struct mv88e639x_pcs *mpcs, bool enable)
{
	u16 val = 0;

	if (enable)
		val = MV88E6393X_10G_INT_LINK_CHANGE;

	return mv88e639x_modify(mpcs, MV88E6393X_10G_INT_ENABLE,
				MV88E6393X_10G_INT_LINK_CHANGE, val);
}

static int mv88e6393x_xg_pcs_enable(struct phylink_pcs *pcs)
{
	struct mv88e639x_pcs *mpcs = xg_pcs_to_mv88e639x_pcs(pcs);
	int err;

	err = mv88e639x_xg_pcs_enable(mpcs);
	if (err)
		return err;

	mpcs->handle_irq = mv88e6393x_xg_handle_irq;

	return mv88e6393x_xg_control_irq(mpcs, !!mpcs->irq);
}

static void mv88e6393x_xg_pcs_disable(struct phylink_pcs *pcs)
{
	struct mv88e639x_pcs *mpcs = xg_pcs_to_mv88e639x_pcs(pcs);

	mv88e6393x_xg_control_irq(mpcs, false);
	mv88e639x_xg_pcs_disable(mpcs);
}

static const struct phylink_pcs_ops mv88e6393x_xg_pcs_ops = {
	.pcs_enable = mv88e6393x_xg_pcs_enable,
	.pcs_disable = mv88e6393x_xg_pcs_disable,
	.pcs_get_state = mv88e639x_xg_pcs_get_state,
	.pcs_config = mv88e639x_xg_pcs_config,
};

int mv88e6393x_pcs_init(struct mv88e6xxx_chip *chip, int port)
{
	struct mv88e639x_pcs *mpcs;
	struct mii_bus *bus;
	struct device *dev;
	int lane, err;

	lane = mv88e6xxx_serdes_get_lane(chip, port);
	if (lane < 0)
		return 0;

	bus = mv88e6xxx_default_mdio_bus(chip);
	dev = chip->dev;

	mpcs = mv88e639x_pcs_alloc(dev, bus, lane, port);
	if (!mpcs)
		return -ENOMEM;

	mpcs->port = &chip->ports[port];
	mpcs->sgmii_pcs.ops = &mv88e639x_sgmii_pcs_ops;
	mpcs->xg_pcs.ops = &mv88e6393x_xg_pcs_ops;

	err = mv88e639x_pcs_setup_irq(mpcs, chip, port);
	if (err)
		return err;

	mpcs->port->pcs_private = mpcs;

	return 0;
}