summaryrefslogtreecommitdiff
path: root/drivers/net/mv643xx_eth.c
blob: 8fbba21d975bc4ad7cbde8dcb9d1998acf3501a3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
/*
 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
 *
 * Based on the 64360 driver from:
 * Copyright (C) 2002 rabeeh@galileo.co.il
 *
 * Copyright (C) 2003 PMC-Sierra, Inc.,
 *	written by Manish Lachwani (lachwani@pmc-sierra.com)
 *
 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
 *
 * Copyright (C) 2004-2005 MontaVista Software, Inc.
 *			   Dale Farnsworth <dale@farnsworth.org>
 *
 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
 *				     <sjhill@realitydiluted.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/tcp.h>
#include <linux/udp.h>
#include <linux/etherdevice.h>

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <asm/io.h>
#include <asm/types.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/delay.h>
#include "mv643xx_eth.h"

/*
 * The first part is the high level driver of the gigE ethernet ports.
 */

/* Constants */
#define VLAN_HLEN		4
#define FCS_LEN			4
#define WRAP			NET_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
#define RX_SKB_SIZE		((dev->mtu + WRAP + 7) & ~0x7)

#define INT_CAUSE_UNMASK_ALL		0x0007ffff
#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
#define INT_CAUSE_MASK_ALL		0x00000000
#define INT_CAUSE_MASK_ALL_EXT		0x00000000
#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT

#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
#define MAX_DESCS_PER_SKB	(MAX_SKB_FRAGS + 1)
#else
#define MAX_DESCS_PER_SKB	1
#endif

#define PHY_WAIT_ITERATIONS	1000	/* 1000 iterations * 10uS = 10mS max */
#define PHY_WAIT_MICRO_SECONDS	10

/* Static function declarations */
static int eth_port_link_is_up(unsigned int eth_port_num);
static void eth_port_uc_addr_get(struct net_device *dev,
						unsigned char *MacAddr);
static int mv643xx_eth_real_open(struct net_device *);
static int mv643xx_eth_real_stop(struct net_device *);
static int mv643xx_eth_change_mtu(struct net_device *, int);
static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
static void eth_port_init_mac_tables(unsigned int eth_port_num);
#ifdef MV643XX_NAPI
static int mv643xx_poll(struct net_device *dev, int *budget);
#endif
static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
static int ethernet_phy_detect(unsigned int eth_port_num);
static struct ethtool_ops mv643xx_ethtool_ops;

static char mv643xx_driver_name[] = "mv643xx_eth";
static char mv643xx_driver_version[] = "1.0";

static void __iomem *mv643xx_eth_shared_base;

/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);

static inline u32 mv_read(int offset)
{
	void __iomem *reg_base;

	reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;

	return readl(reg_base + offset);
}

static inline void mv_write(int offset, u32 data)
{
	void __iomem *reg_base;

	reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
	writel(data, reg_base + offset);
}

/*
 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
 *
 * Input :	pointer to ethernet interface network device structure
 *		new mtu size
 * Output :	0 upon success, -EINVAL upon failure
 */
static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	unsigned long flags;

	spin_lock_irqsave(&mp->lock, flags);

	if ((new_mtu > 9500) || (new_mtu < 64)) {
		spin_unlock_irqrestore(&mp->lock, flags);
		return -EINVAL;
	}

	dev->mtu = new_mtu;
	/*
	 * Stop then re-open the interface. This will allocate RX skb's with
	 * the new MTU.
	 * There is a possible danger that the open will not successed, due
	 * to memory is full, which might fail the open function.
	 */
	if (netif_running(dev)) {
		if (mv643xx_eth_real_stop(dev))
			printk(KERN_ERR
				"%s: Fatal error on stopping device\n",
				dev->name);
		if (mv643xx_eth_real_open(dev))
			printk(KERN_ERR
				"%s: Fatal error on opening device\n",
				dev->name);
	}

	spin_unlock_irqrestore(&mp->lock, flags);
	return 0;
}

/*
 * mv643xx_eth_rx_task
 *
 * Fills / refills RX queue on a certain gigabit ethernet port
 *
 * Input :	pointer to ethernet interface network device structure
 * Output :	N/A
 */
static void mv643xx_eth_rx_task(void *data)
{
	struct net_device *dev = (struct net_device *)data;
	struct mv643xx_private *mp = netdev_priv(dev);
	struct pkt_info pkt_info;
	struct sk_buff *skb;

	if (test_and_set_bit(0, &mp->rx_task_busy))
		panic("%s: Error in test_set_bit / clear_bit", dev->name);

	while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
		skb = dev_alloc_skb(RX_SKB_SIZE);
		if (!skb)
			break;
		mp->rx_ring_skbs++;
		pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
		pkt_info.byte_cnt = RX_SKB_SIZE;
		pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
							DMA_FROM_DEVICE);
		pkt_info.return_info = skb;
		if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
			printk(KERN_ERR
				"%s: Error allocating RX Ring\n", dev->name);
			break;
		}
		skb_reserve(skb, 2);
	}
	clear_bit(0, &mp->rx_task_busy);
	/*
	 * If RX ring is empty of SKB, set a timer to try allocating
	 * again in a later time .
	 */
	if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
		printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
		/* After 100mSec */
		mp->timeout.expires = jiffies + (HZ / 10);
		add_timer(&mp->timeout);
		mp->rx_timer_flag = 1;
	}
#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
	else {
		/* Return interrupts */
		mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
							INT_CAUSE_UNMASK_ALL);
	}
#endif
}

/*
 * mv643xx_eth_rx_task_timer_wrapper
 *
 * Timer routine to wake up RX queue filling task. This function is
 * used only in case the RX queue is empty, and all alloc_skb has
 * failed (due to out of memory event).
 *
 * Input :	pointer to ethernet interface network device structure
 * Output :	N/A
 */
static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
{
	struct net_device *dev = (struct net_device *)data;
	struct mv643xx_private *mp = netdev_priv(dev);

	mp->rx_timer_flag = 0;
	mv643xx_eth_rx_task((void *)data);
}

/*
 * mv643xx_eth_update_mac_address
 *
 * Update the MAC address of the port in the address table
 *
 * Input :	pointer to ethernet interface network device structure
 * Output :	N/A
 */
static void mv643xx_eth_update_mac_address(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	unsigned int port_num = mp->port_num;

	eth_port_init_mac_tables(port_num);
	memcpy(mp->port_mac_addr, dev->dev_addr, 6);
	eth_port_uc_addr_set(port_num, mp->port_mac_addr);
}

/*
 * mv643xx_eth_set_rx_mode
 *
 * Change from promiscuos to regular rx mode
 *
 * Input :	pointer to ethernet interface network device structure
 * Output :	N/A
 */
static void mv643xx_eth_set_rx_mode(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);

	if (dev->flags & IFF_PROMISC)
		mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
	else
		mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;

	mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
}

/*
 * mv643xx_eth_set_mac_address
 *
 * Change the interface's mac address.
 * No special hardware thing should be done because interface is always
 * put in promiscuous mode.
 *
 * Input :	pointer to ethernet interface network device structure and
 *		a pointer to the designated entry to be added to the cache.
 * Output :	zero upon success, negative upon failure
 */
static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
{
	int i;

	for (i = 0; i < 6; i++)
		/* +2 is for the offset of the HW addr type */
		dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
	mv643xx_eth_update_mac_address(dev);
	return 0;
}

/*
 * mv643xx_eth_tx_timeout
 *
 * Called upon a timeout on transmitting a packet
 *
 * Input :	pointer to ethernet interface network device structure.
 * Output :	N/A
 */
static void mv643xx_eth_tx_timeout(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);

	printk(KERN_INFO "%s: TX timeout  ", dev->name);

	/* Do the reset outside of interrupt context */
	schedule_work(&mp->tx_timeout_task);
}

/*
 * mv643xx_eth_tx_timeout_task
 *
 * Actual routine to reset the adapter when a timeout on Tx has occurred
 */
static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);

	netif_device_detach(dev);
	eth_port_reset(mp->port_num);
	eth_port_start(mp);
	netif_device_attach(dev);
}

/*
 * mv643xx_eth_free_tx_queue
 *
 * Input :	dev - a pointer to the required interface
 *
 * Output :	0 if was able to release skb , nonzero otherwise
 */
static int mv643xx_eth_free_tx_queue(struct net_device *dev,
					unsigned int eth_int_cause_ext)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	struct net_device_stats *stats = &mp->stats;
	struct pkt_info pkt_info;
	int released = 1;

	if (!(eth_int_cause_ext & (BIT0 | BIT8)))
		return released;

	spin_lock(&mp->lock);

	/* Check only queue 0 */
	while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
		if (pkt_info.cmd_sts & BIT0) {
			printk("%s: Error in TX\n", dev->name);
			stats->tx_errors++;
		}

		/*
		 * If return_info is different than 0, release the skb.
		 * The case where return_info is not 0 is only in case
		 * when transmitted a scatter/gather packet, where only
		 * last skb releases the whole chain.
		 */
		if (pkt_info.return_info) {
			if (skb_shinfo(pkt_info.return_info)->nr_frags)
				dma_unmap_page(NULL, pkt_info.buf_ptr,
						pkt_info.byte_cnt,
						DMA_TO_DEVICE);
			else
				dma_unmap_single(NULL, pkt_info.buf_ptr,
						pkt_info.byte_cnt,
						DMA_TO_DEVICE);

			dev_kfree_skb_irq(pkt_info.return_info);
			released = 0;
		} else
			dma_unmap_page(NULL, pkt_info.buf_ptr,
					pkt_info.byte_cnt, DMA_TO_DEVICE);
	}

	spin_unlock(&mp->lock);

	return released;
}

/*
 * mv643xx_eth_receive
 *
 * This function is forward packets that are received from the port's
 * queues toward kernel core or FastRoute them to another interface.
 *
 * Input :	dev - a pointer to the required interface
 *		max - maximum number to receive (0 means unlimted)
 *
 * Output :	number of served packets
 */
#ifdef MV643XX_NAPI
static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
#else
static int mv643xx_eth_receive_queue(struct net_device *dev)
#endif
{
	struct mv643xx_private *mp = netdev_priv(dev);
	struct net_device_stats *stats = &mp->stats;
	unsigned int received_packets = 0;
	struct sk_buff *skb;
	struct pkt_info pkt_info;

#ifdef MV643XX_NAPI
	while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
#else
	while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
#endif
		mp->rx_ring_skbs--;
		received_packets++;

		/* Update statistics. Note byte count includes 4 byte CRC count */
		stats->rx_packets++;
		stats->rx_bytes += pkt_info.byte_cnt;
		skb = pkt_info.return_info;
		/*
		 * In case received a packet without first / last bits on OR
		 * the error summary bit is on, the packets needs to be dropeed.
		 */
		if (((pkt_info.cmd_sts
				& (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
					(ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
				|| (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
			stats->rx_dropped++;
			if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
							ETH_RX_LAST_DESC)) !=
				(ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
				if (net_ratelimit())
					printk(KERN_ERR
						"%s: Received packet spread "
						"on multiple descriptors\n",
						dev->name);
			}
			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
				stats->rx_errors++;

			dev_kfree_skb_irq(skb);
		} else {
			/*
			 * The -4 is for the CRC in the trailer of the
			 * received packet
			 */
			skb_put(skb, pkt_info.byte_cnt - 4);
			skb->dev = dev;

			if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
				skb->ip_summed = CHECKSUM_UNNECESSARY;
				skb->csum = htons(
					(pkt_info.cmd_sts & 0x0007fff8) >> 3);
			}
			skb->protocol = eth_type_trans(skb, dev);
#ifdef MV643XX_NAPI
			netif_receive_skb(skb);
#else
			netif_rx(skb);
#endif
		}
	}

	return received_packets;
}

/*
 * mv643xx_eth_int_handler
 *
 * Main interrupt handler for the gigbit ethernet ports
 *
 * Input :	irq	- irq number (not used)
 *		dev_id	- a pointer to the required interface's data structure
 *		regs	- not used
 * Output :	N/A
 */

static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
							struct pt_regs *regs)
{
	struct net_device *dev = (struct net_device *)dev_id;
	struct mv643xx_private *mp = netdev_priv(dev);
	u32 eth_int_cause, eth_int_cause_ext = 0;
	unsigned int port_num = mp->port_num;

	/* Read interrupt cause registers */
	eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
						INT_CAUSE_UNMASK_ALL;

	if (eth_int_cause & BIT1)
		eth_int_cause_ext = mv_read(
			MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
						INT_CAUSE_UNMASK_ALL_EXT;

#ifdef MV643XX_NAPI
	if (!(eth_int_cause & 0x0007fffd)) {
		/* Dont ack the Rx interrupt */
#endif
		/*
		 * Clear specific ethernet port intrerrupt registers by
		 * acknowleding relevant bits.
		 */
		mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
							~eth_int_cause);
		if (eth_int_cause_ext != 0x0)
			mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
					(port_num), ~eth_int_cause_ext);

		/* UDP change : We may need this */
		if ((eth_int_cause_ext & 0x0000ffff) &&
		    (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
		    (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
			netif_wake_queue(dev);
#ifdef MV643XX_NAPI
	} else {
		if (netif_rx_schedule_prep(dev)) {
			/* Mask all the interrupts */
			mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
			mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
								(port_num), 0);
			__netif_rx_schedule(dev);
		}
#else
		if (eth_int_cause & (BIT2 | BIT11))
			mv643xx_eth_receive_queue(dev, 0);

		/*
		 * After forwarded received packets to upper layer, add a task
		 * in an interrupts enabled context that refills the RX ring
		 * with skb's.
		 */
#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
		/* Unmask all interrupts on ethernet port */
		mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
							INT_CAUSE_MASK_ALL);
		queue_task(&mp->rx_task, &tq_immediate);
		mark_bh(IMMEDIATE_BH);
#else
		mp->rx_task.func(dev);
#endif
#endif
	}
	/* PHY status changed */
	if (eth_int_cause_ext & (BIT16 | BIT20)) {
		if (eth_port_link_is_up(port_num)) {
			netif_carrier_on(dev);
			netif_wake_queue(dev);
			/* Start TX queue */
			mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
								(port_num), 1);
		} else {
			netif_carrier_off(dev);
			netif_stop_queue(dev);
		}
	}

	/*
	 * If no real interrupt occured, exit.
	 * This can happen when using gigE interrupt coalescing mechanism.
	 */
	if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
		return IRQ_NONE;

	return IRQ_HANDLED;
}

#ifdef MV643XX_COAL

/*
 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
 *
 * DESCRIPTION:
 *	This routine sets the RX coalescing interrupt mechanism parameter.
 *	This parameter is a timeout counter, that counts in 64 t_clk
 *	chunks ; that when timeout event occurs a maskable interrupt
 *	occurs.
 *	The parameter is calculated using the tClk of the MV-643xx chip
 *	, and the required delay of the interrupt in usec.
 *
 * INPUT:
 *	unsigned int eth_port_num	Ethernet port number
 *	unsigned int t_clk		t_clk of the MV-643xx chip in HZ units
 *	unsigned int delay		Delay in usec
 *
 * OUTPUT:
 *	Interrupt coalescing mechanism value is set in MV-643xx chip.
 *
 * RETURN:
 *	The interrupt coalescing value set in the gigE port.
 *
 */
static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
					unsigned int t_clk, unsigned int delay)
{
	unsigned int coal = ((t_clk / 1000000) * delay) / 64;

	/* Set RX Coalescing mechanism */
	mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
		((coal & 0x3fff) << 8) |
		(mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
			& 0xffc000ff));

	return coal;
}
#endif

/*
 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
 *
 * DESCRIPTION:
 *	This routine sets the TX coalescing interrupt mechanism parameter.
 *	This parameter is a timeout counter, that counts in 64 t_clk
 *	chunks ; that when timeout event occurs a maskable interrupt
 *	occurs.
 *	The parameter is calculated using the t_cLK frequency of the
 *	MV-643xx chip and the required delay in the interrupt in uSec
 *
 * INPUT:
 *	unsigned int eth_port_num	Ethernet port number
 *	unsigned int t_clk		t_clk of the MV-643xx chip in HZ units
 *	unsigned int delay		Delay in uSeconds
 *
 * OUTPUT:
 *	Interrupt coalescing mechanism value is set in MV-643xx chip.
 *
 * RETURN:
 *	The interrupt coalescing value set in the gigE port.
 *
 */
static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
					unsigned int t_clk, unsigned int delay)
{
	unsigned int coal;
	coal = ((t_clk / 1000000) * delay) / 64;
	/* Set TX Coalescing mechanism */
	mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
								coal << 4);
	return coal;
}

/*
 * mv643xx_eth_open
 *
 * This function is called when openning the network device. The function
 * should initialize all the hardware, initialize cyclic Rx/Tx
 * descriptors chain and buffers and allocate an IRQ to the network
 * device.
 *
 * Input :	a pointer to the network device structure
 *
 * Output :	zero of success , nonzero if fails.
 */

static int mv643xx_eth_open(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	unsigned int port_num = mp->port_num;
	int err;

	spin_lock_irq(&mp->lock);

	err = request_irq(dev->irq, mv643xx_eth_int_handler,
			SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);

	if (err) {
		printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
								port_num);
		err = -EAGAIN;
		goto out;
	}

	if (mv643xx_eth_real_open(dev)) {
		printk("%s: Error opening interface\n", dev->name);
		err = -EBUSY;
		goto out_free;
	}

	spin_unlock_irq(&mp->lock);

	return 0;

out_free:
	free_irq(dev->irq, dev);

out:
	spin_unlock_irq(&mp->lock);

	return err;
}

/*
 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
 *
 * DESCRIPTION:
 *	This function prepares a Rx chained list of descriptors and packet
 *	buffers in a form of a ring. The routine must be called after port
 *	initialization routine and before port start routine.
 *	The Ethernet SDMA engine uses CPU bus addresses to access the various
 *	devices in the system (i.e. DRAM). This function uses the ethernet
 *	struct 'virtual to physical' routine (set by the user) to set the ring
 *	with physical addresses.
 *
 * INPUT:
 *	struct mv643xx_private *mp	Ethernet Port Control srtuct.
 *
 * OUTPUT:
 *	The routine updates the Ethernet port control struct with information
 *	regarding the Rx descriptors and buffers.
 *
 * RETURN:
 *	None.
 */
static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
{
	volatile struct eth_rx_desc *p_rx_desc;
	int rx_desc_num = mp->rx_ring_size;
	int i;

	/* initialize the next_desc_ptr links in the Rx descriptors ring */
	p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
	for (i = 0; i < rx_desc_num; i++) {
		p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
			((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
	}

	/* Save Rx desc pointer to driver struct. */
	mp->rx_curr_desc_q = 0;
	mp->rx_used_desc_q = 0;

	mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);

	/* Add the queue to the list of RX queues of this port */
	mp->port_rx_queue_command |= 1;
}

/*
 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
 *
 * DESCRIPTION:
 *	This function prepares a Tx chained list of descriptors and packet
 *	buffers in a form of a ring. The routine must be called after port
 *	initialization routine and before port start routine.
 *	The Ethernet SDMA engine uses CPU bus addresses to access the various
 *	devices in the system (i.e. DRAM). This function uses the ethernet
 *	struct 'virtual to physical' routine (set by the user) to set the ring
 *	with physical addresses.
 *
 * INPUT:
 *	struct mv643xx_private *mp	Ethernet Port Control srtuct.
 *
 * OUTPUT:
 *	The routine updates the Ethernet port control struct with information
 *	regarding the Tx descriptors and buffers.
 *
 * RETURN:
 *	None.
 */
static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
{
	int tx_desc_num = mp->tx_ring_size;
	struct eth_tx_desc *p_tx_desc;
	int i;

	/* Initialize the next_desc_ptr links in the Tx descriptors ring */
	p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
	for (i = 0; i < tx_desc_num; i++) {
		p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
			((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
	}

	mp->tx_curr_desc_q = 0;
	mp->tx_used_desc_q = 0;
#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
	mp->tx_first_desc_q = 0;
#endif

	mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);

	/* Add the queue to the list of Tx queues of this port */
	mp->port_tx_queue_command |= 1;
}

/* Helper function for mv643xx_eth_open */
static int mv643xx_eth_real_open(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	unsigned int port_num = mp->port_num;
	unsigned int size;

	/* Stop RX Queues */
	mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);

	/* Clear the ethernet port interrupts */
	mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
	mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);

	/* Unmask RX buffer and TX end interrupt */
	mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
						INT_CAUSE_UNMASK_ALL);

	/* Unmask phy and link status changes interrupts */
	mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
						INT_CAUSE_UNMASK_ALL_EXT);

	/* Set the MAC Address */
	memcpy(mp->port_mac_addr, dev->dev_addr, 6);

	eth_port_init(mp);

	INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);

	memset(&mp->timeout, 0, sizeof(struct timer_list));
	mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
	mp->timeout.data = (unsigned long)dev;

	mp->rx_task_busy = 0;
	mp->rx_timer_flag = 0;

	/* Allocate RX and TX skb rings */
	mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
								GFP_KERNEL);
	if (!mp->rx_skb) {
		printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
		return -ENOMEM;
	}
	mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
								GFP_KERNEL);
	if (!mp->tx_skb) {
		printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
		kfree(mp->rx_skb);
		return -ENOMEM;
	}

	/* Allocate TX ring */
	mp->tx_ring_skbs = 0;
	size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
	mp->tx_desc_area_size = size;

	if (mp->tx_sram_size) {
		mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
							mp->tx_sram_size);
		mp->tx_desc_dma = mp->tx_sram_addr;
	} else
		mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
							&mp->tx_desc_dma,
							GFP_KERNEL);

	if (!mp->p_tx_desc_area) {
		printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
							dev->name, size);
		kfree(mp->rx_skb);
		kfree(mp->tx_skb);
		return -ENOMEM;
	}
	BUG_ON((u32) mp->p_tx_desc_area & 0xf);	/* check 16-byte alignment */
	memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);

	ether_init_tx_desc_ring(mp);

	/* Allocate RX ring */
	mp->rx_ring_skbs = 0;
	size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
	mp->rx_desc_area_size = size;

	if (mp->rx_sram_size) {
		mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
							mp->rx_sram_size);
		mp->rx_desc_dma = mp->rx_sram_addr;
	} else
		mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
							&mp->rx_desc_dma,
							GFP_KERNEL);

	if (!mp->p_rx_desc_area) {
		printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
							dev->name, size);
		printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
							dev->name);
		if (mp->rx_sram_size)
			iounmap(mp->p_rx_desc_area);
		else
			dma_free_coherent(NULL, mp->tx_desc_area_size,
					mp->p_tx_desc_area, mp->tx_desc_dma);
		kfree(mp->rx_skb);
		kfree(mp->tx_skb);
		return -ENOMEM;
	}
	memset((void *)mp->p_rx_desc_area, 0, size);

	ether_init_rx_desc_ring(mp);

	mv643xx_eth_rx_task(dev);	/* Fill RX ring with skb's */

	eth_port_start(mp);

	/* Interrupt Coalescing */

#ifdef MV643XX_COAL
	mp->rx_int_coal =
		eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
#endif

	mp->tx_int_coal =
		eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);

	netif_start_queue(dev);

	return 0;
}

static void mv643xx_eth_free_tx_rings(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	unsigned int port_num = mp->port_num;
	unsigned int curr;

	/* Stop Tx Queues */
	mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);

	/* Free outstanding skb's on TX rings */
	for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
		if (mp->tx_skb[curr]) {
			dev_kfree_skb(mp->tx_skb[curr]);
			mp->tx_ring_skbs--;
		}
	}
	if (mp->tx_ring_skbs)
		printk("%s: Error on Tx descriptor free - could not free %d"
				" descriptors\n", dev->name, mp->tx_ring_skbs);

	/* Free TX ring */
	if (mp->tx_sram_size)
		iounmap(mp->p_tx_desc_area);
	else
		dma_free_coherent(NULL, mp->tx_desc_area_size,
				mp->p_tx_desc_area, mp->tx_desc_dma);
}

static void mv643xx_eth_free_rx_rings(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	unsigned int port_num = mp->port_num;
	int curr;

	/* Stop RX Queues */
	mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);

	/* Free preallocated skb's on RX rings */
	for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
		if (mp->rx_skb[curr]) {
			dev_kfree_skb(mp->rx_skb[curr]);
			mp->rx_ring_skbs--;
		}
	}

	if (mp->rx_ring_skbs)
		printk(KERN_ERR
			"%s: Error in freeing Rx Ring. %d skb's still"
			" stuck in RX Ring - ignoring them\n", dev->name,
			mp->rx_ring_skbs);
	/* Free RX ring */
	if (mp->rx_sram_size)
		iounmap(mp->p_rx_desc_area);
	else
		dma_free_coherent(NULL, mp->rx_desc_area_size,
				mp->p_rx_desc_area, mp->rx_desc_dma);
}

/*
 * mv643xx_eth_stop
 *
 * This function is used when closing the network device.
 * It updates the hardware,
 * release all memory that holds buffers and descriptors and release the IRQ.
 * Input :	a pointer to the device structure
 * Output :	zero if success , nonzero if fails
 */

/* Helper function for mv643xx_eth_stop */

static int mv643xx_eth_real_stop(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	unsigned int port_num = mp->port_num;

	netif_carrier_off(dev);
	netif_stop_queue(dev);

	mv643xx_eth_free_tx_rings(dev);
	mv643xx_eth_free_rx_rings(dev);

	eth_port_reset(mp->port_num);

	/* Disable ethernet port interrupts */
	mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
	mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);

	/* Mask RX buffer and TX end interrupt */
	mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);

	/* Mask phy and link status changes interrupts */
	mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);

	return 0;
}

static int mv643xx_eth_stop(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);

	spin_lock_irq(&mp->lock);

	mv643xx_eth_real_stop(dev);

	free_irq(dev->irq, dev);
	spin_unlock_irq(&mp->lock);

	return 0;
}

#ifdef MV643XX_NAPI
static void mv643xx_tx(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	struct pkt_info pkt_info;

	while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
		if (pkt_info.return_info) {
			if (skb_shinfo(pkt_info.return_info)->nr_frags)
				dma_unmap_page(NULL, pkt_info.buf_ptr,
						pkt_info.byte_cnt,
						DMA_TO_DEVICE);
			else
				dma_unmap_single(NULL, pkt_info.buf_ptr,
						pkt_info.byte_cnt,
						DMA_TO_DEVICE);

			dev_kfree_skb_irq(pkt_info.return_info);
		} else
			dma_unmap_page(NULL, pkt_info.buf_ptr,
					pkt_info.byte_cnt, DMA_TO_DEVICE);
	}

	if (netif_queue_stopped(dev) &&
			mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
		netif_wake_queue(dev);
}

/*
 * mv643xx_poll
 *
 * This function is used in case of NAPI
 */
static int mv643xx_poll(struct net_device *dev, int *budget)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	int done = 1, orig_budget, work_done;
	unsigned int port_num = mp->port_num;
	unsigned long flags;

#ifdef MV643XX_TX_FAST_REFILL
	if (++mp->tx_clean_threshold > 5) {
		spin_lock_irqsave(&mp->lock, flags);
		mv643xx_tx(dev);
		mp->tx_clean_threshold = 0;
		spin_unlock_irqrestore(&mp->lock, flags);
	}
#endif

	if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
						!= (u32) mp->rx_used_desc_q) {
		orig_budget = *budget;
		if (orig_budget > dev->quota)
			orig_budget = dev->quota;
		work_done = mv643xx_eth_receive_queue(dev, orig_budget);
		mp->rx_task.func(dev);
		*budget -= work_done;
		dev->quota -= work_done;
		if (work_done >= orig_budget)
			done = 0;
	}

	if (done) {
		spin_lock_irqsave(&mp->lock, flags);
		__netif_rx_complete(dev);
		mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
		mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
		mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
						INT_CAUSE_UNMASK_ALL);
		mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
						INT_CAUSE_UNMASK_ALL_EXT);
		spin_unlock_irqrestore(&mp->lock, flags);
	}

	return done ? 0 : 1;
}
#endif

/*
 * mv643xx_eth_start_xmit
 *
 * This function is queues a packet in the Tx descriptor for
 * required port.
 *
 * Input :	skb - a pointer to socket buffer
 *		dev - a pointer to the required port
 *
 * Output :	zero upon success
 */
static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	struct net_device_stats *stats = &mp->stats;
	ETH_FUNC_RET_STATUS status;
	unsigned long flags;
	struct pkt_info pkt_info;

	if (netif_queue_stopped(dev)) {
		printk(KERN_ERR
			"%s: Tried sending packet when interface is stopped\n",
			dev->name);
		return 1;
	}

	/* This is a hard error, log it. */
	if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
					(skb_shinfo(skb)->nr_frags + 1)) {
		netif_stop_queue(dev);
		printk(KERN_ERR
			"%s: Bug in mv643xx_eth - Trying to transmit when"
			" queue full !\n", dev->name);
		return 1;
	}

	/* Paranoid check - this shouldn't happen */
	if (skb == NULL) {
		stats->tx_dropped++;
		printk(KERN_ERR "mv64320_eth paranoid check failed\n");
		return 1;
	}

	spin_lock_irqsave(&mp->lock, flags);

	/* Update packet info data structure -- DMA owned, first last */
#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
	if (!skb_shinfo(skb)->nr_frags) {
linear:
		if (skb->ip_summed != CHECKSUM_HW) {
			/* Errata BTS #50, IHL must be 5 if no HW checksum */
			pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
					   ETH_TX_FIRST_DESC |
					   ETH_TX_LAST_DESC |
					   5 << ETH_TX_IHL_SHIFT;
			pkt_info.l4i_chk = 0;
		} else {

			pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
					   ETH_TX_FIRST_DESC |
					   ETH_TX_LAST_DESC |
					   ETH_GEN_TCP_UDP_CHECKSUM |
					   ETH_GEN_IP_V_4_CHECKSUM |
					   skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
			/* CPU already calculated pseudo header checksum. */
			if (skb->nh.iph->protocol == IPPROTO_UDP) {
				pkt_info.cmd_sts |= ETH_UDP_FRAME;
				pkt_info.l4i_chk = skb->h.uh->check;
			} else if (skb->nh.iph->protocol == IPPROTO_TCP)
				pkt_info.l4i_chk = skb->h.th->check;
			else {
				printk(KERN_ERR
					"%s: chksum proto != TCP or UDP\n",
					dev->name);
				spin_unlock_irqrestore(&mp->lock, flags);
				return 1;
			}
		}
		pkt_info.byte_cnt = skb->len;
		pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
							DMA_TO_DEVICE);
		pkt_info.return_info = skb;
		status = eth_port_send(mp, &pkt_info);
		if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
			printk(KERN_ERR "%s: Error on transmitting packet\n",
								dev->name);
		stats->tx_bytes += pkt_info.byte_cnt;
	} else {
		unsigned int frag;

		/* Since hardware can't handle unaligned fragments smaller
		 * than 9 bytes, if we find any, we linearize the skb
		 * and start again.  When I've seen it, it's always been
		 * the first frag (probably near the end of the page),
		 * but we check all frags to be safe.
		 */
		for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
			skb_frag_t *fragp;

			fragp = &skb_shinfo(skb)->frags[frag];
			if (fragp->size <= 8 && fragp->page_offset & 0x7) {
				skb_linearize(skb, GFP_ATOMIC);
				printk(KERN_DEBUG "%s: unaligned tiny fragment"
						"%d of %d, fixed\n",
						dev->name, frag,
						skb_shinfo(skb)->nr_frags);
				goto linear;
			}
		}

		/* first frag which is skb header */
		pkt_info.byte_cnt = skb_headlen(skb);
		pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
							skb_headlen(skb),
							DMA_TO_DEVICE);
		pkt_info.l4i_chk = 0;
		pkt_info.return_info = 0;

		if (skb->ip_summed != CHECKSUM_HW)
			/* Errata BTS #50, IHL must be 5 if no HW checksum */
			pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
					   5 << ETH_TX_IHL_SHIFT;
		else {
			pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
					   ETH_GEN_TCP_UDP_CHECKSUM |
					   ETH_GEN_IP_V_4_CHECKSUM |
					   skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
			/* CPU already calculated pseudo header checksum. */
			if (skb->nh.iph->protocol == IPPROTO_UDP) {
				pkt_info.cmd_sts |= ETH_UDP_FRAME;
				pkt_info.l4i_chk = skb->h.uh->check;
			} else if (skb->nh.iph->protocol == IPPROTO_TCP)
				pkt_info.l4i_chk = skb->h.th->check;
			else {
				printk(KERN_ERR
					"%s: chksum proto != TCP or UDP\n",
					dev->name);
				spin_unlock_irqrestore(&mp->lock, flags);
				return 1;
			}
		}

		status = eth_port_send(mp, &pkt_info);
		if (status != ETH_OK) {
			if ((status == ETH_ERROR))
				printk(KERN_ERR
					"%s: Error on transmitting packet\n",
					dev->name);
			if (status == ETH_QUEUE_FULL)
				printk("Error on Queue Full \n");
			if (status == ETH_QUEUE_LAST_RESOURCE)
				printk("Tx resource error \n");
		}
		stats->tx_bytes += pkt_info.byte_cnt;

		/* Check for the remaining frags */
		for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
			skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
			pkt_info.l4i_chk = 0x0000;
			pkt_info.cmd_sts = 0x00000000;

			/* Last Frag enables interrupt and frees the skb */
			if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
				pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
							ETH_TX_LAST_DESC;
				pkt_info.return_info = skb;
			} else {
				pkt_info.return_info = 0;
			}
			pkt_info.l4i_chk = 0;
			pkt_info.byte_cnt = this_frag->size;

			pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
							this_frag->page_offset,
							this_frag->size,
							DMA_TO_DEVICE);

			status = eth_port_send(mp, &pkt_info);

			if (status != ETH_OK) {
				if ((status == ETH_ERROR))
					printk(KERN_ERR "%s: Error on "
							"transmitting packet\n",
							dev->name);

				if (status == ETH_QUEUE_LAST_RESOURCE)
					printk("Tx resource error \n");

				if (status == ETH_QUEUE_FULL)
					printk("Queue is full \n");
			}
			stats->tx_bytes += pkt_info.byte_cnt;
		}
	}
#else
	pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
							ETH_TX_LAST_DESC;
	pkt_info.l4i_chk = 0;
	pkt_info.byte_cnt = skb->len;
	pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
								DMA_TO_DEVICE);
	pkt_info.return_info = skb;
	status = eth_port_send(mp, &pkt_info);
	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
		printk(KERN_ERR "%s: Error on transmitting packet\n",
								dev->name);
	stats->tx_bytes += pkt_info.byte_cnt;
#endif

	/* Check if TX queue can handle another skb. If not, then
	 * signal higher layers to stop requesting TX
	 */
	if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
		/*
		 * Stop getting skb's from upper layers.
		 * Getting skb's from upper layers will be enabled again after
		 * packets are released.
		 */
		netif_stop_queue(dev);

	/* Update statistics and start of transmittion time */
	stats->tx_packets++;
	dev->trans_start = jiffies;

	spin_unlock_irqrestore(&mp->lock, flags);

	return 0;		/* success */
}

/*
 * mv643xx_eth_get_stats
 *
 * Returns a pointer to the interface statistics.
 *
 * Input :	dev - a pointer to the required interface
 *
 * Output :	a pointer to the interface's statistics
 */

static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
{
	struct mv643xx_private *mp = netdev_priv(dev);

	return &mp->stats;
}

#ifdef CONFIG_NET_POLL_CONTROLLER
static inline void mv643xx_enable_irq(struct mv643xx_private *mp)
{
	int port_num = mp->port_num;
	unsigned long flags;

	spin_lock_irqsave(&mp->lock, flags);
	mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
					INT_CAUSE_UNMASK_ALL);
	mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
					INT_CAUSE_UNMASK_ALL_EXT);
	spin_unlock_irqrestore(&mp->lock, flags);
}

static inline void mv643xx_disable_irq(struct mv643xx_private *mp)
{
	int port_num = mp->port_num;
	unsigned long flags;

	spin_lock_irqsave(&mp->lock, flags);
	mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
					INT_CAUSE_MASK_ALL);
	mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
					INT_CAUSE_MASK_ALL_EXT);
	spin_unlock_irqrestore(&mp->lock, flags);
}

static void mv643xx_netpoll(struct net_device *netdev)
{
	struct mv643xx_private *mp = netdev_priv(netdev);

	mv643xx_disable_irq(mp);
	mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
	mv643xx_enable_irq(mp);
}
#endif

/*/
 * mv643xx_eth_probe
 *
 * First function called after registering the network device.
 * It's purpose is to initialize the device as an ethernet device,
 * fill the ethernet device structure with pointers * to functions,
 * and set the MAC address of the interface
 *
 * Input :	struct device *
 * Output :	-ENOMEM if failed , 0 if success
 */
static int mv643xx_eth_probe(struct device *ddev)
{
	struct platform_device *pdev = to_platform_device(ddev);
	struct mv643xx_eth_platform_data *pd;
	int port_num = pdev->id;
	struct mv643xx_private *mp;
	struct net_device *dev;
	u8 *p;
	struct resource *res;
	int err;

	dev = alloc_etherdev(sizeof(struct mv643xx_private));
	if (!dev)
		return -ENOMEM;

	dev_set_drvdata(ddev, dev);

	mp = netdev_priv(dev);

	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	BUG_ON(!res);
	dev->irq = res->start;

	mp->port_num = port_num;

	dev->open = mv643xx_eth_open;
	dev->stop = mv643xx_eth_stop;
	dev->hard_start_xmit = mv643xx_eth_start_xmit;
	dev->get_stats = mv643xx_eth_get_stats;
	dev->set_mac_address = mv643xx_eth_set_mac_address;
	dev->set_multicast_list = mv643xx_eth_set_rx_mode;

	/* No need to Tx Timeout */
	dev->tx_timeout = mv643xx_eth_tx_timeout;
#ifdef MV643XX_NAPI
	dev->poll = mv643xx_poll;
	dev->weight = 64;
#endif

#ifdef CONFIG_NET_POLL_CONTROLLER
	dev->poll_controller = mv643xx_netpoll;
#endif

	dev->watchdog_timeo = 2 * HZ;
	dev->tx_queue_len = mp->tx_ring_size;
	dev->base_addr = 0;
	dev->change_mtu = mv643xx_eth_change_mtu;
	SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);

#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
#ifdef MAX_SKB_FRAGS
	/*
	 * Zero copy can only work if we use Discovery II memory. Else, we will
	 * have to map the buffers to ISA memory which is only 16 MB
	 */
	dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
#endif
#endif

	/* Configure the timeout task */
	INIT_WORK(&mp->tx_timeout_task,
			(void (*)(void *))mv643xx_eth_tx_timeout_task, dev);

	spin_lock_init(&mp->lock);

	/* set default config values */
	eth_port_uc_addr_get(dev, dev->dev_addr);
	mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
	mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
	mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
	mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
	mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
	mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;

	pd = pdev->dev.platform_data;
	if (pd) {
		if (pd->mac_addr != NULL)
			memcpy(dev->dev_addr, pd->mac_addr, 6);

		if (pd->phy_addr || pd->force_phy_addr)
			ethernet_phy_set(port_num, pd->phy_addr);

		if (pd->port_config || pd->force_port_config)
			mp->port_config = pd->port_config;

		if (pd->port_config_extend || pd->force_port_config_extend)
			mp->port_config_extend = pd->port_config_extend;

		if (pd->port_sdma_config || pd->force_port_sdma_config)
			mp->port_sdma_config = pd->port_sdma_config;

		if (pd->port_serial_control || pd->force_port_serial_control)
			mp->port_serial_control = pd->port_serial_control;

		if (pd->rx_queue_size)
			mp->rx_ring_size = pd->rx_queue_size;

		if (pd->tx_queue_size)
			mp->tx_ring_size = pd->tx_queue_size;

		if (pd->tx_sram_size) {
			mp->tx_sram_size = pd->tx_sram_size;
			mp->tx_sram_addr = pd->tx_sram_addr;
		}

		if (pd->rx_sram_size) {
			mp->rx_sram_size = pd->rx_sram_size;
			mp->rx_sram_addr = pd->rx_sram_addr;
		}
	}

	err = ethernet_phy_detect(port_num);
	if (err) {
		pr_debug("MV643xx ethernet port %d: "
					"No PHY detected at addr %d\n",
					port_num, ethernet_phy_get(port_num));
		return err;
	}

	err = register_netdev(dev);
	if (err)
		goto out;

	p = dev->dev_addr;
	printk(KERN_NOTICE
		"%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
		dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);

	if (dev->features & NETIF_F_SG)
		printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);

	if (dev->features & NETIF_F_IP_CSUM)
		printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
								dev->name);

#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
	printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
#endif

#ifdef MV643XX_COAL
	printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
								dev->name);
#endif

#ifdef MV643XX_NAPI
	printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
#endif

	if (mp->tx_sram_size > 0)
		printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);

	return 0;

out:
	free_netdev(dev);

	return err;
}

static int mv643xx_eth_remove(struct device *ddev)
{
	struct net_device *dev = dev_get_drvdata(ddev);

	unregister_netdev(dev);
	flush_scheduled_work();

	free_netdev(dev);
	dev_set_drvdata(ddev, NULL);
	return 0;
}

static int mv643xx_eth_shared_probe(struct device *ddev)
{
	struct platform_device *pdev = to_platform_device(ddev);
	struct resource *res;

	printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL)
		return -ENODEV;

	mv643xx_eth_shared_base = ioremap(res->start,
						MV643XX_ETH_SHARED_REGS_SIZE);
	if (mv643xx_eth_shared_base == NULL)
		return -ENOMEM;

	return 0;

}

static int mv643xx_eth_shared_remove(struct device *ddev)
{
	iounmap(mv643xx_eth_shared_base);
	mv643xx_eth_shared_base = NULL;

	return 0;
}

static struct device_driver mv643xx_eth_driver = {
	.name = MV643XX_ETH_NAME,
	.bus = &platform_bus_type,
	.probe = mv643xx_eth_probe,
	.remove = mv643xx_eth_remove,
};

static struct device_driver mv643xx_eth_shared_driver = {
	.name = MV643XX_ETH_SHARED_NAME,
	.bus = &platform_bus_type,
	.probe = mv643xx_eth_shared_probe,
	.remove = mv643xx_eth_shared_remove,
};

/*
 * mv643xx_init_module
 *
 * Registers the network drivers into the Linux kernel
 *
 * Input :	N/A
 *
 * Output :	N/A
 */
static int __init mv643xx_init_module(void)
{
	int rc;

	rc = driver_register(&mv643xx_eth_shared_driver);
	if (!rc) {
		rc = driver_register(&mv643xx_eth_driver);
		if (rc)
			driver_unregister(&mv643xx_eth_shared_driver);
	}
	return rc;
}

/*
 * mv643xx_cleanup_module
 *
 * Registers the network drivers into the Linux kernel
 *
 * Input :	N/A
 *
 * Output :	N/A
 */
static void __exit mv643xx_cleanup_module(void)
{
	driver_unregister(&mv643xx_eth_driver);
	driver_unregister(&mv643xx_eth_shared_driver);
}

module_init(mv643xx_init_module);
module_exit(mv643xx_cleanup_module);

MODULE_LICENSE("GPL");
MODULE_AUTHOR(	"Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
		" and Dale Farnsworth");
MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");

/*
 * The second part is the low level driver of the gigE ethernet ports.
 */

/*
 * Marvell's Gigabit Ethernet controller low level driver
 *
 * DESCRIPTION:
 *	This file introduce low level API to Marvell's Gigabit Ethernet
 *		controller. This Gigabit Ethernet Controller driver API controls
 *		1) Operations (i.e. port init, start, reset etc').
 *		2) Data flow (i.e. port send, receive etc').
 *		Each Gigabit Ethernet port is controlled via
 *		struct mv643xx_private.
 *		This struct includes user configuration information as well as
 *		driver internal data needed for its operations.
 *
 *		Supported Features:
 *		- This low level driver is OS independent. Allocating memory for
 *		  the descriptor rings and buffers are not within the scope of
 *		  this driver.
 *		- The user is free from Rx/Tx queue managing.
 *		- This low level driver introduce functionality API that enable
 *		  the to operate Marvell's Gigabit Ethernet Controller in a
 *		  convenient way.
 *		- Simple Gigabit Ethernet port operation API.
 *		- Simple Gigabit Ethernet port data flow API.
 *		- Data flow and operation API support per queue functionality.
 *		- Support cached descriptors for better performance.
 *		- Enable access to all four DRAM banks and internal SRAM memory
 *		  spaces.
 *		- PHY access and control API.
 *		- Port control register configuration API.
 *		- Full control over Unicast and Multicast MAC configurations.
 *
 *		Operation flow:
 *
 *		Initialization phase
 *		This phase complete the initialization of the the
 *		mv643xx_private struct.
 *		User information regarding port configuration has to be set
 *		prior to calling the port initialization routine.
 *
 *		In this phase any port Tx/Rx activity is halted, MIB counters
 *		are cleared, PHY address is set according to user parameter and
 *		access to DRAM and internal SRAM memory spaces.
 *
 *		Driver ring initialization
 *		Allocating memory for the descriptor rings and buffers is not
 *		within the scope of this driver. Thus, the user is required to
 *		allocate memory for the descriptors ring and buffers. Those
 *		memory parameters are used by the Rx and Tx ring initialization
 *		routines in order to curve the descriptor linked list in a form
 *		of a ring.
 *		Note: Pay special attention to alignment issues when using
 *		cached descriptors/buffers. In this phase the driver store
 *		information in the mv643xx_private struct regarding each queue
 *		ring.
 *
 *		Driver start
 *		This phase prepares the Ethernet port for Rx and Tx activity.
 *		It uses the information stored in the mv643xx_private struct to
 *		initialize the various port registers.
 *
 *		Data flow:
 *		All packet references to/from the driver are done using
 *		struct pkt_info.
 *		This struct is a unified struct used with Rx and Tx operations.
 *		This way the user is not required to be familiar with neither
 *		Tx nor Rx descriptors structures.
 *		The driver's descriptors rings are management by indexes.
 *		Those indexes controls the ring resources and used to indicate
 *		a SW resource error:
 *		'current'
 *		This index points to the current available resource for use. For
 *		example in Rx process this index will point to the descriptor
 *		that will be passed to the user upon calling the receive
 *		routine.  In Tx process, this index will point to the descriptor
 *		that will be assigned with the user packet info and transmitted.
 *		'used'
 *		This index points to the descriptor that need to restore its
 *		resources. For example in Rx process, using the Rx buffer return
 *		API will attach the buffer returned in packet info to the
 *		descriptor pointed by 'used'. In Tx process, using the Tx
 *		descriptor return will merely return the user packet info with
 *		the command status of the transmitted buffer pointed by the
 *		'used' index. Nevertheless, it is essential to use this routine
 *		to update the 'used' index.
 *		'first'
 *		This index supports Tx Scatter-Gather. It points to the first
 *		descriptor of a packet assembled of multiple buffers. For
 *		example when in middle of Such packet we have a Tx resource
 *		error the 'curr' index get the value of 'first' to indicate
 *		that the ring returned to its state before trying to transmit
 *		this packet.
 *
 *		Receive operation:
 *		The eth_port_receive API set the packet information struct,
 *		passed by the caller, with received information from the
 *		'current' SDMA descriptor.
 *		It is the user responsibility to return this resource back
 *		to the Rx descriptor ring to enable the reuse of this source.
 *		Return Rx resource is done using the eth_rx_return_buff API.
 *
 *		Transmit operation:
 *		The eth_port_send API supports Scatter-Gather which enables to
 *		send a packet spanned over multiple buffers. This means that
 *		for each packet info structure given by the user and put into
 *		the Tx descriptors ring, will be transmitted only if the 'LAST'
 *		bit will be set in the packet info command status field. This
 *		API also consider restriction regarding buffer alignments and
 *		sizes.
 *		The user must return a Tx resource after ensuring the buffer
 *		has been transmitted to enable the Tx ring indexes to update.
 *
 *		BOARD LAYOUT
 *		This device is on-board.  No jumper diagram is necessary.
 *
 *		EXTERNAL INTERFACE
 *
 *	Prior to calling the initialization routine eth_port_init() the user
 *	must set the following fields under mv643xx_private struct:
 *	port_num		User Ethernet port number.
 *	port_mac_addr[6]	User defined port MAC address.
 *	port_config		User port configuration value.
 *	port_config_extend	User port config extend value.
 *	port_sdma_config	User port SDMA config value.
 *	port_serial_control	User port serial control value.
 *
 *		This driver data flow is done using the struct pkt_info which
 *		is a unified struct for Rx and Tx operations:
 *
 *		byte_cnt	Tx/Rx descriptor buffer byte count.
 *		l4i_chk		CPU provided TCP Checksum. For Tx operation
 *				only.
 *		cmd_sts		Tx/Rx descriptor command status.
 *		buf_ptr		Tx/Rx descriptor buffer pointer.
 *		return_info	Tx/Rx user resource return information.
 */

/* defines */
/* SDMA command macros */
#define ETH_ENABLE_TX_QUEUE(eth_port) \
	mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)

/* locals */

/* PHY routines */
static int ethernet_phy_get(unsigned int eth_port_num);
static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);

/* Ethernet Port routines */
static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
								int option);

/*
 * eth_port_init - Initialize the Ethernet port driver
 *
 * DESCRIPTION:
 *	This function prepares the ethernet port to start its activity:
 *	1) Completes the ethernet port driver struct initialization toward port
 *		start routine.
 *	2) Resets the device to a quiescent state in case of warm reboot.
 *	3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
 *	4) Clean MAC tables. The reset status of those tables is unknown.
 *	5) Set PHY address.
 *	Note: Call this routine prior to eth_port_start routine and after
 *	setting user values in the user fields of Ethernet port control
 *	struct.
 *
 * INPUT:
 *	struct mv643xx_private *mp	Ethernet port control struct
 *
 * OUTPUT:
 *	See description.
 *
 * RETURN:
 *	None.
 */
static void eth_port_init(struct mv643xx_private *mp)
{
	mp->port_rx_queue_command = 0;
	mp->port_tx_queue_command = 0;

	mp->rx_resource_err = 0;
	mp->tx_resource_err = 0;

	eth_port_reset(mp->port_num);

	eth_port_init_mac_tables(mp->port_num);

	ethernet_phy_reset(mp->port_num);
}

/*
 * eth_port_start - Start the Ethernet port activity.
 *
 * DESCRIPTION:
 *	This routine prepares the Ethernet port for Rx and Tx activity:
 *	 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
 *	    has been initialized a descriptor's ring (using
 *	    ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
 *	 2. Initialize and enable the Ethernet configuration port by writing to
 *	    the port's configuration and command registers.
 *	 3. Initialize and enable the SDMA by writing to the SDMA's
 *	    configuration and command registers.  After completing these steps,
 *	    the ethernet port SDMA can starts to perform Rx and Tx activities.
 *
 *	Note: Each Rx and Tx queue descriptor's list must be initialized prior
 *	to calling this function (use ether_init_tx_desc_ring for Tx queues
 *	and ether_init_rx_desc_ring for Rx queues).
 *
 * INPUT:
 *	struct mv643xx_private *mp	Ethernet port control struct
 *
 * OUTPUT:
 *	Ethernet port is ready to receive and transmit.
 *
 * RETURN:
 *	None.
 */
static void eth_port_start(struct mv643xx_private *mp)
{
	unsigned int port_num = mp->port_num;
	int tx_curr_desc, rx_curr_desc;

	/* Assignment of Tx CTRP of given queue */
	tx_curr_desc = mp->tx_curr_desc_q;
	mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
		(u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));

	/* Assignment of Rx CRDP of given queue */
	rx_curr_desc = mp->rx_curr_desc_q;
	mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
		(u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));

	/* Add the assigned Ethernet address to the port's address table */
	eth_port_uc_addr_set(port_num, mp->port_mac_addr);

	/* Assign port configuration and command. */
	mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);

	mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
						mp->port_config_extend);


	/* Increase the Rx side buffer size if supporting GigE */
	if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
		mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
			(mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
	else
		mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
						mp->port_serial_control);

	mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
		mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
						MV643XX_ETH_SERIAL_PORT_ENABLE);

	/* Assign port SDMA configuration */
	mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
							mp->port_sdma_config);

	/* Enable port Rx. */
	mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
						mp->port_rx_queue_command);

	/* Disable port bandwidth limits by clearing MTU register */
	mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
}

/*
 * eth_port_uc_addr_set - This function Set the port Unicast address.
 *
 * DESCRIPTION:
 *		This function Set the port Ethernet MAC address.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Port number.
 *	char *		p_addr		Address to be set
 *
 * OUTPUT:
 *	Set MAC address low and high registers. also calls eth_port_uc_addr()
 *	To set the unicast table with the proper information.
 *
 * RETURN:
 *	N/A.
 *
 */
static void eth_port_uc_addr_set(unsigned int eth_port_num,
							unsigned char *p_addr)
{
	unsigned int mac_h;
	unsigned int mac_l;

	mac_l = (p_addr[4] << 8) | (p_addr[5]);
	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
							(p_addr[3] << 0);

	mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
	mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);

	/* Accept frames of this address */
	eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);

	return;
}

/*
 * eth_port_uc_addr_get - This function retrieves the port Unicast address
 * (MAC address) from the ethernet hw registers.
 *
 * DESCRIPTION:
 *		This function retrieves the port Ethernet MAC address.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Port number.
 *	char		*MacAddr	pointer where the MAC address is stored
 *
 * OUTPUT:
 *	Copy the MAC address to the location pointed to by MacAddr
 *
 * RETURN:
 *	N/A.
 *
 */
static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
{
	struct mv643xx_private *mp = netdev_priv(dev);
	unsigned int mac_h;
	unsigned int mac_l;

	mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
	mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));

	p_addr[0] = (mac_h >> 24) & 0xff;
	p_addr[1] = (mac_h >> 16) & 0xff;
	p_addr[2] = (mac_h >> 8) & 0xff;
	p_addr[3] = mac_h & 0xff;
	p_addr[4] = (mac_l >> 8) & 0xff;
	p_addr[5] = mac_l & 0xff;
}

/*
 * eth_port_uc_addr - This function Set the port unicast address table
 *
 * DESCRIPTION:
 *	This function locates the proper entry in the Unicast table for the
 *	specified MAC nibble and sets its properties according to function
 *	parameters.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Port number.
 *	unsigned char	uc_nibble	Unicast MAC Address last nibble.
 *	int 		option		0 = Add, 1 = remove address.
 *
 * OUTPUT:
 *	This function add/removes MAC addresses from the port unicast address
 *	table.
 *
 * RETURN:
 *	true is output succeeded.
 *	false if option parameter is invalid.
 *
 */
static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
								int option)
{
	unsigned int unicast_reg;
	unsigned int tbl_offset;
	unsigned int reg_offset;

	/* Locate the Unicast table entry */
	uc_nibble = (0xf & uc_nibble);
	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */

	switch (option) {
	case REJECT_MAC_ADDR:
		/* Clear accepts frame bit at given unicast DA table entry */
		unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
						(eth_port_num) + tbl_offset));

		unicast_reg &= (0x0E << (8 * reg_offset));

		mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
				(eth_port_num) + tbl_offset), unicast_reg);
		break;

	case ACCEPT_MAC_ADDR:
		/* Set accepts frame bit at unicast DA filter table entry */
		unicast_reg =
			mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
						(eth_port_num) + tbl_offset));

		unicast_reg |= (0x01 << (8 * reg_offset));

		mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
				(eth_port_num) + tbl_offset), unicast_reg);

		break;

	default:
		return 0;
	}

	return 1;
}

/*
 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
 *
 * DESCRIPTION:
 *	Go through all the DA filter tables (Unicast, Special Multicast &
 *	Other Multicast) and set each entry to 0.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Ethernet Port number.
 *
 * OUTPUT:
 *	Multicast and Unicast packets are rejected.
 *
 * RETURN:
 *	None.
 */
static void eth_port_init_mac_tables(unsigned int eth_port_num)
{
	int table_index;

	/* Clear DA filter unicast table (Ex_dFUT) */
	for (table_index = 0; table_index <= 0xC; table_index += 4)
		mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
					(eth_port_num) + table_index), 0);

	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
		/* Clear DA filter special multicast table (Ex_dFSMT) */
		mv_write((MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
					(eth_port_num) + table_index), 0);
		/* Clear DA filter other multicast table (Ex_dFOMT) */
		mv_write((MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
					(eth_port_num) + table_index), 0);
	}
}

/*
 * eth_clear_mib_counters - Clear all MIB counters
 *
 * DESCRIPTION:
 *	This function clears all MIB counters of a specific ethernet port.
 *	A read from the MIB counter will reset the counter.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Ethernet Port number.
 *
 * OUTPUT:
 *	After reading all MIB counters, the counters resets.
 *
 * RETURN:
 *	MIB counter value.
 *
 */
static void eth_clear_mib_counters(unsigned int eth_port_num)
{
	int i;

	/* Perform dummy reads from MIB counters */
	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
									i += 4)
		mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
}

static inline u32 read_mib(struct mv643xx_private *mp, int offset)
{
	return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
}

static void eth_update_mib_counters(struct mv643xx_private *mp)
{
	struct mv643xx_mib_counters *p = &mp->mib_counters;
	int offset;

	p->good_octets_received +=
		read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
	p->good_octets_received +=
		(u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;

	for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
			offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
			offset += 4)
		*(u32 *)((char *)p + offset) = read_mib(mp, offset);

	p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
	p->good_octets_sent +=
		(u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;

	for (offset = ETH_MIB_GOOD_FRAMES_SENT;
			offset <= ETH_MIB_LATE_COLLISION;
			offset += 4)
		*(u32 *)((char *)p + offset) = read_mib(mp, offset);
}

/*
 * ethernet_phy_detect - Detect whether a phy is present
 *
 * DESCRIPTION:
 *	This function tests whether there is a PHY present on
 *	the specified port.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Ethernet Port number.
 *
 * OUTPUT:
 *	None
 *
 * RETURN:
 *	0 on success
 *	-ENODEV on failure
 *
 */
static int ethernet_phy_detect(unsigned int port_num)
{
	unsigned int phy_reg_data0;
	int auto_neg;

	eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
	auto_neg = phy_reg_data0 & 0x1000;
	phy_reg_data0 ^= 0x1000;	/* invert auto_neg */
	eth_port_write_smi_reg(port_num, 0, phy_reg_data0);

	eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
	if ((phy_reg_data0 & 0x1000) == auto_neg)
		return -ENODEV;				/* change didn't take */

	phy_reg_data0 ^= 0x1000;
	eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
	return 0;
}

/*
 * ethernet_phy_get - Get the ethernet port PHY address.
 *
 * DESCRIPTION:
 *	This routine returns the given ethernet port PHY address.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Ethernet Port number.
 *
 * OUTPUT:
 *	None.
 *
 * RETURN:
 *	PHY address.
 *
 */
static int ethernet_phy_get(unsigned int eth_port_num)
{
	unsigned int reg_data;

	reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);

	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
}

/*
 * ethernet_phy_set - Set the ethernet port PHY address.
 *
 * DESCRIPTION:
 *	This routine sets the given ethernet port PHY address.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Ethernet Port number.
 *	int		phy_addr	PHY address.
 *
 * OUTPUT:
 *	None.
 *
 * RETURN:
 *	None.
 *
 */
static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
{
	u32 reg_data;
	int addr_shift = 5 * eth_port_num;

	reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
	reg_data &= ~(0x1f << addr_shift);
	reg_data |= (phy_addr & 0x1f) << addr_shift;
	mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
}

/*
 * ethernet_phy_reset - Reset Ethernet port PHY.
 *
 * DESCRIPTION:
 *	This routine utilizes the SMI interface to reset the ethernet port PHY.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Ethernet Port number.
 *
 * OUTPUT:
 *	The PHY is reset.
 *
 * RETURN:
 *	None.
 *
 */
static void ethernet_phy_reset(unsigned int eth_port_num)
{
	unsigned int phy_reg_data;

	/* Reset the PHY */
	eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
	eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
}

/*
 * eth_port_reset - Reset Ethernet port
 *
 * DESCRIPTION:
 * 	This routine resets the chip by aborting any SDMA engine activity and
 *	clearing the MIB counters. The Receiver and the Transmit unit are in
 *	idle state after this command is performed and the port is disabled.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Ethernet Port number.
 *
 * OUTPUT:
 *	Channel activity is halted.
 *
 * RETURN:
 *	None.
 *
 */
static void eth_port_reset(unsigned int port_num)
{
	unsigned int reg_data;

	/* Stop Tx port activity. Check port Tx activity. */
	reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));

	if (reg_data & 0xFF) {
		/* Issue stop command for active channels only */
		mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
							(reg_data << 8));

		/* Wait for all Tx activity to terminate. */
		/* Check port cause register that all Tx queues are stopped */
		while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
									& 0xFF)
			udelay(10);
	}

	/* Stop Rx port activity. Check port Rx activity. */
	reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));

	if (reg_data & 0xFF) {
		/* Issue stop command for active channels only */
		mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
							(reg_data << 8));

		/* Wait for all Rx activity to terminate. */
		/* Check port cause register that all Rx queues are stopped */
		while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
									& 0xFF)
			udelay(10);
	}

	/* Clear all MIB counters */
	eth_clear_mib_counters(port_num);

	/* Reset the Enable bit in the Configuration Register */
	reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
	reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
	mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
}


static int eth_port_autoneg_supported(unsigned int eth_port_num)
{
	unsigned int phy_reg_data0;

	eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);

	return phy_reg_data0 & 0x1000;
}

static int eth_port_link_is_up(unsigned int eth_port_num)
{
	unsigned int phy_reg_data1;

	eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);

	if (eth_port_autoneg_supported(eth_port_num)) {
		if (phy_reg_data1 & 0x20)	/* auto-neg complete */
			return 1;
	} else if (phy_reg_data1 & 0x4)		/* link up */
		return 1;

	return 0;
}

/*
 * eth_port_read_smi_reg - Read PHY registers
 *
 * DESCRIPTION:
 *	This routine utilize the SMI interface to interact with the PHY in
 *	order to perform PHY register read.
 *
 * INPUT:
 *	unsigned int	port_num	Ethernet Port number.
 *	unsigned int	phy_reg		PHY register address offset.
 *	unsigned int	*value		Register value buffer.
 *
 * OUTPUT:
 *	Write the value of a specified PHY register into given buffer.
 *
 * RETURN:
 *	false if the PHY is busy or read data is not in valid state.
 *	true otherwise.
 *
 */
static void eth_port_read_smi_reg(unsigned int port_num,
				unsigned int phy_reg, unsigned int *value)
{
	int phy_addr = ethernet_phy_get(port_num);
	unsigned long flags;
	int i;

	/* the SMI register is a shared resource */
	spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);

	/* wait for the SMI register to become available */
	for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
		if (i == PHY_WAIT_ITERATIONS) {
			printk("mv643xx PHY busy timeout, port %d\n", port_num);
			goto out;
		}
		udelay(PHY_WAIT_MICRO_SECONDS);
	}

	mv_write(MV643XX_ETH_SMI_REG,
		(phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);

	/* now wait for the data to be valid */
	for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
		if (i == PHY_WAIT_ITERATIONS) {
			printk("mv643xx PHY read timeout, port %d\n", port_num);
			goto out;
		}
		udelay(PHY_WAIT_MICRO_SECONDS);
	}

	*value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
out:
	spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
}

/*
 * eth_port_write_smi_reg - Write to PHY registers
 *
 * DESCRIPTION:
 *	This routine utilize the SMI interface to interact with the PHY in
 *	order to perform writes to PHY registers.
 *
 * INPUT:
 *	unsigned int	eth_port_num	Ethernet Port number.
 *	unsigned int	phy_reg		PHY register address offset.
 *	unsigned int	value		Register value.
 *
 * OUTPUT:
 *	Write the given value to the specified PHY register.
 *
 * RETURN:
 *	false if the PHY is busy.
 *	true otherwise.
 *
 */
static void eth_port_write_smi_reg(unsigned int eth_port_num,
				   unsigned int phy_reg, unsigned int value)
{
	int phy_addr;
	int i;
	unsigned long flags;

	phy_addr = ethernet_phy_get(eth_port_num);

	/* the SMI register is a shared resource */
	spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);

	/* wait for the SMI register to become available */
	for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
		if (i == PHY_WAIT_ITERATIONS) {
			printk("mv643xx PHY busy timeout, port %d\n",
								eth_port_num);
			goto out;
		}
		udelay(PHY_WAIT_MICRO_SECONDS);
	}

	mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
				ETH_SMI_OPCODE_WRITE | (value & 0xffff));
out:
	spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
}

/*
 * eth_port_send - Send an Ethernet packet
 *
 * DESCRIPTION:
 *	This routine send a given packet described by p_pktinfo parameter. It
 *	supports transmitting of a packet spaned over multiple buffers. The
 *	routine updates 'curr' and 'first' indexes according to the packet
 *	segment passed to the routine. In case the packet segment is first,
 *	the 'first' index is update. In any case, the 'curr' index is updated.
 *	If the routine get into Tx resource error it assigns 'curr' index as
 *	'first'. This way the function can abort Tx process of multiple
 *	descriptors per packet.
 *
 * INPUT:
 *	struct mv643xx_private	*mp		Ethernet Port Control srtuct.
 *	struct pkt_info		*p_pkt_info	User packet buffer.
 *
 * OUTPUT:
 *	Tx ring 'curr' and 'first' indexes are updated.
 *
 * RETURN:
 *	ETH_QUEUE_FULL in case of Tx resource error.
 *	ETH_ERROR in case the routine can not access Tx desc ring.
 *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
 *	ETH_OK otherwise.
 *
 */
#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
/*
 * Modified to include the first descriptor pointer in case of SG
 */
static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
					 struct pkt_info *p_pkt_info)
{
	int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
	struct eth_tx_desc *current_descriptor;
	struct eth_tx_desc *first_descriptor;
	u32 command;

	/* Do not process Tx ring in case of Tx ring resource error */
	if (mp->tx_resource_err)
		return ETH_QUEUE_FULL;

	/*
	 * The hardware requires that each buffer that is <= 8 bytes
	 * in length must be aligned on an 8 byte boundary.
	 */
	if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
		printk(KERN_ERR
			"mv643xx_eth port %d: packet size <= 8 problem\n",
			mp->port_num);
		return ETH_ERROR;
	}

	mp->tx_ring_skbs++;
	BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);

	/* Get the Tx Desc ring indexes */
	tx_desc_curr = mp->tx_curr_desc_q;
	tx_desc_used = mp->tx_used_desc_q;

	current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];

	tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;

	current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
	current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
	current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
	mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;

	command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
							ETH_BUFFER_OWNED_BY_DMA;
	if (command & ETH_TX_FIRST_DESC) {
		tx_first_desc = tx_desc_curr;
		mp->tx_first_desc_q = tx_first_desc;
		first_descriptor = current_descriptor;
		mp->tx_first_command = command;
	} else {
		tx_first_desc = mp->tx_first_desc_q;
		first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
		BUG_ON(first_descriptor == NULL);
		current_descriptor->cmd_sts = command;
	}

	if (command & ETH_TX_LAST_DESC) {
		wmb();
		first_descriptor->cmd_sts = mp->tx_first_command;

		wmb();
		ETH_ENABLE_TX_QUEUE(mp->port_num);

		/*
		 * Finish Tx packet. Update first desc in case of Tx resource
		 * error */
		tx_first_desc = tx_next_desc;
		mp->tx_first_desc_q = tx_first_desc;
	}

	/* Check for ring index overlap in the Tx desc ring */
	if (tx_next_desc == tx_desc_used) {
		mp->tx_resource_err = 1;
		mp->tx_curr_desc_q = tx_first_desc;

		return ETH_QUEUE_LAST_RESOURCE;
	}

	mp->tx_curr_desc_q = tx_next_desc;

	return ETH_OK;
}
#else
static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
					 struct pkt_info *p_pkt_info)
{
	int tx_desc_curr;
	int tx_desc_used;
	struct eth_tx_desc *current_descriptor;
	unsigned int command_status;

	/* Do not process Tx ring in case of Tx ring resource error */
	if (mp->tx_resource_err)
		return ETH_QUEUE_FULL;

	mp->tx_ring_skbs++;
	BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);

	/* Get the Tx Desc ring indexes */
	tx_desc_curr = mp->tx_curr_desc_q;
	tx_desc_used = mp->tx_used_desc_q;
	current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];

	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
	current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
	current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
	mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;

	/* Set last desc with DMA ownership and interrupt enable. */
	wmb();
	current_descriptor->cmd_sts = command_status |
			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;

	wmb();
	ETH_ENABLE_TX_QUEUE(mp->port_num);

	/* Finish Tx packet. Update first desc in case of Tx resource error */
	tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;

	/* Update the current descriptor */
	mp->tx_curr_desc_q = tx_desc_curr;

	/* Check for ring index overlap in the Tx desc ring */
	if (tx_desc_curr == tx_desc_used) {
		mp->tx_resource_err = 1;
		return ETH_QUEUE_LAST_RESOURCE;
	}

	return ETH_OK;
}
#endif

/*
 * eth_tx_return_desc - Free all used Tx descriptors
 *
 * DESCRIPTION:
 *	This routine returns the transmitted packet information to the caller.
 *	It uses the 'first' index to support Tx desc return in case a transmit
 *	of a packet spanned over multiple buffer still in process.
 *	In case the Tx queue was in "resource error" condition, where there are
 *	no available Tx resources, the function resets the resource error flag.
 *
 * INPUT:
 *	struct mv643xx_private	*mp		Ethernet Port Control srtuct.
 *	struct pkt_info		*p_pkt_info	User packet buffer.
 *
 * OUTPUT:
 *	Tx ring 'first' and 'used' indexes are updated.
 *
 * RETURN:
 *	ETH_ERROR in case the routine can not access Tx desc ring.
 *	ETH_RETRY in case there is transmission in process.
 *	ETH_END_OF_JOB if the routine has nothing to release.
 *	ETH_OK otherwise.
 *
 */
static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
						struct pkt_info *p_pkt_info)
{
	int tx_desc_used;
#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
	int tx_busy_desc = mp->tx_first_desc_q;
#else
	int tx_busy_desc = mp->tx_curr_desc_q;
#endif
	struct eth_tx_desc *p_tx_desc_used;
	unsigned int command_status;

	/* Get the Tx Desc ring indexes */
	tx_desc_used = mp->tx_used_desc_q;

	p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];

	/* Sanity check */
	if (p_tx_desc_used == NULL)
		return ETH_ERROR;

	/* Stop release. About to overlap the current available Tx descriptor */
	if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err)
		return ETH_END_OF_JOB;

	command_status = p_tx_desc_used->cmd_sts;

	/* Still transmitting... */
	if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
		return ETH_RETRY;

	/* Pass the packet information to the caller */
	p_pkt_info->cmd_sts = command_status;
	p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
	mp->tx_skb[tx_desc_used] = NULL;

	/* Update the next descriptor to release. */
	mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;

	/* Any Tx return cancels the Tx resource error status */
	mp->tx_resource_err = 0;

	BUG_ON(mp->tx_ring_skbs == 0);
	mp->tx_ring_skbs--;

	return ETH_OK;
}

/*
 * eth_port_receive - Get received information from Rx ring.
 *
 * DESCRIPTION:
 * 	This routine returns the received data to the caller. There is no
 *	data copying during routine operation. All information is returned
 *	using pointer to packet information struct passed from the caller.
 *	If the routine exhausts Rx ring resources then the resource error flag
 *	is set.
 *
 * INPUT:
 *	struct mv643xx_private	*mp		Ethernet Port Control srtuct.
 *	struct pkt_info		*p_pkt_info	User packet buffer.
 *
 * OUTPUT:
 *	Rx ring current and used indexes are updated.
 *
 * RETURN:
 *	ETH_ERROR in case the routine can not access Rx desc ring.
 *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
 *	ETH_END_OF_JOB if there is no received data.
 *	ETH_OK otherwise.
 */
static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
						struct pkt_info *p_pkt_info)
{
	int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
	volatile struct eth_rx_desc *p_rx_desc;
	unsigned int command_status;

	/* Do not process Rx ring in case of Rx ring resource error */
	if (mp->rx_resource_err)
		return ETH_QUEUE_FULL;

	/* Get the Rx Desc ring 'curr and 'used' indexes */
	rx_curr_desc = mp->rx_curr_desc_q;
	rx_used_desc = mp->rx_used_desc_q;

	p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];

	/* The following parameters are used to save readings from memory */
	command_status = p_rx_desc->cmd_sts;
	rmb();

	/* Nothing to receive... */
	if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
		return ETH_END_OF_JOB;

	p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
	p_pkt_info->cmd_sts = command_status;
	p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
	p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
	p_pkt_info->l4i_chk = p_rx_desc->buf_size;

	/* Clean the return info field to indicate that the packet has been */
	/* moved to the upper layers					    */
	mp->rx_skb[rx_curr_desc] = NULL;

	/* Update current index in data structure */
	rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
	mp->rx_curr_desc_q = rx_next_curr_desc;

	/* Rx descriptors exhausted. Set the Rx ring resource error flag */
	if (rx_next_curr_desc == rx_used_desc)
		mp->rx_resource_err = 1;

	return ETH_OK;
}

/*
 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
 *
 * DESCRIPTION:
 *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
 *	next 'used' descriptor and attached the returned buffer to it.
 *	In case the Rx ring was in "resource error" condition, where there are
 *	no available Rx resources, the function resets the resource error flag.
 *
 * INPUT:
 *	struct mv643xx_private	*mp		Ethernet Port Control srtuct.
 *	struct pkt_info		*p_pkt_info	Information on returned buffer.
 *
 * OUTPUT:
 *	New available Rx resource in Rx descriptor ring.
 *
 * RETURN:
 *	ETH_ERROR in case the routine can not access Rx desc ring.
 *	ETH_OK otherwise.
 */
static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
						struct pkt_info *p_pkt_info)
{
	int used_rx_desc;	/* Where to return Rx resource */
	volatile struct eth_rx_desc *p_used_rx_desc;

	/* Get 'used' Rx descriptor */
	used_rx_desc = mp->rx_used_desc_q;
	p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];

	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
	p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
	mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;

	/* Flush the write pipe */

	/* Return the descriptor to DMA ownership */
	wmb();
	p_used_rx_desc->cmd_sts =
			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
	wmb();

	/* Move the used descriptor pointer to the next descriptor */
	mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;

	/* Any Rx return cancels the Rx resource error status */
	mp->rx_resource_err = 0;

	return ETH_OK;
}

/************* Begin ethtool support *************************/

struct mv643xx_stats {
	char stat_string[ETH_GSTRING_LEN];
	int sizeof_stat;
	int stat_offset;
};

#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
		      offsetof(struct mv643xx_private, m)

static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
	{ "rx_packets", MV643XX_STAT(stats.rx_packets) },
	{ "tx_packets", MV643XX_STAT(stats.tx_packets) },
	{ "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
	{ "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
	{ "rx_errors", MV643XX_STAT(stats.rx_errors) },
	{ "tx_errors", MV643XX_STAT(stats.tx_errors) },
	{ "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
	{ "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
	{ "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
	{ "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
	{ "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
	{ "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
	{ "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
	{ "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
	{ "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
	{ "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
	{ "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
	{ "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
	{ "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
	{ "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
	{ "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
	{ "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
	{ "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
	{ "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
	{ "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
	{ "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
	{ "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
	{ "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
	{ "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
	{ "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
	{ "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
	{ "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
	{ "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
	{ "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
	{ "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
	{ "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
	{ "collision", MV643XX_STAT(mib_counters.collision) },
	{ "late_collision", MV643XX_STAT(mib_counters.late_collision) },
};

#define MV643XX_STATS_LEN	\
	sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)

static int
mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
{
	struct mv643xx_private *mp = netdev->priv;
	int port_num = mp->port_num;
	int autoneg = eth_port_autoneg_supported(port_num);
	int mode_10_bit;
	int auto_duplex;
	int half_duplex = 0;
	int full_duplex = 0;
	int auto_speed;
	int speed_10 = 0;
	int speed_100 = 0;
	int speed_1000 = 0;

	u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
	u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));

	mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;

	if (mode_10_bit) {
		ecmd->supported = SUPPORTED_10baseT_Half;
	} else {
		ecmd->supported = (SUPPORTED_10baseT_Half		|
				   SUPPORTED_10baseT_Full		|
				   SUPPORTED_100baseT_Half		|
				   SUPPORTED_100baseT_Full		|
				   SUPPORTED_1000baseT_Full		|
				   (autoneg ? SUPPORTED_Autoneg : 0)	|
				   SUPPORTED_TP);

		auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
		auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);

		ecmd->advertising = ADVERTISED_TP;

		if (autoneg) {
			ecmd->advertising |= ADVERTISED_Autoneg;

			if (auto_duplex) {
				half_duplex = 1;
				full_duplex = 1;
			} else {
				if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
					full_duplex = 1;
				else
					half_duplex = 1;
			}

			if (auto_speed) {
				speed_10 = 1;
				speed_100 = 1;
				speed_1000 = 1;
			} else {
				if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
					speed_1000 = 1;
				else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
					speed_100 = 1;
				else
					speed_10 = 1;
			}

			if (speed_10 & half_duplex)
				ecmd->advertising |= ADVERTISED_10baseT_Half;
			if (speed_10 & full_duplex)
				ecmd->advertising |= ADVERTISED_10baseT_Full;
			if (speed_100 & half_duplex)
				ecmd->advertising |= ADVERTISED_100baseT_Half;
			if (speed_100 & full_duplex)
				ecmd->advertising |= ADVERTISED_100baseT_Full;
			if (speed_1000)
				ecmd->advertising |= ADVERTISED_1000baseT_Full;
		}
	}

	ecmd->port = PORT_TP;
	ecmd->phy_address = ethernet_phy_get(port_num);

	ecmd->transceiver = XCVR_EXTERNAL;

	if (netif_carrier_ok(netdev)) {
		if (mode_10_bit)
			ecmd->speed = SPEED_10;
		else {
			if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
				ecmd->speed = SPEED_1000;
			else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
				ecmd->speed = SPEED_100;
			else
				ecmd->speed = SPEED_10;
		}

		if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
			ecmd->duplex = DUPLEX_FULL;
		else
			ecmd->duplex = DUPLEX_HALF;
	} else {
		ecmd->speed = -1;
		ecmd->duplex = -1;
	}

	ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
	return 0;
}

static void
mv643xx_get_drvinfo(struct net_device *netdev,
                       struct ethtool_drvinfo *drvinfo)
{
	strncpy(drvinfo->driver,  mv643xx_driver_name, 32);
	strncpy(drvinfo->version, mv643xx_driver_version, 32);
	strncpy(drvinfo->fw_version, "N/A", 32);
	strncpy(drvinfo->bus_info, "mv643xx", 32);
	drvinfo->n_stats = MV643XX_STATS_LEN;
}

static int 
mv643xx_get_stats_count(struct net_device *netdev)
{
	return MV643XX_STATS_LEN;
}

static void 
mv643xx_get_ethtool_stats(struct net_device *netdev, 
		struct ethtool_stats *stats, uint64_t *data)
{
	struct mv643xx_private *mp = netdev->priv;
	int i;

	eth_update_mib_counters(mp);

	for(i = 0; i < MV643XX_STATS_LEN; i++) {
		char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;	
		data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == 
			sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
	}
}

static void 
mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
{
	int i;

	switch(stringset) {
	case ETH_SS_STATS:
		for (i=0; i < MV643XX_STATS_LEN; i++) {
			memcpy(data + i * ETH_GSTRING_LEN, 
			mv643xx_gstrings_stats[i].stat_string,
			ETH_GSTRING_LEN);
		}
		break;
	}
}

static struct ethtool_ops mv643xx_ethtool_ops = {
	.get_settings           = mv643xx_get_settings,
	.get_drvinfo            = mv643xx_get_drvinfo,
	.get_link               = ethtool_op_get_link,
	.get_sg			= ethtool_op_get_sg,
	.set_sg			= ethtool_op_set_sg,
	.get_strings            = mv643xx_get_strings,
	.get_stats_count        = mv643xx_get_stats_count,
	.get_ethtool_stats      = mv643xx_get_ethtool_stats,
};

/************* End ethtool support *************************/