summaryrefslogtreecommitdiff
path: root/include/dt-bindings/memory/mt8192-larb-port.h
blob: 23035a52c675a2e871f30e8d19bfb9ea3a836d95 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2020 MediaTek Inc.
 *
 * Author: Chao Hao <chao.hao@mediatek.com>
 * Author: Yong Wu <yong.wu@mediatek.com>
 */
#ifndef _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_
#define _DT_BINDINGS_MEMORY_MT8192_LARB_PORT_H_

#include <dt-bindings/memory/mtk-memory-port.h>

/*
 * MM IOMMU supports 16GB dma address.
 *
 * The address will preassign like this:
 *
 * modules    dma-address-region	larbs-ports
 * disp         0 ~ 4G                   larb0/1
 * vcodec      4G ~ 8G                  larb4/5/7
 * cam/mdp     8G ~ 12G             larb2/9/11/13/14/16/17/18/19/20
 * CCU0    0x4000_0000 ~ 0x43ff_ffff     larb13: port 9/10
 * CCU1    0x4400_0000 ~ 0x47ff_ffff     larb14: port 4/5
 *
 * larb3/6/8/10/12/15 is null.
 */

/* larb0 */
#define M4U_PORT_L0_DISP_POSTMASK0		MTK_M4U_ID(0, 0)
#define M4U_PORT_L0_OVL_RDMA0_HDR		MTK_M4U_ID(0, 1)
#define M4U_PORT_L0_OVL_RDMA0			MTK_M4U_ID(0, 2)
#define M4U_PORT_L0_DISP_RDMA0			MTK_M4U_ID(0, 3)
#define M4U_PORT_L0_DISP_WDMA0			MTK_M4U_ID(0, 4)
#define M4U_PORT_L0_DISP_FAKE0			MTK_M4U_ID(0, 5)

/* larb1 */
#define M4U_PORT_L1_OVL_2L_RDMA0_HDR		MTK_M4U_ID(1, 0)
#define M4U_PORT_L1_OVL_2L_RDMA2_HDR		MTK_M4U_ID(1, 1)
#define M4U_PORT_L1_OVL_2L_RDMA0		MTK_M4U_ID(1, 2)
#define M4U_PORT_L1_OVL_2L_RDMA2		MTK_M4U_ID(1, 3)
#define M4U_PORT_L1_DISP_MDP_RDMA4		MTK_M4U_ID(1, 4)
#define M4U_PORT_L1_DISP_RDMA4			MTK_M4U_ID(1, 5)
#define M4U_PORT_L1_DISP_UFBC_WDMA0		MTK_M4U_ID(1, 6)
#define M4U_PORT_L1_DISP_FAKE1			MTK_M4U_ID(1, 7)

/* larb2 */
#define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_ID(2, 0)
#define M4U_PORT_L2_MDP_RDMA1			MTK_M4U_ID(2, 1)
#define M4U_PORT_L2_MDP_WROT0			MTK_M4U_ID(2, 2)
#define M4U_PORT_L2_MDP_WROT1			MTK_M4U_ID(2, 3)
#define M4U_PORT_L2_MDP_DISP_FAKE0		MTK_M4U_ID(2, 4)

/* larb3: null */

/* larb4 */
#define M4U_PORT_L4_VDEC_MC_EXT			MTK_M4U_ID(4, 0)
#define M4U_PORT_L4_VDEC_UFO_EXT		MTK_M4U_ID(4, 1)
#define M4U_PORT_L4_VDEC_PP_EXT			MTK_M4U_ID(4, 2)
#define M4U_PORT_L4_VDEC_PRED_RD_EXT		MTK_M4U_ID(4, 3)
#define M4U_PORT_L4_VDEC_PRED_WR_EXT		MTK_M4U_ID(4, 4)
#define M4U_PORT_L4_VDEC_PPWRAP_EXT		MTK_M4U_ID(4, 5)
#define M4U_PORT_L4_VDEC_TILE_EXT		MTK_M4U_ID(4, 6)
#define M4U_PORT_L4_VDEC_VLD_EXT		MTK_M4U_ID(4, 7)
#define M4U_PORT_L4_VDEC_VLD2_EXT		MTK_M4U_ID(4, 8)
#define M4U_PORT_L4_VDEC_AVC_MV_EXT		MTK_M4U_ID(4, 9)
#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(4, 10)

/* larb5 */
#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT		MTK_M4U_ID(5, 0)
#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT		MTK_M4U_ID(5, 1)
#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT	MTK_M4U_ID(5, 2)
#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT	MTK_M4U_ID(5, 3)
#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT		MTK_M4U_ID(5, 4)
#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT		MTK_M4U_ID(5, 5)
#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT	MTK_M4U_ID(5, 6)
#define M4U_PORT_L5_VDEC_UFO_ENC_EXT		MTK_M4U_ID(5, 7)

/* larb6: null */

/* larb7 */
#define M4U_PORT_L7_VENC_RCPU			MTK_M4U_ID(7, 0)
#define M4U_PORT_L7_VENC_REC			MTK_M4U_ID(7, 1)
#define M4U_PORT_L7_VENC_BSDMA			MTK_M4U_ID(7, 2)
#define M4U_PORT_L7_VENC_SV_COMV		MTK_M4U_ID(7, 3)
#define M4U_PORT_L7_VENC_RD_COMV		MTK_M4U_ID(7, 4)
#define M4U_PORT_L7_VENC_CUR_LUMA		MTK_M4U_ID(7, 5)
#define M4U_PORT_L7_VENC_CUR_CHROMA		MTK_M4U_ID(7, 6)
#define M4U_PORT_L7_VENC_REF_LUMA		MTK_M4U_ID(7, 7)
#define M4U_PORT_L7_VENC_REF_CHROMA		MTK_M4U_ID(7, 8)
#define M4U_PORT_L7_JPGENC_Y_RDMA		MTK_M4U_ID(7, 9)
#define M4U_PORT_L7_JPGENC_Q_RDMA		MTK_M4U_ID(7, 10)
#define M4U_PORT_L7_JPGENC_C_TABLE		MTK_M4U_ID(7, 11)
#define M4U_PORT_L7_JPGENC_BSDMA		MTK_M4U_ID(7, 12)
#define M4U_PORT_L7_VENC_SUB_R_LUMA		MTK_M4U_ID(7, 13)
#define M4U_PORT_L7_VENC_SUB_W_LUMA		MTK_M4U_ID(7, 14)

/* larb8: null */

/* larb9 */
#define M4U_PORT_L9_IMG_IMGI_D1			MTK_M4U_ID(9, 0)
#define M4U_PORT_L9_IMG_IMGBI_D1		MTK_M4U_ID(9, 1)
#define M4U_PORT_L9_IMG_DMGI_D1			MTK_M4U_ID(9, 2)
#define M4U_PORT_L9_IMG_DEPI_D1			MTK_M4U_ID(9, 3)
#define M4U_PORT_L9_IMG_ICE_D1			MTK_M4U_ID(9, 4)
#define M4U_PORT_L9_IMG_SMTI_D1			MTK_M4U_ID(9, 5)
#define M4U_PORT_L9_IMG_SMTO_D2			MTK_M4U_ID(9, 6)
#define M4U_PORT_L9_IMG_SMTO_D1			MTK_M4U_ID(9, 7)
#define M4U_PORT_L9_IMG_CRZO_D1			MTK_M4U_ID(9, 8)
#define M4U_PORT_L9_IMG_IMG3O_D1		MTK_M4U_ID(9, 9)
#define M4U_PORT_L9_IMG_VIPI_D1			MTK_M4U_ID(9, 10)
#define M4U_PORT_L9_IMG_SMTI_D5			MTK_M4U_ID(9, 11)
#define M4U_PORT_L9_IMG_TIMGO_D1		MTK_M4U_ID(9, 12)
#define M4U_PORT_L9_IMG_UFBC_W0			MTK_M4U_ID(9, 13)
#define M4U_PORT_L9_IMG_UFBC_R0			MTK_M4U_ID(9, 14)

/* larb10: null */

/* larb11 */
#define M4U_PORT_L11_IMG_IMGI_D1		MTK_M4U_ID(11, 0)
#define M4U_PORT_L11_IMG_IMGBI_D1		MTK_M4U_ID(11, 1)
#define M4U_PORT_L11_IMG_DMGI_D1		MTK_M4U_ID(11, 2)
#define M4U_PORT_L11_IMG_DEPI_D1		MTK_M4U_ID(11, 3)
#define M4U_PORT_L11_IMG_ICE_D1			MTK_M4U_ID(11, 4)
#define M4U_PORT_L11_IMG_SMTI_D1		MTK_M4U_ID(11, 5)
#define M4U_PORT_L11_IMG_SMTO_D2		MTK_M4U_ID(11, 6)
#define M4U_PORT_L11_IMG_SMTO_D1		MTK_M4U_ID(11, 7)
#define M4U_PORT_L11_IMG_CRZO_D1		MTK_M4U_ID(11, 8)
#define M4U_PORT_L11_IMG_IMG3O_D1		MTK_M4U_ID(11, 9)
#define M4U_PORT_L11_IMG_VIPI_D1		MTK_M4U_ID(11, 10)
#define M4U_PORT_L11_IMG_SMTI_D5		MTK_M4U_ID(11, 11)
#define M4U_PORT_L11_IMG_TIMGO_D1		MTK_M4U_ID(11, 12)
#define M4U_PORT_L11_IMG_UFBC_W0		MTK_M4U_ID(11, 13)
#define M4U_PORT_L11_IMG_UFBC_R0		MTK_M4U_ID(11, 14)
#define M4U_PORT_L11_IMG_WPE_RDMA1		MTK_M4U_ID(11, 15)
#define M4U_PORT_L11_IMG_WPE_RDMA0		MTK_M4U_ID(11, 16)
#define M4U_PORT_L11_IMG_WPE_WDMA		MTK_M4U_ID(11, 17)
#define M4U_PORT_L11_IMG_MFB_RDMA0		MTK_M4U_ID(11, 18)
#define M4U_PORT_L11_IMG_MFB_RDMA1		MTK_M4U_ID(11, 19)
#define M4U_PORT_L11_IMG_MFB_RDMA2		MTK_M4U_ID(11, 20)
#define M4U_PORT_L11_IMG_MFB_RDMA3		MTK_M4U_ID(11, 21)
#define M4U_PORT_L11_IMG_MFB_RDMA4		MTK_M4U_ID(11, 22)
#define M4U_PORT_L11_IMG_MFB_RDMA5		MTK_M4U_ID(11, 23)
#define M4U_PORT_L11_IMG_MFB_WDMA0		MTK_M4U_ID(11, 24)
#define M4U_PORT_L11_IMG_MFB_WDMA1		MTK_M4U_ID(11, 25)

/* larb12: null */

/* larb13 */
#define M4U_PORT_L13_CAM_MRAWI			MTK_M4U_ID(13, 0)
#define M4U_PORT_L13_CAM_MRAWO0			MTK_M4U_ID(13, 1)
#define M4U_PORT_L13_CAM_MRAWO1			MTK_M4U_ID(13, 2)
#define M4U_PORT_L13_CAM_CAMSV1			MTK_M4U_ID(13, 3)
#define M4U_PORT_L13_CAM_CAMSV2			MTK_M4U_ID(13, 4)
#define M4U_PORT_L13_CAM_CAMSV3			MTK_M4U_ID(13, 5)
#define M4U_PORT_L13_CAM_CAMSV4			MTK_M4U_ID(13, 6)
#define M4U_PORT_L13_CAM_CAMSV5			MTK_M4U_ID(13, 7)
#define M4U_PORT_L13_CAM_CAMSV6			MTK_M4U_ID(13, 8)
#define M4U_PORT_L13_CAM_CCUI			MTK_M4U_ID(13, 9)
#define M4U_PORT_L13_CAM_CCUO			MTK_M4U_ID(13, 10)
#define M4U_PORT_L13_CAM_FAKE			MTK_M4U_ID(13, 11)

/* larb14 */
#define M4U_PORT_L14_CAM_RESERVE1		MTK_M4U_ID(14, 0)
#define M4U_PORT_L14_CAM_RESERVE2		MTK_M4U_ID(14, 1)
#define M4U_PORT_L14_CAM_RESERVE3		MTK_M4U_ID(14, 2)
#define M4U_PORT_L14_CAM_CAMSV0			MTK_M4U_ID(14, 3)
#define M4U_PORT_L14_CAM_CCUI			MTK_M4U_ID(14, 4)
#define M4U_PORT_L14_CAM_CCUO			MTK_M4U_ID(14, 5)

/* larb15: null */

/* larb16 */
#define M4U_PORT_L16_CAM_IMGO_R1_A		MTK_M4U_ID(16, 0)
#define M4U_PORT_L16_CAM_RRZO_R1_A		MTK_M4U_ID(16, 1)
#define M4U_PORT_L16_CAM_CQI_R1_A		MTK_M4U_ID(16, 2)
#define M4U_PORT_L16_CAM_BPCI_R1_A		MTK_M4U_ID(16, 3)
#define M4U_PORT_L16_CAM_YUVO_R1_A		MTK_M4U_ID(16, 4)
#define M4U_PORT_L16_CAM_UFDI_R2_A		MTK_M4U_ID(16, 5)
#define M4U_PORT_L16_CAM_RAWI_R2_A		MTK_M4U_ID(16, 6)
#define M4U_PORT_L16_CAM_RAWI_R3_A		MTK_M4U_ID(16, 7)
#define M4U_PORT_L16_CAM_AAO_R1_A		MTK_M4U_ID(16, 8)
#define M4U_PORT_L16_CAM_AFO_R1_A		MTK_M4U_ID(16, 9)
#define M4U_PORT_L16_CAM_FLKO_R1_A		MTK_M4U_ID(16, 10)
#define M4U_PORT_L16_CAM_LCESO_R1_A		MTK_M4U_ID(16, 11)
#define M4U_PORT_L16_CAM_CRZO_R1_A		MTK_M4U_ID(16, 12)
#define M4U_PORT_L16_CAM_LTMSO_R1_A		MTK_M4U_ID(16, 13)
#define M4U_PORT_L16_CAM_RSSO_R1_A		MTK_M4U_ID(16, 14)
#define M4U_PORT_L16_CAM_AAHO_R1_A		MTK_M4U_ID(16, 15)
#define M4U_PORT_L16_CAM_LSCI_R1_A		MTK_M4U_ID(16, 16)

/* larb17 */
#define M4U_PORT_L17_CAM_IMGO_R1_B		MTK_M4U_ID(17, 0)
#define M4U_PORT_L17_CAM_RRZO_R1_B		MTK_M4U_ID(17, 1)
#define M4U_PORT_L17_CAM_CQI_R1_B		MTK_M4U_ID(17, 2)
#define M4U_PORT_L17_CAM_BPCI_R1_B		MTK_M4U_ID(17, 3)
#define M4U_PORT_L17_CAM_YUVO_R1_B		MTK_M4U_ID(17, 4)
#define M4U_PORT_L17_CAM_UFDI_R2_B		MTK_M4U_ID(17, 5)
#define M4U_PORT_L17_CAM_RAWI_R2_B		MTK_M4U_ID(17, 6)
#define M4U_PORT_L17_CAM_RAWI_R3_B		MTK_M4U_ID(17, 7)
#define M4U_PORT_L17_CAM_AAO_R1_B		MTK_M4U_ID(17, 8)
#define M4U_PORT_L17_CAM_AFO_R1_B		MTK_M4U_ID(17, 9)
#define M4U_PORT_L17_CAM_FLKO_R1_B		MTK_M4U_ID(17, 10)
#define M4U_PORT_L17_CAM_LCESO_R1_B		MTK_M4U_ID(17, 11)
#define M4U_PORT_L17_CAM_CRZO_R1_B		MTK_M4U_ID(17, 12)
#define M4U_PORT_L17_CAM_LTMSO_R1_B		MTK_M4U_ID(17, 13)
#define M4U_PORT_L17_CAM_RSSO_R1_B		MTK_M4U_ID(17, 14)
#define M4U_PORT_L17_CAM_AAHO_R1_B		MTK_M4U_ID(17, 15)
#define M4U_PORT_L17_CAM_LSCI_R1_B		MTK_M4U_ID(17, 16)

/* larb18 */
#define M4U_PORT_L18_CAM_IMGO_R1_C		MTK_M4U_ID(18, 0)
#define M4U_PORT_L18_CAM_RRZO_R1_C		MTK_M4U_ID(18, 1)
#define M4U_PORT_L18_CAM_CQI_R1_C		MTK_M4U_ID(18, 2)
#define M4U_PORT_L18_CAM_BPCI_R1_C		MTK_M4U_ID(18, 3)
#define M4U_PORT_L18_CAM_YUVO_R1_C		MTK_M4U_ID(18, 4)
#define M4U_PORT_L18_CAM_UFDI_R2_C		MTK_M4U_ID(18, 5)
#define M4U_PORT_L18_CAM_RAWI_R2_C		MTK_M4U_ID(18, 6)
#define M4U_PORT_L18_CAM_RAWI_R3_C		MTK_M4U_ID(18, 7)
#define M4U_PORT_L18_CAM_AAO_R1_C		MTK_M4U_ID(18, 8)
#define M4U_PORT_L18_CAM_AFO_R1_C		MTK_M4U_ID(18, 9)
#define M4U_PORT_L18_CAM_FLKO_R1_C		MTK_M4U_ID(18, 10)
#define M4U_PORT_L18_CAM_LCESO_R1_C		MTK_M4U_ID(18, 11)
#define M4U_PORT_L18_CAM_CRZO_R1_C		MTK_M4U_ID(18, 12)
#define M4U_PORT_L18_CAM_LTMSO_R1_C		MTK_M4U_ID(18, 13)
#define M4U_PORT_L18_CAM_RSSO_R1_C		MTK_M4U_ID(18, 14)
#define M4U_PORT_L18_CAM_AAHO_R1_C		MTK_M4U_ID(18, 15)
#define M4U_PORT_L18_CAM_LSCI_R1_C		MTK_M4U_ID(18, 16)

/* larb19 */
#define M4U_PORT_L19_IPE_DVS_RDMA		MTK_M4U_ID(19, 0)
#define M4U_PORT_L19_IPE_DVS_WDMA		MTK_M4U_ID(19, 1)
#define M4U_PORT_L19_IPE_DVP_RDMA		MTK_M4U_ID(19, 2)
#define M4U_PORT_L19_IPE_DVP_WDMA		MTK_M4U_ID(19, 3)

/* larb20 */
#define M4U_PORT_L20_IPE_FDVT_RDA		MTK_M4U_ID(20, 0)
#define M4U_PORT_L20_IPE_FDVT_RDB		MTK_M4U_ID(20, 1)
#define M4U_PORT_L20_IPE_FDVT_WRA		MTK_M4U_ID(20, 2)
#define M4U_PORT_L20_IPE_FDVT_WRB		MTK_M4U_ID(20, 3)
#define M4U_PORT_L20_IPE_RSC_RDMA0		MTK_M4U_ID(20, 4)
#define M4U_PORT_L20_IPE_RSC_WDMA		MTK_M4U_ID(20, 5)

#endif