summaryrefslogtreecommitdiff
path: root/include/dt-bindings/mux/ti-serdes.h
blob: b0b1091aad6d7222f311dae3d1ba602a8aa26a20 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * This header provides constants for SERDES MUX for TI SoCs
 */

#ifndef _DT_BINDINGS_MUX_TI_SERDES
#define _DT_BINDINGS_MUX_TI_SERDES

/*
 * These bindings are deprecated, because they do not match the actual
 * concept of bindings but rather contain pure constants values used only
 * in DTS board files.
 * Instead include the header in the DTS source directory.
 */
#warning "These bindings are deprecated. Instead, use the header in the DTS source directory."

/* J721E */

#define J721E_SERDES0_LANE0_QSGMII_LANE1	0x0
#define J721E_SERDES0_LANE0_PCIE0_LANE0		0x1
#define J721E_SERDES0_LANE0_USB3_0_SWAP		0x2
#define J721E_SERDES0_LANE0_IP4_UNUSED		0x3

#define J721E_SERDES0_LANE1_QSGMII_LANE2	0x0
#define J721E_SERDES0_LANE1_PCIE0_LANE1		0x1
#define J721E_SERDES0_LANE1_USB3_0		0x2
#define J721E_SERDES0_LANE1_IP4_UNUSED		0x3

#define J721E_SERDES1_LANE0_QSGMII_LANE3	0x0
#define J721E_SERDES1_LANE0_PCIE1_LANE0		0x1
#define J721E_SERDES1_LANE0_USB3_1_SWAP		0x2
#define J721E_SERDES1_LANE0_SGMII_LANE0		0x3

#define J721E_SERDES1_LANE1_QSGMII_LANE4	0x0
#define J721E_SERDES1_LANE1_PCIE1_LANE1		0x1
#define J721E_SERDES1_LANE1_USB3_1		0x2
#define J721E_SERDES1_LANE1_SGMII_LANE1		0x3

#define J721E_SERDES2_LANE0_IP1_UNUSED		0x0
#define J721E_SERDES2_LANE0_PCIE2_LANE0		0x1
#define J721E_SERDES2_LANE0_USB3_1_SWAP		0x2
#define J721E_SERDES2_LANE0_SGMII_LANE0		0x3

#define J721E_SERDES2_LANE1_IP1_UNUSED		0x0
#define J721E_SERDES2_LANE1_PCIE2_LANE1		0x1
#define J721E_SERDES2_LANE1_USB3_1		0x2
#define J721E_SERDES2_LANE1_SGMII_LANE1		0x3

#define J721E_SERDES3_LANE0_IP1_UNUSED		0x0
#define J721E_SERDES3_LANE0_PCIE3_LANE0		0x1
#define J721E_SERDES3_LANE0_USB3_0_SWAP		0x2
#define J721E_SERDES3_LANE0_IP4_UNUSED		0x3

#define J721E_SERDES3_LANE1_IP1_UNUSED		0x0
#define J721E_SERDES3_LANE1_PCIE3_LANE1		0x1
#define J721E_SERDES3_LANE1_USB3_0		0x2
#define J721E_SERDES3_LANE1_IP4_UNUSED		0x3

#define J721E_SERDES4_LANE0_EDP_LANE0		0x0
#define J721E_SERDES4_LANE0_IP2_UNUSED		0x1
#define J721E_SERDES4_LANE0_QSGMII_LANE5	0x2
#define J721E_SERDES4_LANE0_IP4_UNUSED		0x3

#define J721E_SERDES4_LANE1_EDP_LANE1		0x0
#define J721E_SERDES4_LANE1_IP2_UNUSED		0x1
#define J721E_SERDES4_LANE1_QSGMII_LANE6	0x2
#define J721E_SERDES4_LANE1_IP4_UNUSED		0x3

#define J721E_SERDES4_LANE2_EDP_LANE2		0x0
#define J721E_SERDES4_LANE2_IP2_UNUSED		0x1
#define J721E_SERDES4_LANE2_QSGMII_LANE7	0x2
#define J721E_SERDES4_LANE2_IP4_UNUSED		0x3

#define J721E_SERDES4_LANE3_EDP_LANE3		0x0
#define J721E_SERDES4_LANE3_IP2_UNUSED		0x1
#define J721E_SERDES4_LANE3_QSGMII_LANE8	0x2
#define J721E_SERDES4_LANE3_IP4_UNUSED		0x3

/* J7200 */

#define J7200_SERDES0_LANE0_QSGMII_LANE3	0x0
#define J7200_SERDES0_LANE0_PCIE1_LANE0		0x1
#define J7200_SERDES0_LANE0_IP3_UNUSED		0x2
#define J7200_SERDES0_LANE0_IP4_UNUSED		0x3

#define J7200_SERDES0_LANE1_QSGMII_LANE4	0x0
#define J7200_SERDES0_LANE1_PCIE1_LANE1		0x1
#define J7200_SERDES0_LANE1_IP3_UNUSED		0x2
#define J7200_SERDES0_LANE1_IP4_UNUSED		0x3

#define J7200_SERDES0_LANE2_QSGMII_LANE1	0x0
#define J7200_SERDES0_LANE2_PCIE1_LANE2		0x1
#define J7200_SERDES0_LANE2_IP3_UNUSED		0x2
#define J7200_SERDES0_LANE2_IP4_UNUSED		0x3

#define J7200_SERDES0_LANE3_QSGMII_LANE2	0x0
#define J7200_SERDES0_LANE3_PCIE1_LANE3		0x1
#define J7200_SERDES0_LANE3_USB			0x2
#define J7200_SERDES0_LANE3_IP4_UNUSED		0x3

/* AM64 */

#define AM64_SERDES0_LANE0_PCIE0		0x0
#define AM64_SERDES0_LANE0_USB			0x1

/* J721S2 */

#define J721S2_SERDES0_LANE0_EDP_LANE0		0x0
#define J721S2_SERDES0_LANE0_PCIE1_LANE0	0x1
#define J721S2_SERDES0_LANE0_IP3_UNUSED		0x2
#define J721S2_SERDES0_LANE0_IP4_UNUSED		0x3

#define J721S2_SERDES0_LANE1_EDP_LANE1		0x0
#define J721S2_SERDES0_LANE1_PCIE1_LANE1	0x1
#define J721S2_SERDES0_LANE1_USB		0x2
#define J721S2_SERDES0_LANE1_IP4_UNUSED		0x3

#define J721S2_SERDES0_LANE2_EDP_LANE2		0x0
#define J721S2_SERDES0_LANE2_PCIE1_LANE2	0x1
#define J721S2_SERDES0_LANE2_IP3_UNUSED		0x2
#define J721S2_SERDES0_LANE2_IP4_UNUSED		0x3

#define J721S2_SERDES0_LANE3_EDP_LANE3		0x0
#define J721S2_SERDES0_LANE3_PCIE1_LANE3	0x1
#define J721S2_SERDES0_LANE3_USB		0x2
#define J721S2_SERDES0_LANE3_IP4_UNUSED		0x3

/* J784S4 */

#define J784S4_SERDES0_LANE0_IP1_UNUSED		0x0
#define J784S4_SERDES0_LANE0_PCIE1_LANE0	0x1
#define J784S4_SERDES0_LANE0_IP3_UNUSED		0x2
#define J784S4_SERDES0_LANE0_IP4_UNUSED		0x3

#define J784S4_SERDES0_LANE1_IP1_UNUSED		0x0
#define J784S4_SERDES0_LANE1_PCIE1_LANE1	0x1
#define J784S4_SERDES0_LANE1_IP3_UNUSED		0x2
#define J784S4_SERDES0_LANE1_IP4_UNUSED		0x3

#define J784S4_SERDES0_LANE2_PCIE3_LANE0	0x0
#define J784S4_SERDES0_LANE2_PCIE1_LANE2	0x1
#define J784S4_SERDES0_LANE2_IP3_UNUSED		0x2
#define J784S4_SERDES0_LANE2_IP4_UNUSED		0x3

#define J784S4_SERDES0_LANE3_PCIE3_LANE1	0x0
#define J784S4_SERDES0_LANE3_PCIE1_LANE3	0x1
#define J784S4_SERDES0_LANE3_USB		0x2
#define J784S4_SERDES0_LANE3_IP4_UNUSED		0x3

#define J784S4_SERDES1_LANE0_QSGMII_LANE3	0x0
#define J784S4_SERDES1_LANE0_PCIE0_LANE0	0x1
#define J784S4_SERDES1_LANE0_IP3_UNUSED		0x2
#define J784S4_SERDES1_LANE0_IP4_UNUSED		0x3

#define J784S4_SERDES1_LANE1_QSGMII_LANE4	0x0
#define J784S4_SERDES1_LANE1_PCIE0_LANE1	0x1
#define J784S4_SERDES1_LANE1_IP3_UNUSED		0x2
#define J784S4_SERDES1_LANE1_IP4_UNUSED		0x3

#define J784S4_SERDES1_LANE2_QSGMII_LANE1	0x0
#define J784S4_SERDES1_LANE2_PCIE0_LANE2	0x1
#define J784S4_SERDES1_LANE2_PCIE2_LANE0	0x2
#define J784S4_SERDES1_LANE2_IP4_UNUSED		0x3

#define J784S4_SERDES1_LANE3_QSGMII_LANE2	0x0
#define J784S4_SERDES1_LANE3_PCIE0_LANE3	0x1
#define J784S4_SERDES1_LANE3_PCIE2_LANE1	0x2
#define J784S4_SERDES1_LANE3_IP4_UNUSED		0x3

#define J784S4_SERDES2_LANE0_QSGMII_LANE5	0x0
#define J784S4_SERDES2_LANE0_IP2_UNUSED		0x1
#define J784S4_SERDES2_LANE0_IP3_UNUSED		0x2
#define J784S4_SERDES2_LANE0_IP4_UNUSED		0x3

#define J784S4_SERDES2_LANE1_QSGMII_LANE6	0x0
#define J784S4_SERDES2_LANE1_IP2_UNUSED		0x1
#define J784S4_SERDES2_LANE1_IP3_UNUSED		0x2
#define J784S4_SERDES2_LANE1_IP4_UNUSED		0x3

#define J784S4_SERDES2_LANE2_QSGMII_LANE7	0x0
#define J784S4_SERDES2_LANE2_QSGMII_LANE1	0x1
#define J784S4_SERDES2_LANE2_IP3_UNUSED		0x2
#define J784S4_SERDES2_LANE2_IP4_UNUSED		0x3

#define J784S4_SERDES2_LANE3_QSGMII_LANE8	0x0
#define J784S4_SERDES2_LANE3_QSGMII_LANE2	0x1
#define J784S4_SERDES2_LANE3_IP3_UNUSED		0x2
#define J784S4_SERDES2_LANE3_IP4_UNUSED		0x3

#endif /* _DT_BINDINGS_MUX_TI_SERDES */