summaryrefslogtreecommitdiff
path: root/tools/perf/pmu-events/arch/s390/cf_z15/extended.json
blob: 2df2e231e9eed6d2e4b8f708aa556fc18c1ebecd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
[
	{
		"Unit": "CPU-M-CF",
		"EventCode": "128",
		"EventName": "L1D_RO_EXCL_WRITES",
		"BriefDescription": "L1D Read-only Exclusive Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "129",
		"EventName": "DTLB2_WRITES",
		"BriefDescription": "DTLB2 Writes",
		"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "130",
		"EventName": "DTLB2_MISSES",
		"BriefDescription": "DTLB2 Misses",
		"PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "131",
		"EventName": "DTLB2_HPAGE_WRITES",
		"BriefDescription": "DTLB2 One-Megabyte Page Writes",
		"PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "132",
		"EventName": "DTLB2_GPAGE_WRITES",
		"BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
		"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "133",
		"EventName": "L1D_L2D_SOURCED_WRITES",
		"BriefDescription": "L1D L2D Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "134",
		"EventName": "ITLB2_WRITES",
		"BriefDescription": "ITLB2 Writes",
		"PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "135",
		"EventName": "ITLB2_MISSES",
		"BriefDescription": "ITLB2 Misses",
		"PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "136",
		"EventName": "L1I_L2I_SOURCED_WRITES",
		"BriefDescription": "L1I L2I Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "137",
		"EventName": "TLB2_PTE_WRITES",
		"BriefDescription": "TLB2 PTE Writes",
		"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "138",
		"EventName": "TLB2_CRSTE_WRITES",
		"BriefDescription": "TLB2 CRSTE Writes",
		"PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "139",
		"EventName": "TLB2_ENGINES_BUSY",
		"BriefDescription": "TLB2 Engines Busy",
		"PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "140",
		"EventName": "TX_C_TEND",
		"BriefDescription": "Completed TEND instructions in constrained TX mode",
		"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "141",
		"EventName": "TX_NC_TEND",
		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
		"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "143",
		"EventName": "L1C_TLB2_MISSES",
		"BriefDescription": "L1C TLB2 Misses",
		"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "144",
		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
		"BriefDescription": "L1D On-Chip L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "145",
		"EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES",
		"BriefDescription": "L1D On-Chip Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "146",
		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "147",
		"EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES",
		"BriefDescription": "L1D On-Cluster L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "148",
		"EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES",
		"BriefDescription": "L1D On-Cluster Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "149",
		"EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "150",
		"EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Cluster L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "151",
		"EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Cluster Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "152",
		"EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "153",
		"EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Drawer L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "154",
		"EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "155",
		"EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "156",
		"EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
		"BriefDescription": "L1D On-Drawer L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "157",
		"EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES",
		"BriefDescription": "L1D Off-Drawer L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "158",
		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO",
		"BriefDescription": "L1D On-Chip L3 Sourced Writes read-only",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "162",
		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
		"BriefDescription": "L1I On-Chip L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "163",
		"EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES",
		"BriefDescription": "L1I On-Chip Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "164",
		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "165",
		"EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES",
		"BriefDescription": "L1I On-Cluster L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "166",
		"EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES",
		"BriefDescription": "L1I On-Cluster Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "167",
		"EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "168",
		"EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES",
		"BriefDescription": "L1I Off-Cluster L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "169",
		"EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES",
		"BriefDescription": "L1I Off-Cluster Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "170",
		"EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "171",
		"EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES",
		"BriefDescription": "L1I Off-Drawer L3 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "172",
		"EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES",
		"BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "173",
		"EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV",
		"BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "174",
		"EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
		"BriefDescription": "L1I On-Drawer L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "175",
		"EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES",
		"BriefDescription": "L1I Off-Drawer L4 Sourced Writes",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "224",
		"EventName": "BCD_DFP_EXECUTION_SLOTS",
		"BriefDescription": "BCD DFP Execution Slots",
		"PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "225",
		"EventName": "VX_BCD_EXECUTION_SLOTS",
		"BriefDescription": "VX BCD Execution Slots",
		"PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "226",
		"EventName": "DECIMAL_INSTRUCTIONS",
		"BriefDescription": "Decimal Instructions",
		"PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "232",
		"EventName": "LAST_HOST_TRANSLATIONS",
		"BriefDescription": "Last host translation done",
		"PublicDescription": "Last Host Translation done"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "243",
		"EventName": "TX_NC_TABORT",
		"BriefDescription": "Aborted transactions in non-constrained TX mode",
		"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "244",
		"EventName": "TX_C_TABORT_NO_SPECIAL",
		"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "245",
		"EventName": "TX_C_TABORT_SPECIAL",
		"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "247",
		"EventName": "DFLT_ACCESS",
		"BriefDescription": "Cycles CPU spent obtaining access to Deflate unit",
		"PublicDescription": "Cycles CPU spent obtaining access to Deflate unit"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "252",
		"EventName": "DFLT_CYCLES",
		"BriefDescription": "Cycles CPU is using Deflate unit",
		"PublicDescription": "Cycles CPU is using Deflate unit"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "264",
		"EventName": "DFLT_CC",
		"BriefDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed",
		"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "265",
		"EventName": "DFLT_CCERROR",
		"BriefDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2",
		"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "448",
		"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
		"BriefDescription": "Cycle count with one thread active",
		"PublicDescription": "Cycle count with one thread active"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "449",
		"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
		"BriefDescription": "Cycle count with two threads active",
		"PublicDescription": "Cycle count with two threads active"
	},
]