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2025-07-04ARM: dts: aspeed: catalina: Enable MCTP for frontend NIC managementPotin Lai
Add the `mctp-controller` property and MCTP nodes to enable support for frontend NIC management via PLDM over MCTP. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://patch.msgid.link/20250611-catalina-mctp-i2c-10-15-v1-1-2a882e461ed9@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2025-07-03clk: sunxi-ng: v3s: Fix CSI SCLK clock namePaul Kocialkowski
The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the documentation. Fix the name in the driver, header and device-tree. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Reviewed-By: Icenowy Zheng <uwu@icenowy.me> Link: https://patch.msgid.link/20250701201124.812882-3-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-03ARM: dts: lpc32xx: Add #pwm-cells property to the two SoC PWMsUwe Kleine-König
If these PWMs are to be used, a #pwm-cells property is necessary. The right location for that is in the SoC's dtsi file to not make machine.dts files repeat the value for each usage. Currently the machines based on nxp/lpc/lpc32xx.dtsi don't make use of the PWMs, so there are no properties to drop there. Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-03Merge tag 'arm-soc/for-6.17/devicetree' of ↵Arnd Bergmann
https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM-based SoCs Device Tree updates for 6.17, please pull the following: - Linus makes a number of updates to the BCMBCA SoCs Device Tree files to correct UART interrupt numbers, add interrupts to the RNG block, and leverage the fact that all SoCs have the same peripherals at the same aperture - Uwe corrects the Merakia MX6X DTS file to have #pwm-cells = 3 as per the binding * tag 'arm-soc/for-6.17/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: bcm958625-meraki-mx6x: Use #pwm-cells = <3> ARM: dts: bcm63178: Add BCMBCA peripherals ARM: dts: bcm63148: Add BCMBCA peripherals ARM: dts: bcm63138: Add BCMBCA peripherals ARM: dts: bcm6878: Add BCMBCA peripherals ARM: dts: bcm6855: Add BCMBCA peripherals ARM: dts: bcm6846: Add interrupt to RNG dt-bindings: rng: r200: Add interrupt property ARM: dts: bcm6878: Correct UART0 IRQ number Link: https://lore.kernel.org/r/20250630190216.1518354-2-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-07-02ARM: dts: sun8i: v3: Add RGB666 LCD PD pins definitionPaul Kocialkowski
The V3 supports RGB666 LCD output on PD pins, which are not available on the V3s package. Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Link: https://patch.msgid.link/20250701201534.815513-2-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-02ARM: dts: sun8i: v3s: Add RGB666 LCD PE pins definitionPaul Kocialkowski
The V3s (and other packages) supports RGB666 LCD output on PE pins. Signed-off-by: Paul Kocialkowski <paulk@sys-base.io> Link: https://patch.msgid.link/20250701201534.815513-1-paulk@sys-base.io Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-07-02ARM: dts: imx6ul: support Engicam MicroGEA GTW boardDario Binacchi
Support Engicam MicroGEA GTW board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Buttons - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-02ARM: dts: imx6ul: support Engicam MicroGEA RMM boardDario Binacchi
Support Engicam MicroGEA RMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - LEDs - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-02ARM: dts: imx6ul: support Engicam MicroGEA BMM boardDario Binacchi
Support Engicam MicroGEA BMM board with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - CAN - Micro SD card connector - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-02ARM: dts: imx6ul: support Engicam MicroGEA-MX6UL SoMDario Binacchi
Support Engicam MicroGEA-MX6UL SoM with: - 256 Mbytes NAND Flash - 512 Mbytes DRAM DDR2 - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-01ARM: dts: mxs: support i.MX28 Amarula rmm boardDario Binacchi
The board includes the following resources: - 256 Mbytes NAND Flash - 128 Mbytes DRAM DDR2 - CAN - USB 2.0 high-speed/full-speed - Ethernet MAC Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-07-01ARM: dts: imx28: add pwm7 muxing optionsDario Binacchi
Add alternative pinmuxing for pwm7. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-30arm: dts: omap: Add support for BeagleBone Green Eco boardKory Maincent
SeeedStudio BeagleBone Green Eco (BBGE) is a clone of the BeagleBone Green (BBG). It has minor differences from the BBG, such as a different PMIC, a different Ethernet PHY, and a larger eMMC. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Andreas Kemnade <andreas@kemnade.info> Tested-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250620-bbg-v5-3-84f9b9a2e3a8@bootlin.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-06-30arm: dts: omap: am335x-bone-common: Rename tps to generic pmic nodeKory Maincent
Rename tps@24 to the generic pmic@24 node name. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Andreas Kemnade <andreas@kemnade.info> Tested-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250620-bbg-v5-1-84f9b9a2e3a8@bootlin.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-06-27ARM: dts: Fix up wrv54g device treeLinus Walleij
Fix up the KS8995 switch and PHYs the way that is most likely: - Phy 1-4 is certainly the PHYs of the KS8995 (mask 0x1e in the outoftree code masks PHYs 1,2,3,4). - Phy 5 is the MII-P5 separate WAN phy of the KS8995 directly connected to EthC. - The EthB MII is probably connected as CPU interface to the KS8995. Properly integrate the KS8995 switch using the new bindings. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250625-ks8995-dsa-bindings-v2-2-ce71dce9be0b@linaro.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-06-25ARM: dts: microchip: sam9x7: Add LVDS controllerDharma Balasubiramani
Add support for LVDS controller. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Link: https://lore.kernel.org/r/20250625-b4-sam9x7-dts-v1-1-92aaee14ed16@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-25ARM: dts: s5pv210: Align i2c-gpio node names with dtschemaKrzysztof Kozlowski
New dtschema v2025.6 enforces different naming on I2C nodes thus new dtbs_check warnings appeared for I2C GPIO nodes: s5pv210-fascinate4g.dtb: i2c-gpio-0 (i2c-gpio): $nodename:0: 'i2c-gpio-0' does not match '^i2c(@.+|-[a-z0-9]+)?$' s5pv210-fascinate4g.dtb: i2c-gpio-0 (i2c-gpio): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'audio-codec@1a' were unexpected) Rename the nodes to a generic i2c-[0-9]+ style with numbers continuing the SoC I2C controller indexing (3 controllers) for simplicity and obviousness, even if the SoC I2C controller is not enabled on given board. The names anyway would not conflict with SoC ones because of unit addresses. Verified with comparing two fdt (after fdtdump). Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Closes: https://lore.kernel.org/all/aCtD7BH5N_uPGkq7@shikoro/ Link: https://lore.kernel.org/r/20250612094807.62532-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-25ARM: dts: exynos: Align i2c-gpio node names with dtschemaKrzysztof Kozlowski
New dtschema v2025.6 enforces different naming on I2C nodes thus new dtbs_check warnings appeared for I2C GPIO nodes: exynos4212-tab3-lte8.dtb: i2c-gpio-3 (i2c-gpio): $nodename:0: 'i2c-gpio-3' does not match '^i2c(@.+|-[a-z0-9]+)?$' exynos4212-tab3-lte8.dtb: i2c-gpio-3 (i2c-gpio): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'magnetometer@2e' were unexpected) Rename the nodes to a generic i2c-[0-9]+ style with numbers continuing the SoC I2C controller indexing (Exynos3250: 8 controllers, Exynos4: 9 controllers) for simplicity and obviousness, even if the SoC I2C controller is not enabled on given board. The names anyway would not conflict with SoC ones because of unit addresses. Verified with comparing two fdt (after fdtdump). Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Closes: https://lore.kernel.org/all/aCtD7BH5N_uPGkq7@shikoro/ Link: https://lore.kernel.org/r/20250612094807.62532-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-24ARM: dts: microchip: sama5d2_icp: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 46a8a137d8f6 ("ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250521054309.361894-4-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-24ARM: dts: microchip: sama5d27_wlsom1: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 417e58ea41ab ("ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250521054309.361894-3-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-24ARM: dts: microchip: sama5d27_som1: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 09ce8651229b ("ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250521054309.361894-2-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-24ARM: dts: microchip: sam9x60ek: rename spi-cs-setup-ns property to ↵Manikandan Muralidharan
spi-cs-setup-delay-ns The naming scheme for delay properties includes "delay" in the name, so renaming spi-cs-setup-ns property to spi-cs-setup-delay-ns. Fixes: 2c0a1faa4da5 ("ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency") Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Reviewed-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/r/20250521054309.361894-1-manikandan.m@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-23Revert "ARM: dts: Update pcie ranges for dra7"Frank Li
This reverts commit c761028ef5e27f477fe14d2b134164c584fc21ee. The commit being reverted updated the "ranges" property for the sake of readability. However, this change is no longer appropriate due to the following reasons: - On many SoCs, the PCIe parent bus translates CPU addresses to different values before passing them to the PCIe controller. - The reverted commit introduced a fake address translation, which violates the fundamental DTS principle: the device tree should reflect actual hardware behavior. Reverting this change prepares for the cleanup of the driver's cpu_addr_fixup() hook. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250411153454.3258098-1-Frank.Li@nxp.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-06-23ARM: dts: omap: am335x: Use non-deprecated rts-gpiosKrzysztof Kozlowski
The 'rts-gpio' (without trailing 's') is deprecated in favor of 'rts-gpios'. Kernel supports both variants, so switch the DTS to preferred one. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250514125158.56285-2-krzysztof.kozlowski@linaro.org Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-06-22ARM: dts: at91-sama5d27_wlsom1: Improve the Wifi compatibleFabio Estevam
The at91-sama5d27_wlsom1 SoM has a WIL3000 Wifi SDIO device populated. Improve the description of the Wifi compatible string by passing the more specific "microchip,wilc3000" string. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250617140502.1042812-1-festevam@gmail.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: gardena-smart-gateway: Fix power LEDEzra Buehler
When starting up, the GARDENA smart Gateway's power LED should be flashing green. It is unclear why this has not been done earlier. The LED frequency cannot be configured in the devicetree. Luckily, the default is 1 Hz, which is what we want. Signed-off-by: Ezra Buehler <ezra.buehler@husqvarnagroup.com> Link: https://lore.kernel.org/r/20250612074737.311346-1-ezra@easyb.ch Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sam9x7: Add clock name propertyRyan Wanner
Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal. This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree. Fixes: 41af45af8bc3 ("ARM: dts: at91: sam9x7: add device tree for SoC") Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/036518968ac657b93e315bb550b822b59ae6f17c.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add clock name propertyRyan Wanner
Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal. This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree. Fixes: 261dcfad1b59 ("ARM: dts: microchip: add sama7d65 SoC DT") Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/3878ae6d0016d46f0c91bd379146d575d5d336aa.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7g5: Adjust clock xtal phandleRyan Wanner
Adjust clock xtal phandles to match the new xtal phandle formatting. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/8a9ece664958d07b1be73b4b6676a2a2ee397a94.1750175453.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sam9x7: Add HLCD controllerDharma Balasubiramani
Add support for HLCD controller. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Link: https://lore.kernel.org/r/20250611-sam9x7-dts-v1-1-7f52fcb488ad@microchip.com [claudiu.beznea: keep reg the 1st property on port@0 to comply with dts coding style] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Enable CAN busRyan Wanner
Enable CAN bus for SAMA7D65 curiosity board. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/ab719861de53432bdf19593fa4eee40adf57aed9.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Clean up extra spaceRyan Wanner
Remove the extra space that causes formatting issues. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Link: https://lore.kernel.org/r/ac1decc35e2b4f706cf6ab9378f2c88e5295dde4.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add CAN bus supportRyan Wanner
Add support for CAN bus to the SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/f80a4206c05ed5d80a9527476963a18070ca42b6.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add PWM supportRyan Wanner
Add support for PWMs to the SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/195c69a19be1ff14736db402e0f1ee64438b4b20.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: sama7d65: Add crypto supportRyan Wanner
Add and enable SHA, AES, TDES, and TRNG for SAMA7D65 SoC. Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/fc791949c97f368f32a710e64d8db4018e45e70f.1749666053.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-22ARM: dts: microchip: use recent scl/sda gpio bindingsWolfram Sang
We have dedictaded bindings for scl/sda nowadays. Switch away from the deprecated plain 'gpios' property. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Link: https://lore.kernel.org/r/20250519112107.2980-4-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-06-19ARM: dts: renesas: r9a06g032: Add second clock input to RTCWolfram Sang
The external RTC clock is populated on the RZ/N1D module, so describe it and add a reference to the RTC node. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250604084211.28090-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe debug LEDsWolfram Sang
Enable the debug LEDs connected via the I2C GPIO extender. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250522080112.26050-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19ARM: dts: vf: vf610-zii-cfu1: rename node name *-gpio to *-gpiosFrank Li
Rename node name *-gpio to *-gpios to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dtb: sfp (sff,sff): 'los-gpio', 'tx-disable-gpio' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19ARM: dts: vf: vf-colibri-eval-v3: add power-supply for edt,et057090dhuFrank Li
Add power-supply for edt,et057090dhu to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/vf/vf610-colibri-eval-v3.dtb: panel (edt,et057090dhu): 'power-supply' is a required property Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19ARM: dts: vf: rename io-expander@20 to pinctrl@20Frank Li
Rename io-expander@20 to pinctrl@20 to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dtb: sx1503@20 (semtech,sx1503q): $nodename:0: 'sx1503@20' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$ Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19ARM: dts: vf: remove redundant layer under iomuxFrank Li
Remove redundant layer under iomux and add grp surfix for pinmux node name to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/vf/vf610-colibri-eval-v3.dtb: pinctrl@40048000 (fsl,vf610-iomuxc): Unevaluated properties are not allowed ('vf610-colibri' was unexpected) Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19ARM: dts: vf: remove redundant pinctrl-namesFrank Li
Remove redundant pinctrl-names because no pinctrl-0 node to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dtb: i2c-mux@71 (nxp,pca9548): 'pinctrl-0' is a dependency of 'pinctrl-names Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19ARM: dts: vf: remove reg property for arm pmuFrank Li
Remove reg property for arm pmu to align binding doc and move it under root node to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dtb: pmu@40089000 (arm,cortex-a5-pmu): 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19ARM: dts: vfxxx: Correctly use two tuples for timer addressKrzysztof Kozlowski
Address and size-cells are 1 and the ftm timer node takes two address spaces in "reg" property, so this should be in two <> tuples. Change has no functional impact, but original code is confusing/less readable. Fixes: 07513e1330a9 ("ARM: dts: vf610: Add Freescale FlexTimer Module timer node.") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-19ARM: dts: add ngpios for vf610 compatible gpio controllersHaibo Chen
After commit da5dd31efd24 ("gpio: vf610: Switch to gpio-mmio"), the vf610 GPIO driver no longer uses the static number 32 for gc->ngpio. This allows users to configure the number of GPIOs per port. And some gpio controllers did have less pads. So add 'ngpios' here, this can save some memory when request bitmap, and also show user more accurate information when use gpio tools. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-13ARM: dts: imx7s-warp: Improve the Wifi descriptionFabio Estevam
GPIO5_10 is connected to the BCM43455 WL_REG_ON pin and it is better descrbed via mmc-pwrseq-simple.yaml. Also improve the Wifi devicetree description by passing a compatible string that describes the BCM43455 presence as per brcm,bcm4329-fmac.yaml. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-13ARM: dts: imx7s-warp: Improve the Bluetooth descriptionFabio Estevam
GPIO5_17 is connected to the BCM43455 BT_REG_ON pin. Improve the Bluetooth devicetree description by using a more accurate description of the hardware as per brcm,bluetooth.yaml. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-06-12ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950Alexey Charkov
WonderMedia WM8850/WM8950 uses an ARM PL310 cache controller for its L2 cache, add it. The parameters have been deduced from vendor's U-boot environment variables, which the downstream code uses to initialize the controller. They set the following register values: aux = 0x3e440000 prefetch_ctrl = 0x70000007 Their initialization code also unconditionally sets the flags L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, so encode those too Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250515-wmt-dts-updates-v2-5-246937484cc8@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-06-12ARM: dts: vt8500: Fix the unit address of the VT8500 LCD controllerAlexey Charkov
Set correct unit address of d800e400 for the via,vt8500-fb node in vt8500.dtsi. Note that the reg property contained a correct address, so it must have been a copy and paste error earlier. While here, also update its node name to a generic one. Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://lore.kernel.org/r/20250515-wmt-dts-updates-v2-4-246937484cc8@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
generated by cgit (git 2.34.1) at 2025-08-02 04:56:41 +0000