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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v6.17
79b896e7da7e arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree
6516961352a1 arm64: dts: qcom: Add support for X1-based Asus Zenbook A14
The DB410c D3 camera mezzanine is converted to an overlay.
On MSM8976 SDC2 pinctrl definitions are introduced and BLSP DMA
controller is marked to be managed by another entity.
Add camera subsystem on the QCM2290 platform.
Add and enable remoteproc and related devices on QCS615.
Add and enable Video encoder/decoder on QCS8300 and SA8775P.
Also on SA8775P add CPU OPP tables for scaling DDR/L3 bandwidth based on
CPU frequency, add L3 interconnect definitions, DSI and video
encoder/decoder support.
Enable the SLPI remoteproc on SDM850-based Lenovo Yoga C630.
On SM6350, add the video clock controller, APR and some audio related
services.
Describe the camera subsystem on SM8550 and add Iris video
encoder/decoder node for SM8650.
On SM8750 introduce UFS and Soundwire support, enable these and describe
the sound hardware on MTP and QRD.
Add camera clock controller on SC8180X.
On X Elite, for the Dell XPS13, add WiFi and Bluetooth pwrseq and enable
the fingerprint sensor. For HP Omnibook X14 USB1 SS1 SBU mux and do
some misc cleanup.
Replace the thermal zones inherited from X Elite with X Plus-specific
ones.
Add missing interrupts and clean up unrelated clocks for PCIe
controllers across a variety of platforms.
* tag 'qcom-arm64-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (67 commits)
arm64: dts: qcom: sm8150: Drop unrelated clocks from PCIe hosts
arm64: dts: qcom: sc8180x: Drop unrelated clocks from PCIe hosts
arm64: dts: qcom: x1-asus-zenbook: support sound
arm64: dts: qcom: x1-asus-zenbook: fixup GPU nodes
arm64: dts: qcom: sm6115: add debug UART pins
arm64: dts: qcom: sm8650: add iris DT node
arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree
arm64: dts: qcom: msm8976: Add sdc2 GPIOs
dt-bindings: arm: qcom: Add MSM8976 BQ Aquaris X5 Plus
arm64: dts: qcom: msm8976: Make blsp_dma controlled-remotely
arm64: dts: qcom: sa8775p: Correct the interrupt for remoteproc
arm64: dts: qcom: sm8550: Add support for camss
arm64: dts: qcom: qcs615: disable the CTI device of the camera block
arm64: dts: qcom: qcs615-ride: enable remoteprocs
arm64: dts: qcom: qcs615: add ADSP and CDSP nodes
arm64: dts: qcom: qcs615: Add IMEM and PIL info region
arm64: dts: qcom: qcs615: Add mproc node for SEMP2P
arm64: dts: qcom: Add support for X1-based Asus Zenbook A14
arm64: dts: qcom: sc7180: Expand IMEM region
arm64: dts: qcom: sdm845: Expand IMEM region
...
Link: https://lore.kernel.org/r/20250716031059.76348-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Allwinner device tree changes for 6.17
This branch includes a change shared with the clk tree for adding
the missing PPU0 reset on the A523.
The PM domain DT binding immutable branch is also included, which
brings in v6.16-rc2, as well as PM domain bindings for other platforms.
Other changes include:
- RGB666 LCD pin definitions for the V3s PE pins and V3 PD pins
- node order fixes for the A523 dtsi
- UART1 pin definitions for A523
- Allwinner board DT binding cleanup
- EMAC support on A100/A133
- Enabled on the Liontron H-A133L board
- SID efuse, power controllers and GPU added for A523
- A523 GPU enabled on all existing boards
New boards:
- Xunlong OrangePi 4A with the Allwinner T527 SoC.
* tag 'sunxi-dt-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
arm64: dts: allwinner: a523: enable Mali GPU for all boards
arm64: dts: allwinner: a523: add Mali GPU node
arm64: dts: allwinner: a523: Add power controller device nodes
dt-bindings: power: Add A523 PPU and PCK600 power controllers
arm64: dts: allwinner: A523: Add SID controller node
arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
arm64: dts: allwinner: a100: Add EMAC support
arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
dt-bindings: arm: sunxi: Combine board variants into enums
dt-bindings: power: qcom,rpmpd: document the Milos RPMh Power Domains
arm64: dts: allwinner: t527: Add OrangePi 4A board
arm64: dts: allwinner: a523: Add UART1 pins
arm64: dts: allwinner: a523: Move rgmii0 pins to correct location
arm64: dts: allwinner: a523: Move mmc nodes to correct position
dt-bindings: arm: sunxi: Add Xunlong OrangePi 4A board
ARM: dts: sun8i: v3: Add RGB666 LCD PD pins definition
ARM: dts: sun8i: v3s: Add RGB666 LCD PE pins definition
dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen
dt-bindings: rockchip: pmu: Add compatible for RK3528
...
Link: https://lore.kernel.org/r/aHaQFe3Lr8Qzyb1M@wens.tw
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
TI K3 device tree updates for v6.17
Generic fixes and cleanups:
* Enable overlays for all DTB files
* Enable Schmitt Trigger by default in K3 pinctrl
SoC specific changes:
AM62D
* Add new SoC support and pinctrl entries
AM62
* Remove eMMC High Speed DDR support
* Move eMMC pinmux to top level board file
J784S4/J742S2
* Add Power on BIST (PBSIT) nodes
* Add ACSPCIE1 node
J721S2
* Add McASP support
J722S
* Add alernate audio-refclk0 node
Board changes:
Multiple boards
* Bootphase tags for Ethernet boot support
AM62D2-EVM
* Add new board support
AM62A7-SK
* Fix pinmux for main_uart1
* Add SPI NAND support
AM62P
* Fix PWM_3_DSI GPIO direction, SD pull up, I2C ups on AM62P-Verdin
* Add bootph-all property for Ethernet boot
AM62-Verdin
* Enable pull-ups on I2C buses
AM654-base-board
* Add boot phase tags for various bootmodes
AM64
* Add boot phase tag PCIe EP boot
* Fix PRU-ICSSG Ethernet ports on AM642-PhyBoard-Electra
AM69-SK
* Add idle-states for remaining SERDES instances
J722S-EVM
* Fix USB gpio-hog level for Type-C
* tag 'ti-k3-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (33 commits)
arm64: dts: ti: k3-am69-sk: Add idle-states for remaining SERDES instances
arm64: dts: ti: k3-am62a7-sk: add boot phase tags
arm64: dts: ti: k3-am654-base-board: add boot phase tags
arm64: dts: ti: k3-am65: add boot phase tags
arm64: dts: ti: k3-am69-sk: Add bootph-all property to enable Ethernet boot
arm64: dts: ti: k3-j722s-evm: Add bootph-all property to enable Ethernet boot
arm64: dts: ti: k3-am62p5-sk: Add bootph-all property to enable Ethernet boot
arm64: dts: ti: k3-am68-sk-base-board: Add bootph-all property to enable Ethernet boot
arm64: dts: ti: Add support for AM62D2-EVM
arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs
dt-bindings: arm: ti: Add AM62D2 SoC and Boards
arm64: dts: ti: Add bootph property to nodes at source for am62a
arm64: dts: ti: k3-am62p-verdin: Adjust temperature trip points
arm64: dts: ti: k3-am62p-j722s: Enable freq throttling on thermal alert
arm64: dts: ti: k3-j784s4-j742s2-main-common: Add PBIST_14 node
dt-bindings: soc: ti: bist: Add BIST for K3 devices
arm64: dts: ti: k3-am62-main: Remove eMMC High Speed DDR support
arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file
arm64: dts: ti: k3-am62a7-sk: fix pinmux for main_uart1
arm64: dts: ti: Enable overlays for all DTB files
...
Link: https://lore.kernel.org/r/a0401460-8c67-4c29-a6cf-fa4bdf33bc7d@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm64 device tree changes for 6.17:
- New board support: GOcontroll Moduline based devices, phyCORE-i.MX 95
Plus FPSC SoM and base boards, i.MX93 phycore overlays
- A few i.MX8M changes from Adam Ford to add DMA configuration for
UART2, set up VPU clocks for nominal and overdrive mode, improve
HS400 USDHC clock speed
- Several sets of changes from Alexander Stein to add EASRC support for
tqma8mnql and tqma8mpql board, add missing DMA entries for I2C & LPUART
on ls1043a and ls1046a, enable SFP interface for tqmls1043a and
tqmls1046a, etc.
- A series from Clark Wang to improve Ethernet support for i.MX93,
removing eee-broken-1000t for eqos node, reducing the driving strength
of net RXC/TXC, etc.
- A few i.MX95 and i.MX8Q changes from Frank Li to add missing devices
for EVK board and enable camera support
- A couple of changes from Laurentiu Mihalcea to support WM8962 audio
codec for imx8qxp-mek and imx8qm-mek board
- A number of changes from Shengjiu Wang to improve various audio
support for imx943-evk and imx8mp-evk
- A series from Tim Harvey to increase HS400 USDHC clock speed for
Gateworks i.MX8M Venice devices
- Many other random improvements and cleanups on various boards
* tag 'imx-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (85 commits)
arm64: dts: imx8q: add camera ov5640 support for imx8qm-mek and imx8qxp-mek
arm64: dts: freescale: imx8mp-toradex-smarc: remove gpio hog
arm64: dts: freescale: imx8mp-toradex-smarc: fix lvds dsi mux gpio
arm64: dts: imx8mm-venice-gw7904: Increase HS400 USDHC clock speed
arm64: dts: imx8mm-venice-gw7903: Increase HS400 USDHC clock speed
arm64: dts: imx8mn-venice-gw7902: Increase HS400 USDHC clock speed
arm64: dts: imx8mm-venice-gw7902: Increase HS400 USDHC clock speed
arm64: dts: imx8mm-venice-gw7901: Increase HS400 USDHC clock speed
arm64: dts: imx8mp-venice-gw702x: Increase HS400 USDHC clock speed
arm64: dts: imx8mm-venice-gw700x: Increase HS400 USDHC clock speed
arm64: dts: lx2160a-qds: add the two on-board RGMII PHYs
arm64: dts: add imx95-libra-rdk-fpsc board
arm64: dts: imx8q: add linux,cma node for imx8qm-mek and imx8qxp-mek
arm64: dts: imx8: add capture controller for i.MX8's img subsystem
arm64: dts: imx95: add jpeg encode and decode nodes
arm64: dts: imx93-phyboard-nash: Add PEB-WLBT-07 overlay
arm64: dts: imx93-phyboard-segin: Add PEB-WLBT-05 overlay
arm64: dts: imx93-phyboard-segin: Add PEB-EVAL-01 overlay
arm64: dts: imx93-phycore-som: Add RPMsg overlay
arm64: dts: freescale: tqmls10xx: Add vdd-supply for spi-nor flash
...
Link: https://lore.kernel.org/r/20250713055441.221235-4-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v6.17
- Fix dt_binding_check warnings
- agilex - f2s-free-clk
- stratix10 - rstmgr
- swvp - remove phy-addr, cpu1-start-addr and altr,modrst-offset
* tag 'socfpga_dts_updates_for_v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: altera: socfpga_stratix10: update internal oscillators
arm64: dts: socfpga: swvp: remove phy-addr in the GMAC node
arm64: dts: socfpga: swvp: remove cpu1-start-addr
arm64: dts: socfpga: swvp: remove altr,modrst-offset
arm64: dts: socfpga: stratix10: fix dtbs_check for rstmgr
arm64: dts: socfpga: agilex: fix dtbs_check warning for f2s-free-clk
Link: https://lore.kernel.org/r/20250712123248.16981-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Changes for v6.17-rc1
Add support for the Tegra264 SoC and the corresponding engineering
reference hardware (P3971-0089+P3834-0008).
* tag 'tegra-for-6.17-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Add p3971-0089+p3834-0008 support
arm64: tegra: Add memory controller on Tegra264
arm64: tegra: Add Tegra264 support
Link: https://lore.kernel.org/r/20250711220943.2389322-7-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/arm
TI K3 defconfig updates for v6.17
Cleanup select clauses for ARCH_K3 allow more modular builds
* tag 'ti-k3-config-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
arm64: Kconfig.platforms: remove useless select for ARCH_K3
Link: https://lore.kernel.org/r/5488ccd5-c999-4b72-bfc0-ba94bb9a360d@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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`cpu_switch_to()` and `call_on_irq_stack()` manipulate SP to change
to different stacks along with the Shadow Call Stack if it is enabled.
Those two stack changes cannot be done atomically and both functions
can be interrupted by SErrors or Debug Exceptions which, though unlikely,
is very much broken : if interrupted, we can end up with mismatched stacks
and Shadow Call Stack leading to clobbered stacks.
In `cpu_switch_to()`, it can happen when SP_EL0 points to the new task,
but x18 stills points to the old task's SCS. When the interrupt handler
tries to save the task's SCS pointer, it will save the old task
SCS pointer (x18) into the new task struct (pointed to by SP_EL0),
clobbering it.
In `call_on_irq_stack()`, it can happen when switching from the task stack
to the IRQ stack and when switching back. In both cases, we can be
interrupted when the SCS pointer points to the IRQ SCS, but SP points to
the task stack. The nested interrupt handler pushes its return addresses
on the IRQ SCS. It then detects that SP points to the task stack,
calls `call_on_irq_stack()` and clobbers the task SCS pointer with
the IRQ SCS pointer, which it will also use !
This leads to tasks returning to addresses on the wrong SCS,
or even on the IRQ SCS, triggering kernel panics via CONFIG_VMAP_STACK
or FPAC if enabled.
This is possible on a default config, but unlikely.
However, when enabling CONFIG_ARM64_PSEUDO_NMI, DAIF is unmasked and
instead the GIC is responsible for filtering what interrupts the CPU
should receive based on priority.
Given the goal of emulating NMIs, pseudo-NMIs can be received by the CPU
even in `cpu_switch_to()` and `call_on_irq_stack()`, possibly *very*
frequently depending on the system configuration and workload, leading
to unpredictable kernel panics.
Completely mask DAIF in `cpu_switch_to()` and restore it when returning.
Do the same in `call_on_irq_stack()`, but restore and mask around
the branch.
Mask DAIF even if CONFIG_SHADOW_CALL_STACK is not enabled for consistency
of behaviour between all configurations.
Introduce and use an assembly macro for saving and masking DAIF,
as the existing one saves but only masks IF.
Cc: <stable@vger.kernel.org>
Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Reported-by: Cristian Prundeanu <cpru@amazon.com>
Fixes: 59b37fe52f49 ("arm64: Stash shadow stack pointer in the task struct on interrupt")
Tested-by: Cristian Prundeanu <cpru@amazon.com>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20250718142814.133329-1-ada.coupriediaz@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
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Recent patches selecting HAVE_RELIABLE_STACKTRACE and HAVE_LIVEPATCH
added them to the end of the ARM64 Kconfig select list. Move them around
to keep this list nearly alphabetically ordered.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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POR_EL0 is set to its most permissive value before setting up the
signal frame, to ensure that uaccess succeeds regardless of the
signal stack's pkey.
We are now tolerant to spurious POE faults. This means that we do
not strictly need to issue an ISB after updating POR_EL0, even when
followed by uaccess. The question is whether a fault is likely to
happen or not if the ISB is omitted; in this case the answer seems
to be no. If the regular stack is used, then it should already be
accessible. If the alternate signal stack is used, then a special
(inaccessible) pkey may be used - the assumption is that this
situation is very uncommon.
Remove the ISB to speed up the regular path - this should not have
any functional impact regardless of the scenario.
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
Link: https://lore.kernel.org/r/20250619160042.2499290-3-kevin.brodsky@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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In preparation for Clang stack depth tracking for KSTACK_ERASE,
split the stackleak-specific cflags out of GCC_PLUGINS_CFLAGS into
KSTACK_ERASE_CFLAGS.
Link: https://lore.kernel.org/r/20250717232519.2984886-3-kees@kernel.org
Signed-off-by: Kees Cook <kees@kernel.org>
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In preparation for adding Clang sanitizer coverage stack depth tracking
that can support stack depth callbacks:
- Add the new top-level CONFIG_KSTACK_ERASE option which will be
implemented either with the stackleak GCC plugin, or with the Clang
stack depth callback support.
- Rename CONFIG_GCC_PLUGIN_STACKLEAK as needed to CONFIG_KSTACK_ERASE,
but keep it for anything specific to the GCC plugin itself.
- Rename all exposed "STACKLEAK" names and files to "KSTACK_ERASE" (named
for what it does rather than what it protects against), but leave as
many of the internals alone as possible to avoid even more churn.
While here, also split "prev_lowest_stack" into CONFIG_KSTACK_ERASE_METRICS,
since that's the only place it is referenced from.
Suggested-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20250717232519.2984886-1-kees@kernel.org
Signed-off-by: Kees Cook <kees@kernel.org>
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We currently always expose FEAT_RAS when available on the host.
As we are about to make this feature selectable from userspace,
check for it being present before emulating register accesses
as RAZ/WI, and inject an UNDEF otherwise.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250721101955.535159-4-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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Most HCR_EL2 bits are not supposed to affect EL2 at all, but only
the guest. However, we gladly merge these bits with the host's
HCR_EL2 configuration, irrespective of entering L1 or L2.
This leads to some funky behaviour, such as L1 trying to inject
a virtual SError for L2, and getting a taste of its own medecine.
Not quite what the architecture anticipated.
In the end, the only bits that matter are those we have defined as
invariants, either because we've made them RESx (E2H, HCD...), or
that we actively refuse to merge because the mess with KVM's own
logic.
Use the sanitisation infrastructure to get the RES1 bits, and let
things rip in a safer way.
Fixes: 04ab519bb86df ("KVM: arm64: nv: Configure HCR_EL2 for FEAT_NV2")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20250721101955.535159-3-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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Mark Brown reports that since we commit to making exceptions
visible without the vcpu being loaded, the external abort selftest
fails.
Upon investigation, it turns out that the code that makes registers
affected by an exception visible to the guest is completely broken
on VHE, as we don't check whether the system registers are loaded
on the CPU at this point. We managed to get away with this so far,
but that's obviously as bad as it gets,
Add the required checksm and document the absolute need to check
for the SYSREGS_ON_CPU flag before calling into any of the
__vcpu_write_sys_reg_to_cpu()__vcpu_read_sys_reg_from_cpu() helpers.
Reported-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/18535df8-e647-4643-af9a-bb780af03a70@sirena.org.uk
Link: https://lore.kernel.org/r/20250720102229.179114-1-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/defconfig
Samsung SoC defconfig changes for v6.17
1. Multiple SoCs (including Samsung, Apple): switch sound to module from
a built-in, because it is not necessary for booting. Also drop
redundant sound codec options.
2. Enable PMIC drivers for Google GS101 Pixel 6 phones: MAX77759 and
Samsung PMIC over ACPM protocol.
* tag 'samsung-defconfig-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: defconfig: enable Samsung PMIC over ACPM
arm64: defconfig: enable Maxim max77759 driver
arm64: defconfig: Drop unneeded unselectable sound drivers
arm64: defconfig: Switch SOUND to module
Link: https://lore.kernel.org/r/20250709191523.171359-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add device tree entries for GPUs in M-series SoCs
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Sven Peter <sven@kernel.org>
Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
Link: https://lore.kernel.org/r/20250710-sgx-dt-v3-2-299bb3a65109@gmail.com
Signed-off-by: Sven Peter <sven@kernel.org>
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Apple T2 MacBookPro15,2 (j132) has a touchbar so include the framebuffer
node.
Cc: stable@vger.kernel.org
Fixes: 4efbcb623e9bc ("arm64: dts: apple: Add T2 devices")
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/stable/20250620-j132-fb-v1-1-bc6937baf0b9%40gmail.com
Link: https://lore.kernel.org/r/20250620-j132-fb-v2-1-65f100182085@gmail.com
Signed-off-by: Sven Peter <sven@kernel.org>
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Now that the dt-binding has been extended to allow indicating the bit
position the following warning about a duplicate unit address with W=1
can be fixed:
arch/arm64/boot/dts/apple/t8103.dtsi:764.46-767.8: Warning (unique_unit_address_if_enabled): /soc/spmi@23d0d9300/pmic@f/nvmem-layout/boot-error-count@9f02: duplicate unit-address (also used in node /soc/spmi@23d0d9300/pmic@f/nvmem-layout/panic-count@9f02)
Fixes: d8bf82081c9e ("arm64: dts: apple: Add PMIC NVMEM")
Link: https://lore.kernel.org/r/20250610-nvmem-bit-pattern-v1-2-55ed5c1b369c@kernel.org
Signed-off-by: Sven Peter <sven@kernel.org>
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Patches from Peter Chen <peter.chen@cixtech.com>:
Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC.
Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief
introduction for SoC and related boards at:
https://radxa.com/products/orion/o6#overview
Currently, to run upstream kernel at Orion O6 board, you need to
use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs.
https://docs.radxa.com/en/orion/o6/bios/install-bios
In this series, we add initial SoC and board support for Kernel building.
Since mailbox is used for SCMI clock communication, mailbox driver is added
in this series for the minimum SoC support.
Patch 1-2: add dt-binding doc for CIX and its sky1 SoC
Patch 3: add Arm64 build support
Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol.
Patch 6: add Arm64 defconfig support
Patch 7-8: add initial dts support for SoC and Orion O6 board
Patch 9: add MAINTAINERS entry
* newsoc/cix-p1:
MAINTAINERS: Add CIX SoC maintainer entry
arm64: dts: cix: Add sky1 base dts initial support
dt-bindings: clock: cix: Add CIX sky1 scmi clock id
arm64: defconfig: Enable CIX SoC
mailbox: add CIX mailbox driver
dt-bindings: mailbox: add cix,sky1-mbox
arm64: Kconfig: add ARCH_CIX for cix silicons
dt-bindings: arm: add CIX P1 (SKY1) SoC
dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech,
and Orion O6 is the motherboard launched by Radxa. See below for
detail:
https://docs.radxa.com/en/orion/o6/getting-started/introduction
In this commit, it only adds limited components for running initramfs
at Orion O6.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Enric Balletbo i Serra <eballetb@redhat.com>
Tested-by: Kajetan Puchalski <kajetan.puchalski@arm.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com>
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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- Enable CIX SoC support at ARM64 defconfig
- Enable CIX mailbox
At CIX SoC platforms, the clock handling uses Arm SCMI protocol,
the physical clock access is at sub processor, so it needs to enable
mailbox by default.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add ARCH_CIX for CIX SoC series support.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM64 DeviceTree updates for v6.17
This adds new machines and improves support for already supported
MediaTek SoCs.
In particular:
- New machine: MT8186 Steelix Squirtle Chromebook
- Steelix-Voltorb's two dts are merged in one
...and improvements for already supported SoCs and machines:
- Added reserved memory for AFE DMA for MT8173/83/86/92,
aligning audio related memory allocation between all of
the Chromebook SoCs
- Added second source components for Steelix, and marked the
multiple trackpads for Asurada as such
- MediaTek Genio 1200: Enabled support for the Audio DSP and sound
- MediaTek Genio 510/700/1200: Added support for the PMIC Keys
- MediaTek MT7988: Added Cache Coherent Interconnect for CPU DVFS
- MT7988A-BananaPi-R4: Enabled CCI, added GPIO LEDs
- Airoha EN7581: Added ethernet nodes to Evaluation Board
* tag 'mtk-dts64-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
arm64: dts: mediatek: mt8395-genio-1200-evk: Add MT6359 PMIC key support
arm64: dts: mediatek: mt8390-genio-common: Add Home MT6359 PMIC key support
arm64: dts: mediatek: mt7988a-bpi-r4: add gpio leds
arm64: dts: mediatek: mt7988a-bpi-r4: drop unused pins
arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
arm64: dts: mediatek: mt7988: add cci node
dt-bindings: interconnect: add mt7988-cci compatible
arm64: dts: airoha: en7581: Add ethernet nodes to EN7581 SoC evaluation board
arm64: dts: mediatek: mt8192-asurada-spherion: Mark trackpads as fail-needs-probe
arm64: dts: mediatek: mt8186: Add Squirtle Chromebooks
arm64: dts: mediatek: mt8186: Merge Voltorb device trees
arm64: dts: mediatek: mt8186-steelix: Mark second source components for probing
dt-bindings: arm: mediatek: Add MT8186 Squirtle Chromebooks
dt-bindings: arm: mediatek: Merge MT8186 Voltorb entries
arm64: dts: mediatek: mt8395-genio-1200-evk: Enable Audio DSP and sound card
arm64: dts: mediatek: mt8192-asurada: Reserve memory for audio frontend
arm64: dts: mediatek: mt8186-corsola: Reserve memory for audio frontend
arm64: dts: mediatek: mt8183-kukui: Reserve memory for audio frontend
arm64: dts: mediatek: mt8173: Reserve memory for audio frontend
Link: https://lore.kernel.org/r/20250711083656.33538-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.17, round 1
Highlights:
----------
- MPU:
- STM32MP13:
-Add Ethernet MAC adress efuse support.
- STMP32MP15:
- Add stm32mp157f-DK2 board support. This board embedds the same
conectivity devices, DDR ... than stm32mp157c-dk2.
However there are two differences: STM32MP157F SoC which allows
overdrive OPP and the SCMI support for system features like
clocks and regulators.
- STM32MP25:
- Fix tick timer for low power use cases.
- Add timer support.
* tag 'stm32-dt-for-v6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
arm64: dts: st: remove empty line in stm32mp251.dtsi
arm64: dts: st: fix timer used for ticks
arm64: defconfig: Enable STM32 Octo Memory Manager and OcstoSPI driver
ARM: dts: stm32: add stm32mp157f-dk2 board support
dt-bindings: arm: stm32: add STM32MP157F-DK2 board compatible
ARM: dts: stm32: optee async notif interrupt for MP15 scmi variants
ARM: dts: stm32: use internal regulators bindings for MP15 scmi variants
dt-bindings: regulator: Add STM32MP15 SCMI regulator identifiers
ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkx
ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCs
ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkx
arm64: defconfig: enable STM32 timers drivers
arm64: dts: st: add timer nodes on stm32mp257f-ev1
arm64: dts: st: add timer pins for stm32mp257f-ev1
arm64: dts: st: add timer nodes on stm32mp251
ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addresses
Link: https://lore.kernel.org/r/b3e3363b-1ea5-457c-b244-2cbe26f7d6e4@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: ROC-RK3588S-PC, Luckfox Omni3576, Radxa Rock 5T,
Sakura Pi RK3308B - all of them have the used soc in their name.
New overlays: RockPro64 screen, optional Sige5 Wifi/BT module,
ethernet-switch addon for Jaguar.
Added peripherals on rk3528 (spi, power-domain controller, gpu)
and sdio controller on rk3576.
DSI display support for the Gameforce-ACE handheld, a fix for the
cover-detection (closed/open) on the PineNote, camera support for
the Haikou Video Demo overlay on PX30 Ringneck as well as a number
of other newly enabled peripherals on a number of boards.
* tag 'v6.17-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (40 commits)
arm64: dts: rockchip: Enable eMMC HS200 mode on Radxa E20C
arm64: dts: rockchip: Add bluetooth support to ArmSoM Sige7
arm64: dts: rockchip: enable PCIe on ROCK 4D
arm64: dts: rockchip: Enable HDMI receiver on CM3588
arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576
arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576
arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PC
dt-bindings: arm: rockchip: Add Firefly ROC-RK3588S-PC
arm64: dts: rockchip: Enable GPU on Radxa E20C
arm64: dts: rockchip: Add GPU node for RK3528
arm64: dts: rockchip: support camera module on Haikou Video Demo on PX30 Ringneck
arm64: dts: rockchip: add label to first port of ISP on px30
arm64: dts: rockchip: fix endpoint dtc warning for PX30 ISP
arm64: dts: rockchip: Add power controller for RK3528
arm64: dts: rockchip: enable USB on Sige5
arm64: dts: rockchip: add overlay for the WiFi/BT module on Sige5 v1.2
arm64: dts: rockchip: add version-independent WiFi/BT nodes on Sige5
arm64: dts: rockchip: add SDIO controller on RK3576
arm64: dts: rockchip: Enable gpu on rk3576-evb1-v10
arm64: dts: rockchip: Update the PinePhone Pro panel description
...
Link: https://lore.kernel.org/r/15465458.uLZWGnKmhe@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The Arm GIC "ppi-partitions" node is only relevant to GICv3 and makes no
sense for GICv2 implementations which the GIC-400 is. PPIs in GICv2 have
no CPU affinity.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250609203721.2852879-1-robh@kernel.org
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/r/20250710-nuvoton-arm64-dt-v1-1-ec7db96ea507@codeconstruct.com.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.17 (take two)
- Add support for the Renesas Gray Hawk Single board with R-Car
V4M-7 (R8A779H2),
- Add eMMC and microSD expansion board support for the RZ/V2H and
RZ/V2N EVK development boards,
- Add GPIO keys and Ethernet support for the RZ/G3E SoM and SMARC
Carrier-II EVK development board,
- Add QSPI FLASH support for the RZ/V2H and RZ/V2N SoCs and their EVK
development boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH
arm64: dts: renesas: r9a09g057: Add XSPI node
arm64: dts: renesas: r9a09g056: Add XSPI node
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Fix pinctrl node name for GBETH1
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Fix pinctrl node name for GBETH1
arm64: dts: renesas: r8a779g3-sparrow-hawk-fan-pwm: Add missing install target
arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs
arm64: dts: renesas: r8a779h2: Add Gray Hawk Single support
arm64: dts: renesas: Add Renesas R8A779H2 SoC support
arm64: dts: renesas: Factor out Gray Hawk Single board support
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
Link: https://lore.kernel.org/r/cover.1752090401.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.17
1. New SoC - Exynos2200 SoC - with basic nodes, pin controllers,
clock controllers and initial USB support. Add board using it:
Samsung Galaxy S22+ (SM-S906B), called G0S.
2. ExynosAutov920: Add CMU_HSI2 clock controller, remaining SPI nodes
3. Google GS101:
- Prepare to switching to architected timer, instead of Exynos MCT as
the primary one.
- Add secondary Maxim MAX77759 PMIC to Pixel boards, managing USB Type-C and
charger.
- Add incomplete description of the primary Samsung S2MPG10 PMIC.
Several bits, like regulators, are still missing, though.
- Add also secondary reboot-mode, via MAX77759 NVMEM.
- Switch the primary (SoC) reboot handler to Google specific
google,gs101-reboot which gives additional GS101 features (cold and
warm reboots).
This change will affect other users of this DTS, but to our
knowledge there is only Android, from which this change originates.
4. Exynos7870:
- Fix speed problems in USB gadget mode.
- Correct memory map to avoid crashes due to secure world.
* tag 'samsung-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos7870-j6lte: reduce memory ranges to base amount
arm64: dts: exynos7870-on7xelte: reduce memory ranges to base amount
arm64: dts: exynos7870: add quirk to disable USB2 LPM in gadget mode
arm64: dts: exynos: gs101: switch to gs101 specific reboot
arm64: dts: exynos: gs101-pixel-common: add main PMIC node
arm64: dts: exynos: gs101: ufs: add dma-coherent property
arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode
arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode
arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC
arm64: dts: exynos5433: Align i2c-gpio node names with dtschema
arm64: dts: exynos: gs101: Add 'local-timer-stop' to cpuidle nodes
arm64: dts: exynosautov920: Add DT node for all SPI ports
arm64: dts: exynosautov920: add CMU_HSI2 clock DT nodes
MAINTAINERS: add entry for Samsung Exynos2200 SoC
arm64: dts: exynos: add initial support for Samsung Galaxy S22+
arm64: dts: exynos: add initial support for exynos2200 SoC
dt-bindings: arm: samsung: document g0s board binding
Link: https://lore.kernel.org/r/20250709191523.171359-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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We need the USB/Thunderbolt fixes in here for other patches to be on top
of.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Patch series "kdump: crashkernel reservation from CMA", v5.
This series implements a way to reserve additional crash kernel memory
using CMA.
Currently, all the memory for the crash kernel is not usable by the 1st
(production) kernel. It is also unmapped so that it can't be corrupted by
the fault that will eventually trigger the crash. This makes sense for
the memory actually used by the kexec-loaded crash kernel image and initrd
and the data prepared during the load (vmcoreinfo, ...). However, the
reserved space needs to be much larger than that to provide enough
run-time memory for the crash kernel and the kdump userspace. Estimating
the amount of memory to reserve is difficult. Being too careful makes
kdump likely to end in OOM, being too generous takes even more memory from
the production system. Also, the reservation only allows reserving a
single contiguous block (or two with the "low" suffix). I've seen systems
where this fails because the physical memory is fragmented.
By reserving additional crashkernel memory from CMA, the main crashkernel
reservation can be just large enough to fit the kernel and initrd image,
minimizing the memory taken away from the production system. Most of the
run-time memory for the crash kernel will be memory previously available
to userspace in the production system. As this memory is no longer
wasted, the reservation can be done with a generous margin, making kdump
more reliable. Kernel memory that we need to preserve for dumping is
normally not allocated from CMA, unless it is explicitly allocated as
movable. Currently this is only the case for memory ballooning and zswap.
Such movable memory will be missing from the vmcore. User data is
typically not dumped by makedumpfile. When dumping of user data is
intended this new CMA reservation cannot be used.
There are five patches in this series:
The first adds a new ",cma" suffix to the recenly introduced generic
crashkernel parsing code. parse_crashkernel() takes one more argument to
store the cma reservation size.
The second patch implements reserve_crashkernel_cma() which performs the
reservation. If the requested size is not available in a single range,
multiple smaller ranges will be reserved.
The third patch updates Documentation/, explicitly mentioning the
potential DMA corruption of the CMA-reserved memory.
The fourth patch adds a short delay before booting the kdump kernel,
allowing pending DMA transfers to finish.
The fifth patch enables the functionality for x86 as a proof of
concept. There are just three things every arch needs to do:
- call reserve_crashkernel_cma()
- include the CMA-reserved ranges in the physical memory map
- exclude the CMA-reserved ranges from the memory available
through /proc/vmcore by excluding them from the vmcoreinfo
PT_LOAD ranges.
Adding other architectures is easy and I can do that as soon as this
series is merged.
With this series applied, specifying
crashkernel=100M craskhernel=1G,cma
on the command line will make a standard crashkernel reservation
of 100M, where kexec will load the kernel and initrd.
An additional 1G will be reserved from CMA, still usable by the production
system. The crash kernel will have 1.1G memory available. The 100M can
be reliably predicted based on the size of the kernel and initrd.
The new cma suffix is completely optional. When no
crashkernel=size,cma is specified, everything works as before.
This patch (of 5):
Add a new cma_size parameter to parse_crashkernel(). When not NULL, call
__parse_crashkernel to parse the CMA reservation size from
"crashkernel=size,cma" and store it in cma_size.
Set cma_size to NULL in all calls to parse_crashkernel().
Link: https://lkml.kernel.org/r/aEqnxxfLZMllMC8I@dwarf.suse.cz
Link: https://lkml.kernel.org/r/aEqoQckgoTQNULnh@dwarf.suse.cz
Signed-off-by: Jiri Bohac <jbohac@suse.cz>
Cc: Baoquan He <bhe@redhat.com>
Cc: Dave Young <dyoung@redhat.com>
Cc: Donald Dutile <ddutile@redhat.com>
Cc: Michal Hocko <mhocko@suse.cz>
Cc: Philipp Rudo <prudo@redhat.com>
Cc: Pingfan Liu <piliu@redhat.com>
Cc: Tao Liu <ltao@redhat.com>
Cc: Vivek Goyal <vgoyal@redhat.com>
Cc: David Hildenbrand <david@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
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Pull kvm fixes from Paolo Bonzini:
"ARM:
- Fix use of u64_replace_bits() in adjusting the guest's view of
MDCR_EL2.HPMN
RISC-V:
- Fix an issue related to timer cleanup when exiting to user-space
- Fix a race-condition in updating interrupts enabled for the guest
when IMSIC is hardware-virtualized
x86:
- Reject KVM_SET_TSC_KHZ for guests with a protected TSC (currently
only TDX)
- Ensure struct kvm_tdx_capabilities fields that are not explicitly
set by KVM are zeroed
Documentation:
- Explain how KVM contributions should be made testable
- Fix a formatting goof in the TDX documentation"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: TDX: Don't report base TDVMCALLs
KVM: VMX: Ensure unused kvm_tdx_capabilities fields are zeroed out
KVM: Documentation: document how KVM is tested
KVM: Documentation: minimal updates to review-checklist.rst
KVM: x86: Reject KVM_SET_TSC_KHZ vCPU ioctl for TSC protected guest
RISC-V: KVM: Move HGEI[E|P] CSR access to IMSIC virtualization
RISC-V: KVM: Disable vstimecmp before exiting to user-space
Documentation: KVM: Fix unexpected unindent warning
KVM: arm64: Fix enforcement of upper bound on MDCR_EL2.HPMN
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Cross-merge BPF and other fixes after downstream PR.
No conflicts.
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
Allwinner fixes for 6.16
Only one fix:
Correct the name of the A523's EMAC0 to GMAC0, as seen in the SoC's
datasheets. The matching DT binding change is in the net tree.
* tag 'sunxi-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: a523: Rename emac0 to gmac0
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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The 'addr' need not be incremented in the loop because that is not going to
be used subsequently.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Ryan Roberts <ryan.roberts@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Dev Jain <dev.jain@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20250716035432.293682-1-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
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Set TAINT_MACHINE_CHECK when SError or Synchronous External Abort (SEA)
interrupts trigger a panic to flag potential hardware faults. This
tainting mechanism aids in debugging and enables correlation of
hardware-related crashes in large-scale deployments.
This change aligns with similar patches[1] that mark machine check
events when the system crashes due to hardware errors.
Link: https://lore.kernel.org/all/20250702-add_tain-v1-1-9187b10914b9@debian.org/ [1]
Signed-off-by: Breno Leitao <leitao@debian.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20250716-vmcore_hw_error-v2-1-f187f7d62aba@debian.org
Signed-off-by: Will Deacon <will@kernel.org>
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Both the R5S and R5C have a MASKROM button connected via saradc.
For both the R5S as the R5C it's described on page 9 of their
respective schematic, identified as 'Recovery'.
Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
Link: https://lore.kernel.org/r/20250716083355.327451-1-didi.debian@cknow.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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While introducing support for 9+ arguments for tracing programs on
ARM64, commit 9014cf56f13d ("bpf, arm64: Support up to 12 function
arguments") has also introduced a constraint preventing BPF trampolines
from being generated if the target function consumes a struct argument
passed on stack, because of uncertainties around the exact struct
location: if the struct has been marked as packed or with a custom
alignment, this info is not reflected in BTF data, and so generated
tracing trampolines could read the target function arguments at wrong
offsets.
This issue is not specific to ARM64: there has been an attempt (see [1])
to bring the same constraint to other architectures JIT compilers. But
discussions following this attempt led to the move of this constraint
out of the kernel (see [2]): instead of preventing the kernel from
generating trampolines for those functions consuming structs on stack,
it is simpler to just make sure that those functions with uncertain
struct arguments location are not encoded in BTF information, and so
that one can not even attempt to attach a tracing program to such
function. The task is then deferred to pahole (see [3]).
Now that the constraint is handled by pahole, remove it from the arm64
JIT compiler to keep it simple.
[1] https://lore.kernel.org/bpf/20250613-deny_trampoline_structs_on_stack-v1-0-5be9211768c3@bootlin.com/
[2] https://lore.kernel.org/bpf/CAADnVQ+sj9XhscN9PdmTzjVa7Eif21noAUH3y1K6x5bWcL-5pg@mail.gmail.com/
[3] https://lore.kernel.org/bpf/20250707-btf_skip_structs_on_stack-v3-0-29569e086c12@bootlin.com/
Signed-off-by: Alexis Lothoré (eBPF Foundation) <alexis.lothore@bootlin.com>
Link: https://lore.kernel.org/r/20250709-arm64_relax_jit_comp-v1-1-3850fe189092@bootlin.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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Filesystems like resctrl use the cache-id exposed via sysfs to identify
groups of CPUs. The value is also used for PCIe cache steering tags. On
DT platforms cache-id is not something that is described in the
device-tree, but instead generated from the smallest MPIDR of the CPUs
associated with that cache. The cache-id exposed to user-space has
historically been 32 bits.
MPIDR values may be larger than 32 bits.
MPIDR only has 32 bits worth of affinity data, but the aff3 field lives
above 32bits. The corresponding lower bits are masked out by
MPIDR_HWID_BITMASK and contain an SMT flag and Uni-Processor flag.
Swizzzle the aff3 field into the bottom 32 bits and using that.
In case more affinity fields are added in the future, the upper RES0
area should be checked. Returning a value greater than 32 bits from
this helper will cause the caller to give up on allocating cache-ids.
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Link: https://lore.kernel.org/r/20250711182743.30141-4-james.morse@arm.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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The current definition of FEAT_PMUv3p9 doesn't check for the lack
of an IMPDEF PMU, which is encoded as 0b1111, but considered unsigned.
Use the recently introduced helper to address the issue (which is
harmless, as KVM never advertises an IMPDEF PMU).
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714115503.3334242-6-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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As for other registers, convert the determination of the RES0 bits
affecting MDCR_EL2 to be driven by a table extracted from the 2025-06
JSON drop
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714115503.3334242-5-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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As for other registers, convert the determination of the RES0 bits
affecting SCTLR_EL1 to be driven by a table extracted from the 2025-06
JSON drop
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714115503.3334242-4-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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As for other registers, convert the determination of the RES0 bits
affecting TCR2_EL2 to be driven by a table extracted from the 2025-06
JSON drop.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714115503.3334242-3-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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FEAT_THE and FEAT_ASID2 add new controls to the TCR2_ELx registers.
Add them to the register descriptions.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714115503.3334242-2-maz@kernel.org
[ fix whitespace ]
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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While a guest is able to use the FEAT_FGT2 registers, we're missing
them being exposed to userspace. Add them to the (very long) list.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714122634.3334816-9-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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We shouldn't expose the FEAT_FGT registers unconditionally. Make
them dependent on FEAT_FGT being actually advertised to the guest.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714122634.3334816-8-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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Expose all the GICv3 EL2 registers through the usual GICv3 save/restore
interface, making it possible for a VMM to access the EL2 state.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714122634.3334816-7-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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The GICv3 save/restore code never needed any visibility attribute,
but that's about to change. Make vgic_v3_has_cpu_sysregs_attr()
check the visibility in case a register is hidden.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714122634.3334816-6-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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Move the computation of the ICH_VTR_EL2 value to a common location,
so that it can be reused by the save/restore code.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714122634.3334816-5-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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Move the bag of bits defining the value of ICC_SRE_EL2 to a common
spot so that it can be reused by the save/restore code.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250714122634.3334816-4-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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