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path: root/drivers/gpu/drm/i915
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2025-05-16drm/i915/dmc: Extract is_event_handler()Ville Syrjälä
Extract the helper to determine if the mmio reg+data are the event handler register (DMC_EVT_CTL) for a specific event. We'll have another use for this for runtime event handler enable/disable. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250512103358.15724-7-ville.syrjala@linux.intel.com Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
2025-05-16drm/i915/dmc: Relocate is_dmc_evt_{ctl,htp}_reg()Ville Syrjälä
Move is_dmc_evt_ctl_reg() to a slightly earlier position in the file so that we can reuse it in the pkgc workaround code. Also move is_dmc_evt_htp_reg() just to keep the two together. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250512103358.15724-6-ville.syrjala@linux.intel.com Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
2025-05-16drm/i915/dmc: Extract dmc_evt_ctl_disable()Ville Syrjälä
We have two copies of the code to generate the "disable this event" value for the DMC_EVT_CTL registers. Extract to a helper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250512103358.15724-5-ville.syrjala@linux.intel.com Reviewed-by: Luca Coelho <luciano.coeho@intel.com>
2025-05-16drm/i915/dmc: Define all DMC event IDsVille Syrjälä
Define all the DMC event IDs to make life less misrable when having to deal with these. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250512103358.15724-4-ville.syrjala@linux.intel.com Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
2025-05-16drm/i915/dmc: Hook up PIPEDMC interruptsVille Syrjälä
Hook up PIPEDMC interrupts. We'll need these for: - flip queue signalling - GTT/ATS faults on LNL+ - unclaimed register access errors (supposedly that is what the error interrupt indicated according to Windows code). On LNL+ we get a new level of interrupts registers PIPEDMC_INTERRUPT*. On earlier platforms we only have the INT_VECTOR field in the PIPEDMC_STATUS registers, whose values are defined by the firmware. For now we'll enable the interrupts on LNL+ only. For earlier platforms it's not clear that there is any use for these interrupts, and some ADL machines have exhibited spurious DE_PIPE interrupts with the PIPEDMC interrupts unmasked/enabled. We can revisit enabling these for earlier platforms in the future. For some unknown reason LNL pipe B triggers the error interrupt during the first DC state transition (subsequent transitions are maybe OK?). No clear idea what's going on here yet, so keep the error interrupt disabled for now. Similar to DSB interrupt registers, the unused bits in PIPEDMC_INTERRUPT* seem to act like randomg r/w bits (instead of being hardwired to 0 like one would expect), and so we'll try to avoid setting them so that we don't mistake them for real interrupts. v2: Only enable/unmask for LNL+ Keep the flip queue interrupt masked off for now since we don't have a use for it yet v3: Also keep the error interrupt masked off for now due to LNL pipe B triggering it Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250514174257.8708-1-ville.syrjala@linux.intel.com
2025-05-16drm/i915/dmc: Drop PIPEDMC faults from the fault mask on LNL+Ville Syrjälä
On LNL+ PIPEDMC faults are reported via PIPEDMC interrupts instead of the direct DE_PIPE_* reporting used on earlier platforms. Drop the relevant bits from the fault mask. The bits are tied to zero on LNL, so there is no danger of spurious fault interrupts even with an incorrect mask. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250512103358.15724-2-ville.syrjala@linux.intel.com Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
2025-05-16drm/{i915,xe}: convert i915 and xe display members into pointersJani Nikula
As the first step towards making struct intel_display an opaque pointer in i915 and xe drivers, convert the struct drm_i915_private and struct xe_device display members into pointers. Initially, add temporary struct intel_display __display members, and point display at it to avoid dynamic allocation. In the future, we can drop this, and switch to dynamic allocation. The conversion is done simply with sed: sed -i 's/&\([a-zA-Z0-9_>.-]*\)\(dev_priv\|i915\|xe\)->display\([^.]\)/\1\2->display\3/g' \ $(git ls-files -- drivers/gpu/drm/i915 drivers/gpu/drm/xe) sed -i 's/\(dev_priv\|i915\|xe\)->display\./\1->display->/g' \ $(git ls-files -- drivers/gpu/drm/i915 drivers/gpu/drm/xe) With a couple of manual tweaks on top. v2: Initialize i915->display also in selftest mock_gem_device() Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250507152254.2398934-1-jani.nikula@intel.com
2025-05-16drm/i915: do not reference i915->display inlineJani Nikula
Always use a local variable for display instead of referencing i915->display inline. This makes it easier to convert i915->display into a pointer. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/afcf305e8c4ea452cee37479530958f36a10c840.1746610601.git.jani.nikula@intel.com
2025-05-16Merge drm/drm-next into drm-intel-nextJani Nikula
Backmerge to sync with v6.15-rc, xe, and specifically async flip changes in drm-misc. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-16Merge tag 'drm-intel-next-fixes-2025-05-15' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next - Stop writing ALPM registers when PSR is enabled - Use the correct connector while computing the link BPP limit on MST Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://lore.kernel.org/r/aCWlWk5rTE7TH1pN@jlahtine-mobl
2025-05-15drm/i915/pci: Remove force_probe requirement for DG1Ville Syrjälä
Dunno why we still have .require_force_probe=1 on DG1 after all this time. I'm not aware of any real problems with DG1, so get rid of the force_probe requirement. Generally the difficulty with DG1 is that it requires a 4GiB BAR for the local memory, and that's not something that works on every system. Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20250411144313.11660-3-ville.syrjala@linux.intel.com
2025-05-15drm/i915/gem: Allow EXEC_CAPTURE on recoverable contexts on DG1Ville Syrjälä
The intel-media-driver is currently broken on DG1 because it uses EXEC_CAPTURE with recovarable contexts. Relax the check to allow that. I've also submitted a fix for the intel-media-driver: https://github.com/intel/media-driver/pull/1920 Cc: stable@vger.kernel.org # v6.0+ Cc: Matthew Auld <matthew.auld@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Testcase: igt/gem_exec_capture/capture-invisible Fixes: 71b1669ea9bd ("drm/i915/uapi: tweak error capture on recoverable contexts") Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20250411144313.11660-2-ville.syrjala@linux.intel.com
2025-05-15Merge tag 'drm-misc-next-2025-05-12' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v6.16-rc1: Once more, with async flips. UAPI Changes: - Add IN_FORMATS_ASYNC property, use in i915. Cross-subsystem Changes: - Remove some unused debug code in dma-buf. Core Changes: Driver Changes: - Add Novatek NT37801 panel. - Allow submitting empty commands in amdxdna. - Convert cirrus to use managed request_all_regions. - Move Sitronix from tiny to their own place. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://lore.kernel.org/r/23ded62c-6a62-4195-9c08-4dfb81eafd72@linux.intel.com
2025-05-14drm/i915/ptl: Use everywhere the correct DDI port clock select maskImre Deak
The PTL XELPDP_PORT_CLOCK_CTL register XELPDP_DDI_CLOCK_SELECT field's size is 5 bits vs. the earlier platforms where its size is 4 bits. Make sure the field is read-out/programmed everywhere correctly, according to the above. Cc: Mika Kahola <mika.kahola@intel.com> Cc: stable@vger.kernel.org # v6.13+ Tested-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250512142600.824347-1-imre.deak@intel.com
2025-05-14drm/i915/alpm: Stop writing ALPM registers when PSR is enabledJouni Högander
Currently we are seeing these on PTL: xe 0000:00:02.0: [drm] *ERROR* Timeout waiting for DDI BUF A to get active These seem to be caused by writing ALPM registers while Panel Replay is enabled. Fix this by writing ALPM registers only when Panel Replay is about to be enabled. v4: improve comment on intel_psr_panel_replay_enable_sink call v3: enable/disable ALPM from PSR code Fixes: 172757acd6f6 ("drm/i915/lobf: Add lobf enablement in post plane update") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250513054814.3702977-3-jouni.hogander@intel.com (cherry picked from commit a8eb102ce0944a9de2a62aa9d195861b7f26668a) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2025-05-14drm/i915/alpm: Make intel_alpm_enable_sink available for PSRJouni Högander
We want to enable sink ALPM from PSR code. Make intel_alpm_enable_sink available for PSR. v2: do not add kerneldoc comments Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250513054814.3702977-2-jouni.hogander@intel.com (cherry picked from commit 2d278488761f0b5be651a3db41e615a964123d6c) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2025-05-14drm/i915/display: drop unnecessary includes on i915 core headersJani Nikula
These includes have become unnecessary. Drop them. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/6ca3be3e3fbbd99c169345c3add4b76315390e77.1747128495.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-14drm/i915/gem: drop intel_display.h includeJani Nikula
The include is not needed since commit 44a34dec43e8 ("drm/i915: Calculate the VT-d guard size in the display code"). Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/80ea203e004b7378c14f2367258b5785e40bf126.1747128495.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-14drm/i915/display: drop unused declarations from intel_display.hJani Nikula
We've accumulated lots of forward declarations in intel_display.h that are no longer necessary. Clean them up. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/5ad046b74040e84fab51786c346ff9a445e351bc.1747128495.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-14drm/i915/rps: pass struct intel_display to DISPLAY_VER()Jani Nikula
Avoid passing drm_i915_private to DISPLAY_VER(). Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/5e97ee7675b32397163eb4fba17184fc1c5a04cd.1747128495.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-14drm/i915/pps: drop dependency on intel_display_conversion.hJani Nikula
All the PPS register users have been converted to struct intel_display. The backward compat conversion to struct drm_i915_private is no longer needed. Drop it, along with the include, and convert the dev_priv macro parameter names to display while at it. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/4c23fd8dfcadefeeb52189045421084bcfd50d57.1747128495.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-14drm/i915/alpm: Stop writing ALPM registers when PSR is enabledJouni Högander
Currently we are seeing these on PTL: xe 0000:00:02.0: [drm] *ERROR* Timeout waiting for DDI BUF A to get active These seem to be caused by writing ALPM registers while Panel Replay is enabled. Fix this by writing ALPM registers only when Panel Replay is about to be enabled. v4: improve comment on intel_psr_panel_replay_enable_sink call v3: enable/disable ALPM from PSR code Fixes: 172757acd6f6 ("drm/i915/lobf: Add lobf enablement in post plane update") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250513054814.3702977-3-jouni.hogander@intel.com
2025-05-14drm/i915/alpm: Make intel_alpm_enable_sink available for PSRJouni Högander
We want to enable sink ALPM from PSR code. Make intel_alpm_enable_sink available for PSR. v2: do not add kerneldoc comments Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250513054814.3702977-2-jouni.hogander@intel.com
2025-05-13drm/i915/dp_mst: Use the correct connector while computing the link BPP ↵Imre Deak
limit on MST Atm, on an MST link in DSC mode intel_dp_compute_config_link_bpp_limits() calculates the maximum link bpp limit using the MST root connector's DSC capabilities. That's not correct in general: the decompression could be performed by a branch device downstream of the root branch device or the sink itself. Fix the above by passing to intel_dp_compute_config_link_bpp_limits() the actual connector being modeset, containing the correct DSC capabilities. Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Fixes: 1c5b72daff46 ("drm/i915/dp: Set the DSC link limits in intel_dp_compute_config_link_bpp_limits") Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-2-imre.deak@intel.com (cherry picked from commit 266e2fcfe2ea0d062ea392cd22f6250ae0d11c04) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2025-05-13Merge branch 'x86/msr' into x86/core, to resolve conflictsIngo Molnar
Conflicts: arch/x86/boot/startup/sme.c arch/x86/coco/sev/core.c arch/x86/kernel/fpu/core.c arch/x86/kernel/fpu/xstate.c Semantic conflict: arch/x86/include/asm/sev-internal.h Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-05-13drm/i915: Use provided dma_fence_is_chainTvrtko Ursulin
Replace open-coded helper with the subsystem one. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net> Link: https://lore.kernel.org/r/20250512072047.56851-1-tvrtko.ursulin@igalia.com
2025-05-13drm/i915: ensure correct VLV IOSF SB units have been get/putJani Nikula
Add some extra paranoia to check correct use of the VLV IOSF SB get/put/read/write. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/be6f029adf7148198821e5fe01dcf5d5406aa1fe.1747061743.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-13drm/i915: rename VLV IOSF SB ports parameter to unit_maskJani Nikula
Clarify what the parameter is about through proper naming. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/b1be9a4089dfbf48ea1434944a4841d2ac4c4acc.1747061743.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-13drm/i915: convert VLV IOSF SB interface to struct drm_deviceJani Nikula
With users both in i915 core and display, struct drm_device is the common denominator for the VLV IOSF SB users. Also use drm_device for the helpers on the display side to keep the static inlines as simple as possible. We can drop a number of dependencies on i915_drv.h with this. v2,v3: Rebase Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/c1d013ed88ce2e3e5bdc15ce3bf01a3960b1e817.1747061743.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-13drm/i915: move VLV IOSF SB unit specific helpers under displayJani Nikula
Now that all the VLV IOSF SB unit specific helper users are under display, relocate the helpers themselves under display as well. Resurrect the vlv_sideband.[ch] name for this. Make everything except DPIO helpers static inlines, as their implementations are trivial. All of this considerably simplifies the xe compat header. v2: Rebase Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/e86c2498c9f1c1d30f8e83fa5f1c23526b87b9ab.1747061743.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-13drm/i915: switch i915 core to generic VLV IOSF SB functionsJani Nikula
We'll want to relocate the unit specific functions to display, making them inaccessible to i915 core. As there aren't that many users in i915 core, we can just convert them to the generic VLV IOSF SB read/write functions. v2: Use BIT(unit) for get/put Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/3162c8768eeeba928bbc3d4aa2ddfc6a1030a451.1747061743.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-13drm/i915: rewrite VLV IOSF SB unit specific read/write functionsJani Nikula
Rewrite the VLV IOSF SB unit specific helpers in terms of the new generic read/write functions. They become even simpler than they were. The DPIO get/put helpers need to get/put both DPIO units. v2: get/put both DPIO units Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1 Link: https://lore.kernel.org/r/df97dafa0f7b665e2078c392f0dc3edc59655b0a.1747061743.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-13drm/i915: add generic read/write functions for VLV IOSF SBJani Nikula
The read/write functions will be helpful for rewriting the unit specific functions. v2: Fix checkpatch complaint on indent Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/babe42609c7a2056aff301320efbda534d20ad82.1747061743.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-13drm/i915: rename vlv_sideband*.[ch] to vlv_iosf_sb*.[ch]Jani Nikula
Be more specific in the naming, and follow the existing function naming pattern of vlv_iosf_sb_*() in the file. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/d3d97d34a197ba801c558c3fd72b29f9e5c783af.1747061743.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-12drm/i915/dp_mst: Enable fractional link bpps on MST if the bpp is forcedImre Deak
Enable using a fractional (compressed) link bpp on MST links, if this is supported and the link bpp is forced. Fractional link bpps will be enabled by default as a follow-up change after testing this functionality within a set of commonly used MST monitors and docks/hubs which support it. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-13-imre.deak@intel.com
2025-05-12drm/i915: Add support for forcing the link bpp on a connectorImre Deak
Add support for forcing the link bpp on a connector via a connector debugfs entry. During reducing link bpps due to a link BW limit, keep bpps close to their forced value. Add the debugfs entry to all relevant connectors: all DP connectors and on an FDI link CRT/SDVO/LVDS/HDMI connectors. v2: - Move adding the debugfs entries to this patch. - Rename i915_force_link_bpp to intel_force_link_bpp. (Jani) - Select the relevant connectors via platform checks. (Jani) - Use for_each_new_intel_connector_in_state(). (Jani) - Fix 64 bit division vs. 32 bit build when converting str to q4. (lkp) - Avoid division and addition overflow when converting str to q4. v3: - Add TODO: to make the non-DSC min bpp value connector specific. (Ankit) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-12-imre.deak@intel.com
2025-05-12drm/i915/dp: Export intel_dp_dsc_min_src_compressed_bpp()Imre Deak
Export the function that can be used by a follow-up change to query the minimum compressed link bpp supported by the HW. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-11-imre.deak@intel.com
2025-05-12drm/i915/display: Factor out intel_display_{min, max}_pipe_bpp()Imre Deak
Factor out helpers that can be used in a follow-up change to query the minimum and maximum pipe bpp supported by the HW. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-10-imre.deak@intel.com
2025-05-12drm/i915/dp_mst: Add support for fractional compressed link bpps on MSTImre Deak
Add support for a fractional compressed link bpp on an MST link. Leave the actual enabling of fractional bpps to a follow-up change. While at it add an assert before the bpp loop, that the min and max bpps are aligned to the bpp step. This should hold regardless of the non-DSC/DSC or MST/UHBR-SST modes. This keeps the mode validation and DSC->DPT BW specific maximum link bpps as rounded-down integer values still, changing those to a fractional value is left for later, add here TODO comments for them. v2: - Align the min/max bpp value to the bpp step. - Assert that the min/max bpp values are aligned to the bpp step. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-9-imre.deak@intel.com
2025-05-12drm/i915/dp: Limit max link bpp properly to a fractional value on SSTImre Deak
The maximum link bpp - determined by the link BW for instance - can be fractional, handle this properly during computing the link bpp on SST. This keeps the pipe joiner specific maximum link bpp as a rounded-down integer value still, changing that to a fractional value is left for later. v2: Align the min/max bpp value to the bpp step. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-8-imre.deak@intel.com
2025-05-12drm/i915/dp_mst: Simplify computing the min/max compressed bpp limitsImre Deak
Adjusting the compressed bpp range min/max limits in intel_dp_dsc_nearest_valid_bpp() is unnecessary: - The source/sink min/max values are enforced already by the link_config_limits::min_bpp_x16/max_bpp_x16 values computed early in intel_dp_compute_config_link_bpp_limits(). - The fixed set of valid bpps are enforced already - for all bpps in the min .. max range by intel_dp_dsc_valid_compressed_bpp() called from intel_dp_mtp_tu_compute_config(). The only thing needed is limiting max compressed bpp below the uncompressed pipe bpp, do that one thing only instead of calling intel_dp_dsc_nearest_valid_bpp(). Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-7-imre.deak@intel.com
2025-05-12drm/i915/dp_mst: Check BW limit on the local MST link earlyImre Deak
Check the BW requirement of a selected compressed bpp against the total MST link BW early. This didn't cause a problem, since all the BW limits within the MST topology are checked during the later MST topology BW check. However it doesn't make sense to defer the total link BW check, since for resolving a BW limit issue due to this later also (a) requires selecting a pipe to reduce its bpp, ending up reducing the bpp for another pipe, which is not ideal (b) requires recomputing the state for all CRTC/stream's in the topology which may slow down the commit considerably (especially when using fractional bpps). Based on the above, check a stream bpp's BW requirement against the MST link's total BW early. Ideally drm_dp_atomic_find_time_slots() should check internally the corresponding PBN/TU slot BW against the total link BW, returning an error if the check fails, however that change would also affect other drivers, so leaving this for a follow-up. v2: Rephrase description of pipe selection/bpp reduction in commit message. (Ankit) Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-6-imre.deak@intel.com
2025-05-12drm/i915/dp_mst: Update the total link slot count earlyImre Deak
A follow up change will check a selected bpp's BW requirement in intel_dp_mtp_tu_compute_config(), however that requires the total link slot count to be up-to-date. The latter in turn depends on the channel encoding and hence the link rate used, so it can be set after the link rate used is selected. This also allows simplifying mst_stream_update_slots(), do that as well, moving the function definition before its use. Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-5-imre.deak@intel.com
2025-05-12drm/i915/dp_mst: Validate compressed bpp vs. platform restrictionsImre Deak
Atm TGL supports only a fixed set of valid DSC compressed bpps (6,8,10,12,15), but this is not taken into account while looking for a bpp in the minimum..maximum compressed bpp range. This happened to work only by chance since atm from the above min..max range it's always the maximum bpp that is selected, which is one of the above valid bpps (see mst_stream_dsc_compute_link_config() -> intel_dp_dsc_nearest_valid_bpp()). Before selecting a bpp however, the bpp's BW requirement should be checked wrt. to the MST total link BW; after doing that - in a follow-up change - the validity of any bpp in the min..max range must be ensured before the bpp is selected, do that here. Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-4-imre.deak@intel.com
2025-05-12drm/i915/dp_mst: Simplify handling the single-bpp case during state computationImre Deak
A follow-up change wants to skip invalid bpps in the bpp select loop of a stream state computation. To allow for that, using the usual 'continue' statement in the loop, change the way the single-bpp range is handled. v2: Fix typo in commit message. (Ankit) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-3-imre.deak@intel.com
2025-05-12drm/i915/dp_mst: Use the correct connector while computing the link BPP ↵Imre Deak
limit on MST Atm, on an MST link in DSC mode intel_dp_compute_config_link_bpp_limits() calculates the maximum link bpp limit using the MST root connector's DSC capabilities. That's not correct in general: the decompression could be performed by a branch device downstream of the root branch device or the sink itself. Fix the above by passing to intel_dp_compute_config_link_bpp_limits() the actual connector being modeset, containing the correct DSC capabilities. Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Fixes: 1c5b72daff46 ("drm/i915/dp: Set the DSC link limits in intel_dp_compute_config_link_bpp_limits") Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250509180340.554867-2-imre.deak@intel.com
2025-05-12drm/i915/selftest: allow larger memory allocationMikolaj Wasiak
Due to changes in allocator, the size of the allocation for contiguous region is not rounded up to a power-of-two and instead allocated as is. Thus, change the part of test that expected the allocation to fail. Signed-off-by: Mikolaj Wasiak <mikolaj.wasiak@intel.com> Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Krzysztof Niemiec <krzysztof.niemiec@intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/fptevdfbclvg2lbfuys5ibffbl2baouywkutnr7vdsy5tzcqfk@mpflwlh6jxfd
2025-05-12drm/i915/irq: stop using HAS_GMCH()Jani Nikula
Right or wrong, HAS_GMCH() has become a display only thing. The last three users outside of display are in irq code. Reorder the if ladders to stop using HAS_GMCH(). Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://lore.kernel.org/r/20250502120725.439800-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-10Merge tag 'drm-intel-next-2025-05-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Non-display related: - Fix undefined reference to `intel_pxp_gsccs_is_ready_for_sessions' Display related: - More work towards display separation (Jani) - Stop writing VRR_CTL_IGN_MAX_SHIFT for MTL onwards (Jouni) - DSC checks for 3 engines (Ankit) - Add link rate and lane count to i915_display_info (Khaled) - PSR fixes and workaround for underrun on idle (Jouni) - LOBF enablement and ALMP fixes (Animesh) - Clean up VGA plane handling (Ville) - Use an intel_connector pointer everywhere (Imre) - Fix warning for coffeelake on SunrisePoint PCH (Jiajia) - Rework/Correction on minimum hblank calculation (Arun) - Dmesg clean up (Jani) - Add a couple of simple display workarounds (Ankit, Vinod) - Refactor HDCP GSC (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/aByyL3bEufPu79OM@intel.com
2025-05-09drm/i915/display: Indexed 8bit format does not support async flipArun R Murthy
Async flip is not supported with Indexed 8 bit format as it depends on LUT and can't be updated atomically. Note: This may change the alignment for C8 framebuffers on some platforms. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250407-asyn-v13-5-b93ef83076c5@intel.com
generated by cgit (git 2.34.1) at 2025-08-01 22:50:32 +0000