From 30eba8c45b512634f389461adb8b8765e0090522 Mon Sep 17 00:00:00 2001 From: Leonard Göhrs Date: Tue, 21 Jan 2025 12:14:05 +0100 Subject: dt-bindings: arm: stm32: add compatible strings for Linux Automation GmbH LXA FairyTux 2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Linux Automation GmbH FairyTux2 is a small Linux device based on an Octavo Systems OSD32MP153c SiP, that occupies just two slots on a DIN rail. Add compatible for the generation 1 and 2 based on the STM32MP153c. Signed-off-by: Leonard Göhrs Acked-by: Krzysztof Kozlowski Signed-off-by: Marc Kleine-Budde Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index b6c56d4ce6b9..6825d965da3d 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -94,6 +94,8 @@ properties: - description: Octavo OSD32MP153 System-in-Package based boards items: - enum: + - lxa,stm32mp153c-fairytux2-gen1 # Linux Automation FairyTux 2 (Generation 1) + - lxa,stm32mp153c-fairytux2-gen2 # Linux Automation FairyTux 2 (Generation 2) - lxa,stm32mp153c-tac-gen3 # Linux Automation TAC (Generation 3) - const: oct,stm32mp153x-osd32 - const: st,stm32mp153 -- cgit From 8c6d469f524960a0f97ec74f1d9ac737a39c3f1e Mon Sep 17 00:00:00 2001 From: Leonard Göhrs Date: Tue, 21 Jan 2025 12:14:06 +0100 Subject: ARM: dts: stm32: lxa-fairytux2: add Linux Automation GmbH FairyTux 2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Linux Automation GmbH FairyTux2 is a small Linux device based on an Octavo Systems OSD32MP153c SiP, that occupies just two slots on a DIN rail. The device contains an eMMC for storage, a gigabit Ethernet connection, a CAN bus and a RS485 transceiver. Add support for the lxa-fairytux2 generation 1 and 2 boards based on the STM32MP153c. Signed-off-by: Leonard Göhrs Signed-off-by: Marc Kleine-Budde Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/Makefile | 2 + .../boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts | 103 ++++++ .../boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts | 147 ++++++++ .../arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi | 397 +++++++++++++++++++++ 4 files changed, 649 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts create mode 100644 arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts create mode 100644 arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index b7d5d305cbbe..f68da19d7cbf 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -39,6 +39,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151c-mect1s.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp153c-dhcor-drc-compact.dtb \ + stm32mp153c-lxa-fairytux2-gen1.dtb \ + stm32mp153c-lxa-fairytux2-gen2.dtb \ stm32mp153c-lxa-tac-gen3.dtb \ stm32mp153c-mecio1r1.dtb \ stm32mp157a-avenger96.dtb \ diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts new file mode 100644 index 000000000000..3a0e84262424 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2024 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp153c-lxa-fairytux2.dtsi" + +/ { + model = "Linux Automation GmbH FairyTux 2 Gen 1"; + compatible = "lxa,stm32mp153c-fairytux2-gen1", "oct,stm32mp153x-osd32", "st,stm32mp153"; + + gpio-keys { + compatible = "gpio-keys"; + + button-left { + label = "USER_BTN1"; + linux,code = ; + gpios = <&gpioi 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-right { + label = "USER_BTN2"; + linux,code = ; + gpios = <&gpioe 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&gpiof { + gpio-line-names = "GPIO1", "GPIO2", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioh { + gpio-line-names = "", "", "", "", "LCD_RESET", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "GPIO3", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioi { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "ETH_", "", /* 5 */ + "", "USER_BTN1"; /* 10 */ +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + status = "okay"; + + io_board_gpio: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&v3v3_hdmi>; + gpio-line-names = "LED1_GA_YK", "LED2_GA_YK", "LED1_GK_YA", "LED2_GK_YA", + "RS485_EN", "RS485_120R", "", "CAN_120R"; + }; +}; + +&led_controller_io { + /* + * led-2 and led-3 are internally connected antiparallel to one + * another inside the ethernet jack like this: + * GPIO1 ---+---|led-2|>--+--- GPIO3 + * +--<|led-3|---+ + * E.g. only one of the LEDs can be illuminated at a time while + * the other output must be driven low. + * This should likely be implemented using a multi color LED + * driver for antiparallel LEDs. + */ + led-2 { + color = ; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 1 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&usart3 { + /* + * On Gen 1 FairyTux 2 only RTS can be used and not CTS as well, + * Because pins PD11 (CTS) and PI11 (USER_BTN1) share the same + * interrupt and only one of them can be used at a time. + */ + rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; +}; + +&usbotg_hs { + dr_mode = "peripheral"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts new file mode 100644 index 000000000000..66e6da912508 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2024 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp153c-lxa-fairytux2.dtsi" + +/ { + model = "Linux Automation GmbH FairyTux 2 Gen 2"; + compatible = "lxa,stm32mp153c-fairytux2-gen2", "oct,stm32mp153x-osd32", "st,stm32mp153"; + + gpio-keys { + compatible = "gpio-keys"; + + button-left { + label = "USER_BTN1"; + linux,code = ; + gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-right { + label = "USER_BTN2"; + linux,code = ; + gpios = <&gpioe 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&gpiof { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioh { + gpio-line-names = "", "", "", "", "LCD_RESET", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "GPIO1", "GPIO_INT", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioi { + gpio-line-names = "GPIO2", "", "", "", "", /* 0 */ + "", "", "", "ETH_", "", /* 5 */ + "", "USER_BTN1"; /* 10 */ +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + status = "okay"; + + io_board_gpio: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpioh>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&board_tca6408_pins>; + #interrupt-cells = <2>; + vcc-supply = <&v3v3_hdmi>; + gpio-line-names = "LED1_GA_YK", "LED2_GA_YK", "LED1_GK_YA", "USB_CC_ALERT", + "RS485_EN", "RS485_120R", "USB_CC_RESET", "CAN_120R"; + }; + + usb_c: typec@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupt-parent = <&io_board_gpio>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <®_5v>; + vsys-supply = <&v3v3_hdmi>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + con_usbotg_hs_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + + temperature-sensor@48 { + compatible = "national,lm75a"; + reg = <0x48>; + /* + * The sensor itself is powered by a voltage divider from the + * always-on 5V supply. + * The required pull-up resistors however are on v3v3_hdmi. + */ + vs-supply = <&v3v3_hdmi>; + }; + + io_board_eeprom: eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + vcc-supply = <&v3v3_hdmi>; + }; +}; + +&rtc { + status = "okay"; +}; + +&led_controller_io { + led-2 { + color = ; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 1 GPIO_ACTIVE_LOW>; + }; +}; + +&usart3 { + rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpiod 11 GPIO_ACTIVE_LOW>; +}; + +&usbotg_hs { + usb-role-switch; + + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; +}; + +&pinctrl { + board_tca6408_pins: stusb1600-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi new file mode 100644 index 000000000000..9eeb9d6b5eb0 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023, 2024 Leonard Göhrs, Pengutronix + */ + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include +#include +#include +#include + +/ { + aliases { + can0 = &m_can1; + ethernet0 = ðernet0; + i2c0 = &i2c1; + i2c1 = &i2c4; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &usart3; + spi0 = &spi4; + }; + + chosen { + stdout-path = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&v3v3>; + + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + pwms = <&led_pwm 3 1000000 0>; + }; + + led-controller-cpu { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + led_controller_io: led-controller-io { + compatible = "gpio-leds"; + + /* + * led-0 and led-1 are internally connected antiparallel to one + * another inside the ethernet jack like this: + * GPIO0 ---+---|led-0|>--+--- GPIO2 + * +--<|led-1|---+ + * E.g. only one of the LEDs can be illuminated at a time while + * the other output must be driven low. + * This should likely be implemented using a multi color LED + * driver for antiparallel LEDs. + */ + led-0 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&io_board_gpio 0 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&io_board_gpio 2 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_1v2: regulator-1v2 { + compatible = "regulator-fixed"; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_5v>; + }; +}; + +baseboard_eeprom: &sip_eeprom { +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>; + + st,eth-clk-sel; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { /* KSZ9031RN */ + reg = <3>; + reset-gpios = <&gpioe 11 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + interrupt-parent = <&gpioa>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ + reset-assert-us = <10000>; + reset-deassert-us = <300>; + micrel,force-master; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "ETH_INT", "", "", "", /* 5 */ + "", "", "", "BOOTROM_LED", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiob { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioc { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", ""; /* 10 */ +}; + +&gpiod { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "LCD_TE", "", "", /* 5 */ + "LCD_DC", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioe { + gpio-line-names = "LCD_CS", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiof { + gpio-line-names = "GPIO1", "GPIO2", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiog { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioz { + gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", /* 0 */ + "", "HWID4", "HWID5"; /* 5 */ +}; + +&hash1 { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <8>; + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "okay"; + termination-gpios = <&io_board_gpio 7 GPIO_ACTIVE_HIGH>; + termination-ohms = <120>; +}; + +&pmic { + regulators { + buck1-supply = <®_5v>; /* VIN */ + buck2-supply = <®_5v>; /* VIN */ + buck3-supply = <®_5v>; /* VIN */ + buck4-supply = <®_5v>; /* VIN */ + ldo2-supply = <®_5v>; /* PMIC_LDO25IN */ + ldo4-supply = <®_5v>; /* VIN */ + ldo5-supply = <®_5v>; /* PMIC_LDO25IN */ + vref_ddr-supply = <®_5v>; /* VIN */ + boost-supply = <®_5v>; /* PMIC_BSTIN */ + pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + vmmc-supply = <&v3v3>; + + bus-width = <8>; + mmc-ddr-3_3v; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + + status = "okay"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + lcd: display@0 { + compatible = "shineworld,lh133k", "panel-mipi-dbi-spi"; + reg = <0>; + power-supply = <&v3v3>; + io-supply = <&v3v3>; + backlight = <&backlight>; + dc-gpios = <&gpiod 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_HIGH>; + spi-3wire; + spi-max-frequency = <32000000>; + + width-mm = <23>; + height-mm = <23>; + rotation = <180>; + + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <0>; + vback-porch = <0>; + + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@1 { + status = "okay"; + }; +}; + +&timers3 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@3 { + status = "okay"; + }; +}; + +&timers8 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + led_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm8_pins_b>; + pinctrl-1 = <&pwm8_sleep_pins_b>; + status = "okay"; + }; +}; + +&uart4 { + label = "debug"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usart3 { + label = "external"; + + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + + vusb_d-supply = <&vdd_usb>; + vusb_a-supply = <®18>; + + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&v3v3_hdmi { + regulator-enable-ramp-delay = <1000>; +}; -- cgit From d9b48a56b24b6dc812ee4c4904ff778e2c436047 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 3 Feb 2025 09:58:17 +0100 Subject: dt-bindings: vendor-prefixes: Add prefix for Priva Introduce the 'pri' vendor prefix for Priva, a company specializing in sustainable solutions for building automation, energy, and climate control. More information about Priva can be found at https://www.priva.com Signed-off-by: Oleksij Rempel Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250203085820.609176-2-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 5079ca6ce1d1..afdd861b4cad 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1202,6 +1202,8 @@ patternProperties: description: Primux Trading, S.L. "^probox2,.*": description: PROBOX2 (by W2COMP Co., Ltd.) + "^pri,.*": + description: Priva "^prt,.*": description: Protonic Holland "^pulsedlight,.*": -- cgit From f3607b168318e62172f1d08132a84e823612ce32 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 3 Feb 2025 09:58:18 +0100 Subject: dt-bindings: arm: stm32: Add Priva E-Measuringbox board Add support for the Priva E-Measuringbox ('pri,prihmb') board based on the ST STM32MP133 SoC to the STM32 devicetree bindings. Signed-off-by: Oleksij Rempel Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250203085820.609176-3-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 6825d965da3d..082337a177f8 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -51,6 +51,12 @@ properties: - st,stm32mp135f-dk - const: st,stm32mp135 + - description: ST STM32MP133 based Boards + items: + - enum: + - pri,prihmb # Priva E-Measuringbox board + - const: st,stm32mp133 + - description: ST STM32MP151 based Boards items: - enum: -- cgit From d5a79bf998dca1d51f6938f236e14f53be38628a Mon Sep 17 00:00:00 2001 From: Roan van Dijk Date: Mon, 3 Feb 2025 09:58:19 +0100 Subject: ARM: dts: stm32: Add thermal support for STM32MP131 Add thermal zone configuration and sensor node for STM32MP131 SoC. Signed-off-by: Roan van Dijk Signed-off-by: Oleksij Rempel Link: https://lore.kernel.org/r/20250203085820.609176-4-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 0019d12c3d3d..8512a6e46b33 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -100,6 +100,31 @@ always-on; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&dts>; + + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -919,6 +944,16 @@ }; }; + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = ; + clocks = <&rcc DTS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; -- cgit From 80c7ee9c20946bff988d4008cde82e12bb717666 Mon Sep 17 00:00:00 2001 From: Roan van Dijk Date: Mon, 3 Feb 2025 09:58:20 +0100 Subject: ARM: dts: stm32: Add Priva E-Measuringbox devicetree Introduce the devicetree for the Priva E-Measuringbox board (stm32mp133c-prihmb), based on the STM32MP133 SoC. Signed-off-by: Roan van Dijk Signed-off-by: Oleksij Rempel Link: https://lore.kernel.org/r/20250203085820.609176-5-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/Makefile | 1 + arch/arm/boot/dts/st/stm32mp133c-prihmb.dts | 496 ++++++++++++++++++++++++++++ 2 files changed, 497 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32mp133c-prihmb.dts diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index f68da19d7cbf..efbb96d19004 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ stm32h750i-art-pi.dtb \ + stm32mp133c-prihmb.dtb \ stm32mp135f-dhcor-dhsbc.dtb \ stm32mp135f-dk.dtb \ stm32mp151a-prtt1a.dtb \ diff --git a/arch/arm/boot/dts/st/stm32mp133c-prihmb.dts b/arch/arm/boot/dts/st/stm32mp133c-prihmb.dts new file mode 100644 index 000000000000..663b6de1b814 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp133c-prihmb.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/dts-v1/; + +#include +#include +#include +#include +#include "stm32mp133.dtsi" +#include "stm32mp13xc.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "Priva E-Measuringbox board"; + compatible = "pri,prihmb", "st,stm32mp133"; + + aliases { + ethernet0 = ðernet1; + mdio-gpio0 = &mdio0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &usart6; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + counter-0 { + compatible = "interrupt-counter"; + gpios = <&gpioa 11 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-reset { + label = "reset-button"; + linux,code = ; + gpios = <&gpioi 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + led-controller-0 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + + led-red { + active-low; + color = ; + pwms = <&pwm2 2 1000000 1>; + }; + + led-green { + active-low; + color = ; + pwms = <&pwm1 1 1000000 1>; + }; + + led-blue { + active-low; + color = ; + pwms = <&pwm1 2 1000000 1>; + }; + }; + }; + + led-controller-1 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + + led-red { + active-low; + color = ; + pwms = <&pwm1 0 1000000 1>; + }; + + led-green { + active-low; + color = ; + pwms = <&pwm2 0 1000000 1>; + }; + + led-blue { + active-low; + color = ; + pwms = <&pwm2 1 1000000 1>; + }; + }; + }; + + /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce + * stmmac MDC clock without reducing system bus rate, we need to use + * gpio based MDIO bus. + */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpiog 2 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@ce000000 { + reg = <0xce000000 0x02000000>; + no-map; + }; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc_1_pins_a>; + vdda-supply = <®_3v3>; + vref-supply = <®_3v3>; + status = "okay"; +}; + +&adc1 { + status = "okay"; + + channel@0 { /* Fan current PC0*/ + reg = <0>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + channel@11 { /* Fan voltage */ + reg = <11>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + channel@15 { /* Supply voltage */ + reg = <15>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; +}; + +&dts { + status = "okay"; +}; + +ðernet1 { + status = "okay"; + pinctrl-0 = <ðernet1_rmii_pins_a>; + pinctrl-1 = <ðernet1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + phy-handle = <&phy0>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + clock-frequency = <100000>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + board-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + vs-supply = <®_3v3>; + }; +}; + +&{i2c1_pins_a/pins} { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; +}; + +&{i2c1_sleep_pins_a/pins} { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +/* SD card without Card-detect */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +/* EMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + mmc-ddr-3_3v; + bus-width = <8>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&timers1 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm1: pwm { + pinctrl-0 = <&pwm1_pins_a>; + pinctrl-1 = <&pwm1_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&timers4 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm2: pwm { + pinctrl-0 = <&pwm4_pins_a>; + pinctrl-1 = <&pwm4_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +/* Fan PWM */ +&timers5 { + status = "okay"; + + pwm3: pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&timers2 { + status = "okay"; + + timer@1 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_a>; + pinctrl-1 = <&uart7_sleep_pins_a>; + pinctrl-2 = <&uart7_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart6 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart6_pins_a>; + pinctrl-1 = <&usart6_sleep_pins_a>; + pinctrl-2 = <&usart6_idle_pins_a>; + linux,rs485-enabled-at-boot-time; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&pinctrl { + adc_1_pins_a: adc1-0 { + pins { + pinmux = , /* ADC1 in0 */ + , /* ADC1 in15 */ + ; /* ADC1 in11 */ + }; + }; + + ethernet1_rmii_pins_a: rmii-0 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + ; /* ETH1_RMII_REF_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet1_rmii_sleep_pins_a: rmii-sleep-0 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + + pwm1_pins_a: pwm1-0 { + pins { + pinmux = , /* TIM1_CH1 */ + , /* TIM1_CH2 */ + ; /* TIM1_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_a: pwm1-sleep-0 { + pins { + pinmux = , /* TIM1_CH1 */ + , /* TIM1_CH2 */ + ; /* TIM1_CH3 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux = , /* TIM4_CH1 */ + , /* TIM4_CH2 */ + ; /* TIM4_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = , /* TIM4_CH1 */ + , /* TIM4_CH2 */ + ; /* TIM4_CH3 */ + }; + }; + pwm5_pins_a: pwm5-0 { + pins { + pinmux = ; /* TIM5_CH1 */ + }; + }; + + pwm5_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = ; /* TIM5_CH1 */ + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = ; /* UART_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-pull-up; + }; + }; + + uart7_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = ; /* UART7_TX */ + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-pull-up; + }; + }; + + uart7_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = , /* UART7_TX */ + ; /* UART7_RX */ + }; + }; + + usart6_pins_a: usart6-0 { + pins1 { + pinmux = , /* USART6_TX */ + ; /* USART6_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART6_RX */ + bias-disable; + }; + }; + + usart6_idle_pins_a: usart6-idle-0 { + pins1 { + pinmux = ; /* USART6_TX */ + }; + pins2 { + pinmux = ; /* USART6_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART6_RX */ + bias-disable; + }; + }; + + usart6_sleep_pins_a: usart6-sleep-0 { + pins { + pinmux = , /* USART6_TX */ + , /* USART6_DE */ + ; /* USART6_RX */ + }; + }; +}; -- cgit From 4b442649e91e765807d639c7417cf443e0c97ddb Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 17 Feb 2025 12:43:22 +0100 Subject: ARM: dts: stm32: add led to stm32f746 Discovery board Add node for the user led. Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/r/20250217114332.1098482-1-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f746-disco.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index 087de6f09629..8bdd10644bf1 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -78,6 +78,14 @@ serial0 = &usart1; }; + leds { + compatible = "gpio-leds"; + led-usr { + gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; -- cgit From d36f7da43f92b5e682bd6938ee0e44d1ad255282 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 17 Feb 2025 12:43:23 +0100 Subject: ARM: dts: stm32: add push button to stm32f746 Discovery board Add node for user push button. Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/r/20250217114332.1098482-2-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f746-disco.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index 8bdd10644bf1..b57dbdce2f40 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -86,6 +86,16 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "User"; + linux,code = ; + gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; -- cgit From 9ccf47393d5d8245c6ce59800cfe58564d63737f Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 17 Feb 2025 12:45:08 +0100 Subject: ARM: dts: stm32: rename LEDs nodes for stm32f769-disco Associate the LED node name with the corresponding board silkscreen for more precise identification. In fact, the board has a total of seven LEDs, some of which are user-controllable (i. e. usr{1,2,3}), while others are directly controlled by hardware (e. g. power, overcurrent, ...). All these LEDs are either green or red, so using the names led-green and led-red for the two LEDs mapped in the DTS does not simplify their identification on the board. Moreover, this patch is a prerequisite for adding the usr3 LED, which has not been included in the DTS. Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/r/20250217114513.1098844-1-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f769-disco.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 52c5baf58ab9..d52e36aedcfb 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -79,11 +79,11 @@ leds { compatible = "gpio-leds"; - led-green { + led-usr2 { gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - led-red { + led-usr1 { gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; }; -- cgit From 1e494daa7e289706f09c17eb9d753256e462b919 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 17 Feb 2025 12:45:09 +0100 Subject: ARM: dts: stm32: add usr3 LED node to stm32f769-disco As indicated by the board silkscreen, there are three user LEDs. Add the missing one. Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/r/20250217114513.1098844-2-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f769-disco.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index d52e36aedcfb..535cfdc4681c 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -86,6 +86,9 @@ led-usr1 { gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; + led-usr3 { + gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>; + }; }; gpio-keys { -- cgit From 5980d9d0e4a24817151ddacb5308662dc682a086 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 10 Mar 2025 13:23:56 +0100 Subject: ARM: dts: stm32: use IRQ_TYPE_EDGE_FALLING on stm32mp157c-dk2 Replace the number 2 with the appropriate numerical constant defined in dt-bindings/interrupt-controller/irq.h. Signed-off-by: Dario Binacchi Reviewed-by: Antonio Borneo Link: https://lore.kernel.org/r/20250310122402.8795-1-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 5f9c0160a9c4..324f7bb988d1 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -67,7 +67,7 @@ touchscreen@38 { compatible = "focaltech,ft6236"; reg = <0x38>; - interrupts = <2 2>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpiof>; touchscreen-size-x = <480>; touchscreen-size-y = <800>; -- cgit From 44525a456296a47150292aacb0748366f42dc5e6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 2 Mar 2025 16:25:14 +0100 Subject: ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC rev.200 board LDO2 is expansion connector supply on STM32MP13xx DHCOR DHSBC rev.200. LDO5 is carrier board supply on STM32MP13xx DHCOR DHSBC rev.200. Keep both regulators always enabled to make sure both the carrier board and the expansion connector is always powered on and supplied with correct voltage. Describe ST33TPHF2XSPI TPM 2.0 chip interrupt and reset lines. Signed-off-by: Marek Vasut Link: https://lore.kernel.org/r/20250302152605.54792-1-marex@denx.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 30 ++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 853dc21449d9..9902849ed040 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -176,7 +176,7 @@ gpio-line-names = "", "", "", "", "", "DHSBC_USB_PWR_CC1", "", "", "", "", "", "DHSBC_nETH1_RST", - "", "DHCOR_HW-CODING_0", "", ""; + "", "DHCOR_HW-CODING_0", "", "DHSBC_HW-CODE_2"; }; &gpiob { @@ -197,7 +197,7 @@ gpio-line-names = "", "", "", "", "", "DHCOR_RAM-CODING_0", "", "", "", "DHCOR_RAM-CODING_1", "", "", - "", "", "", ""; + "", "DHSBC_HW-CODE_1", "", ""; }; &gpioe { @@ -221,6 +221,13 @@ "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB"; }; +&gpioh { + gpio-line-names = "", "", "", "DHSBC_HW-CODE_0", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + &gpioi { gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1", "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT", @@ -296,6 +303,9 @@ st33htph: tpm@0 { compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; reg = <0>; + interrupt-parent = <&gpioe>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; spi-max-frequency = <24000000>; }; }; @@ -419,3 +429,19 @@ type = "micro"; }; }; + +/* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ +&vdd_ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ +&vdd_sd { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; -- cgit From e0f4274365de5bb156547ccb7f2841b2e5baefa9 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 5 Mar 2025 14:14:22 +0100 Subject: dt-bindings: sound: convert ICS-43432 binding to YAML Convert the ICS-43432 MEMS microphone device tree binding from text format to YAML. Signed-off-by: Oleksij Rempel Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250305131425.1491769-2-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/sound/ics43432.txt | 19 -------- .../bindings/sound/invensense,ics43432.yaml | 51 ++++++++++++++++++++++ 2 files changed, 51 insertions(+), 19 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/ics43432.txt create mode 100644 Documentation/devicetree/bindings/sound/invensense,ics43432.yaml diff --git a/Documentation/devicetree/bindings/sound/ics43432.txt b/Documentation/devicetree/bindings/sound/ics43432.txt deleted file mode 100644 index e6f05f2f6c4e..000000000000 --- a/Documentation/devicetree/bindings/sound/ics43432.txt +++ /dev/null @@ -1,19 +0,0 @@ -Invensense ICS-43432-compatible MEMS microphone with I2S output. - -There are no software configuration options for this device, indeed, the only -host connection is the I2S interface. Apart from requirements on clock -frequency (460 kHz to 3.379 MHz according to the data sheet) there must be -64 clock cycles in each stereo output frame; 24 of the 32 available bits -contain audio data. A hardware pin determines if the device outputs data -on the left or right channel of the I2S frame. - -Required properties: - - compatible: should be one of the following. - "invensense,ics43432": For the Invensense ICS43432 - "cui,cmm-4030d-261": For the CUI CMM-4030D-261-I2S-TR - -Example: - - ics43432: ics43432 { - compatible = "invensense,ics43432"; - }; diff --git a/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml b/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml new file mode 100644 index 000000000000..7bd984817aa9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/invensense,ics43432.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Invensense ICS-43432-compatible MEMS Microphone with I2S Output + +maintainers: + - Oleksij Rempel + +description: + The ICS-43432 and compatible MEMS microphones output audio over an I2S + interface and require no software configuration. The only host connection + is the I2S bus. The microphone requires an I2S clock frequency between + 460 kHz and 3.379 MHz and 64 clock cycles per stereo frame. Each frame + contains 32-bit slots per channel, with 24 bits carrying audio data. + A hardware pin determines whether the microphone outputs audio on the + left or right channel of the I2S frame. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - invensense,ics43432 + - cui,cmm-4030d-261 + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + ics43432: ics43432 { + compatible = "invensense,ics43432"; + + port { + endpoint { + remote-endpoint = <&i2s1_endpoint>; + dai-format = "i2s"; + }; + }; + + }; -- cgit From 3de1c89674b3e6d509fc1dc9c90e605da6786dfa Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 5 Mar 2025 14:14:23 +0100 Subject: dt-bindings: arm: stm32: Add Plymovent AQM board Add support for the Plymovent AQM board based on the ST STM32MP151 SoC to the STM32 devicetree bindings. Signed-off-by: Oleksij Rempel Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250305131425.1491769-3-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 082337a177f8..0ec5c5d9f3f5 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -60,6 +60,7 @@ properties: - description: ST STM32MP151 based Boards items: - enum: + - ply,plyaqm # Plymovent AQM board - prt,mecio1r0 # Protonic MECIO1r0 - prt,mect1s # Protonic MECT1S - prt,prtt1a # Protonic PRTT1A -- cgit From 0144bc5b3ce96c6cdf1be79a0a6db6f02ba30c24 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 5 Mar 2025 14:14:24 +0100 Subject: ARM: dts: stm32: Add pinmux groups for Plymovent AQM board Add pinmux groups required for the Plymovent AQM board. Signed-off-by: Oleksij Rempel Link: https://lore.kernel.org/r/20250305131425.1491769-4-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 292 ++++++++++++++++++++++++++++ 1 file changed, 292 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 95fafc51a1c8..40605ea85ee1 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -25,6 +25,13 @@ }; }; + /omit-if-no-ref/ + adc1_in10_pins_a: adc1-in10-0 { + pins { + pinmux = ; + }; + }; + /omit-if-no-ref/ adc12_ain_pins_a: adc12-ain-0 { pins { @@ -584,6 +591,43 @@ }; }; + /omit-if-no-ref/ + ethernet0_rmii_pins_d: rmii-3 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + ethernet0_rmii_sleep_pins_d: rmii-sleep-3 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + /omit-if-no-ref/ fmc_pins_a: fmc-0 { pins1 { @@ -725,6 +769,25 @@ }; }; + /omit-if-no-ref/ + i2c1_pins_c: i2c1-2 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c1_sleep_pins_c: i2c1-sleep-2 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { @@ -819,6 +882,27 @@ }; }; + /omit-if-no-ref/ + i2s1_pins_a: i2s1-0 { + pins { + pinmux = , /* I2S2_SDI */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + /omit-if-no-ref/ + i2s1_sleep_pins_a: i2s1-sleep-0 { + pins { + pinmux = , /* I2S2_SDI */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + }; + }; + /omit-if-no-ref/ i2s2_pins_a: i2s2-0 { pins { @@ -1418,6 +1502,23 @@ }; }; + /omit-if-no-ref/ + pwm1_pins_d: pwm1-3 { + pins { + pinmux = ; /* TIM5_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + pwm1_sleep_pins_d: pwm1-sleep-3 { + pins { + pinmux = ; + }; + }; + /omit-if-no-ref/ pwm2_pins_a: pwm2-0 { pins { @@ -2160,6 +2261,66 @@ }; }; + /omit-if-no-ref/ + sdmmc2_b4_pins_c: sdmmc2-b4-2 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_c: sdmmc2-b4-od-2 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_c: sdmmc2-b4-sleep-2 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + /omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { @@ -2389,6 +2550,66 @@ }; }; + /omit-if-no-ref/ + sdmmc3_b4_pins_c: sdmmc3-b4-2 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_od_pins_c: sdmmc3-b4-od-2 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux = ; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_sleep_pins_c: sdmmc3-b4-sleep-2 { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; + }; + /omit-if-no-ref/ spdifrx_pins_a: spdifrx-0 { pins { @@ -2600,6 +2821,41 @@ }; }; + /omit-if-no-ref/ + uart4_pins_e: uart4-4 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_idle_pins_e: uart4-idle-4 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_sleep_pins_e: uart4-sleep-4 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + /omit-if-no-ref/ uart5_pins_a: uart5-0 { pins1 { @@ -2677,6 +2933,23 @@ }; }; + /omit-if-no-ref/ + uart7_pins_d: uart7-3 { + pins1 { + pinmux = , /* UART7_TX */ + ; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = , /* UART7_RX */ + ; /* UART7_CTS */ + bias-disable; + }; + }; + /omit-if-no-ref/ uart8_pins_a: uart8-0 { pins1 { @@ -3118,6 +3391,25 @@ }; }; + /omit-if-no-ref/ + i2c6_pins_b: i2c6-1 { + pins { + pinmux = , /* I2C6_SCL */ + ; /* I2C6_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c6_sleep_pins_b: i2c6-sleep-1 { + pins { + pinmux = , /* I2C6_SCL */ + ; /* I2C6_SDA */ + }; + }; + /omit-if-no-ref/ spi1_pins_a: spi1-0 { pins1 { -- cgit From 9365fa46be3589092a06f403cf10faca703a05b6 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 5 Mar 2025 14:14:25 +0100 Subject: ARM: dts: stm32: Add Plymovent AQM devicetree Introduce the devicetree for the Plymovent AQM board (stm32mp151c-plyaqm), based on the STM32MP151 SoC. Signed-off-by: Oleksij Rempel Link: https://lore.kernel.org/r/20250305131425.1491769-5-o.rempel@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/Makefile | 1 + arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts | 376 ++++++++++++++++++++++++++++ 2 files changed, 377 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index efbb96d19004..60d55516f723 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151a-dhcor-testbench.dtb \ stm32mp151c-mecio1r0.dtb \ stm32mp151c-mect1s.dtb \ + stm32mp151c-plyaqm.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp153c-dhcor-drc-compact.dtb \ stm32mp153c-lxa-fairytux2-gen1.dtb \ diff --git a/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts new file mode 100644 index 000000000000..39a3211c6133 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Plymovent AQM board"; + compatible = "ply,plyaqm", "st,stm32mp151"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &uart7; + }; + + codec { + compatible = "invensense,ics43432"; + + port { + codec_endpoint: endpoint { + remote-endpoint = <&i2s1_endpoint>; + dai-format = "i2s"; + }; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; /* WHITE_EN */ + color = ; + default-state = "on"; + }; + }; + + v3v3: fixed-regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + v5v_sw: fixed-regulator-v5sw { + compatible = "regulator-fixed"; + regulator-name = "5v-switched"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpioe 10 GPIO_ACTIVE_HIGH>; /* 5V_SWITCHED_EN */ + startup-delay-us = <100000>; + enable-active-high; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@cfd00000 { + reg = <0xcfd00000 0x300000>; + no-map; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP15"; + dais = <&i2s1_port>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; /* WLAN_REG_ON */ + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_in10_pins_a>; + vdda-supply = <&v3v3>; + vref-supply = <&v3v3>; + status = "okay"; + + adc@0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@10 { /* NTC */ + reg = <10>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; + status = "okay"; +}; + +ðernet0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rmii_pins_d>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_d>; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + /* KSZ8081RNA PHY */ + ethphy0: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpiob 0 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpioa { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "HWID_PL_N", "HWID_CP", ""; +}; + +&gpiob { + gpio-line-names = + "", "", "", "", "", "", "LED_LATCH", "", + "", "RELAY1_EN", "", "", "", "", "", ""; +}; + +&gpioc { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "HWID_Q7", "", ""; +}; + +&gpioe { + gpio-line-names = + "", "", "", "", "RELAY2_EN", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpiog { + gpio-line-names = + "", "", "", "", "", "", "", "SW1", + "", "", "", "", "", "", "", ""; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_c>; + pinctrl-1 = <&i2c1_sleep_pins_c>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&i2c6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_b>; + pinctrl-1 = <&i2c6_sleep_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clocks = <&scmi_clk CK_SCMI_I2C6>; + resets = <&scmi_reset RST_SCMI_I2C6>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pressure-sensor@47 { + compatible = "bosch,bmp580"; + reg = <0x47>; + vdda-supply = <&v5v_sw>; + vddd-supply = <&v5v_sw>; + }; + + co2-sensor@62 { + compatible = "sensirion,scd41"; + reg = <0x62>; + vdd-supply = <&v5v_sw>; + }; + + pm-sensor@69 { + compatible = "sensirion,sps30"; + reg = <0x69>; + }; +}; + +&i2s1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s1_pins_a>; + pinctrl-1 = <&i2s1_sleep_pins_a>; + clocks = <&rcc SPI1>, <&rcc SPI1_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; + #clock-cells = <0>; /* Set I2S2 as master clock provider */ + status = "okay"; + + i2s1_port: port { + i2s1_endpoint: endpoint { + format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&codec_endpoint>; + }; + }; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; + status = "okay"; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; + status = "okay"; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +/* SD card without Card-detect */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +/* EMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_c &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_c &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_c &sdmmc2_d47_sleep_pins_b>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +/* Wifi */ +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_c>; + pinctrl-1 = <&sdmmc3_b4_od_pins_c>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_c>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&timers5 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm { + pinctrl-0 = <&pwm1_pins_d>; + pinctrl-1 = <&pwm1_sleep_pins_d>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_e>; + pinctrl-1 = <&uart4_idle_pins_e>; + pinctrl-2 = <&uart4_sleep_pins_e>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_d>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; /* BT_REG_ON */ + max-speed = <4000000>; + vbat-supply = <&v3v3>; + vddio-supply = <&v3v3>; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; /* BT_HOST_WAKE */ + interrupt-names = "host-wakeup"; + }; +}; -- cgit From be977f2690cb79431b02ed69cdadaa1e86985a39 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 25 Feb 2025 09:54:04 +0100 Subject: dt-bindings: stm32: document stm32mp257f-dk board Add new entry for stm32mp257f-dk board. Signed-off-by: Amelie Delaunay Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-1-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 0ec5c5d9f3f5..456648e2d1e7 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -187,6 +187,7 @@ properties: - description: ST STM32MP257 based Boards items: - enum: + - st,stm32mp257f-dk - st,stm32mp257f-ev1 - const: st,stm32mp257 -- cgit From 113ff0e048ff11e4c52ae97f9fa59fd39c1c0f6a Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Tue, 25 Feb 2025 09:54:05 +0100 Subject: arm64: dts: st: add stm32mp257f-dk board support Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC, with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ... Signed-off-by: Alexandre Torgue Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-2-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/Makefile | 4 +- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 113 ++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/st/stm32mp257f-dk.dts diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile index 881fe1296c58..0cc12f2b1dfe 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_STM32) += stm32mp257f-ev1.dtb +dtb-$(CONFIG_ARCH_STM32) += \ + stm32mp257f-dk.dtb \ + stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts new file mode 100644 index 000000000000..a278a1e3ce03 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include +#include +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-DK Discovery Board"; + compatible = "st,stm32mp257f-dk", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = ; + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + }; + + button-user-2 { + label = "User-2"; + linux,code = ; + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vdd_sdcard: regulator@23 { + reg = ; + regulator-name = "vdd_sdcard"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; -- cgit From f5d548c9248c53c5adbae5201393ab5c60a85871 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 25 Feb 2025 09:54:06 +0100 Subject: arm64: Kconfig: expand STM32 Armv8 SoC with STM32MP21/STM32MP23 SoCs family Expand config ARCH_STM32 with two new SoCs families: - STM32MP21 SoCs family, which is composed of STM32MP211, STM32MP213 and STM32MP215 SoCs; - STM32MP23 SoCs family, which is composed of STM32MP231, STM32MP233 and STM32MP235 SoCs. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-3-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/Kconfig.platforms | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 02f9248f7c84..6b7ca916c9c1 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -321,6 +321,10 @@ config ARCH_STM32 help This enables support for ARMv8 based STMicroelectronics STM32 family, including: + - STM32MP21: + - STM32MP211, STM32MP213, STM32MP215. + - STM32MP23: + - STM32MP231, STM32MP233, STM32MP235. - STM32MP25: - STM32MP251, STM32MP253, STM32MP255 and STM32MP257. -- cgit From 04b2ca486456988a7d0890fdbe215fe5e37d6829 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 25 Feb 2025 09:54:07 +0100 Subject: dt-bindings: stm32: add STM32MP21 and STM32MP23 compatibles for syscon Add the new syscon compatibles for STM32MP21 syscfg = "st,stm32mp21-syscfg" and for STM32MP23 syscfg = "st,stm32mp23-syscfg". Signed-off-by: Amelie Delaunay Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-4-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index d083d8ad48b7..ed97652c8492 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -21,6 +21,8 @@ properties: - st,stm32f4-gcan - st,stm32mp151-pwr-mcu - st,stm32mp157-syscfg + - st,stm32mp21-syscfg + - st,stm32mp23-syscfg - st,stm32mp25-syscfg - const: syscon - items: -- cgit From e9b03ef21386e7583806e1e624a8b44c6722b365 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Tue, 25 Feb 2025 09:54:08 +0100 Subject: arm64: dts: st: introduce stm32mp23 SoCs family STM32MP23 family is composed of 3 SoCs defined as following: -STM32MP231: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP233: STM32MP231 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD. -STM32MP235: STM32MP233 + GPU/AI and video encode/decode, DSI and LDVS display. A second diversity layer exists for security features/ A35 frequency: -STM32MP23xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-5-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 1214 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp233.dtsi | 94 +++ arch/arm64/boot/dts/st/stm32mp235.dtsi | 16 + arch/arm64/boot/dts/st/stm32mp23xc.dtsi | 8 + arch/arm64/boot/dts/st/stm32mp23xf.dtsi | 8 + 5 files changed, 1340 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp231.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp233.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp235.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp23xc.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp23xf.dtsi diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi new file mode 100644 index 000000000000..8820d219a33e --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -0,0 +1,1214 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + reg = <0>; + device_type = "cpu"; + enable-method = "psci"; + power-domains = <&cpu0_pd>; + power-domain-names = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xb200005a>; + status = "disabled"; + }; + + clk_dsi_txbyte: clock-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + clk_rcbsec: clk-64000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <64000000>; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + interrupt-parent = <&intc>; + interrupts = ; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_regu: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_vddio1: regulator@0 { + reg = ; + regulator-name = "vddio1"; + }; + scmi_vddio2: regulator@1 { + reg = ; + regulator-name = "vddio2"; + }; + scmi_vddio3: regulator@2 { + reg = ; + regulator-name = "vddio3"; + }; + scmi_vddio4: regulator@3 { + reg = ; + regulator-name = "vddio4"; + }; + scmi_vdd33ucpd: regulator@5 { + reg = ; + regulator-name = "vdd33ucpd"; + }; + scmi_vdda18adc: regulator@7 { + reg = ; + regulator-name = "vdda18adc"; + }; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu0_pd: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + power-domains = <&ret_pd>; + }; + + ret_pd: power-domain-retention { + #power-domain-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x80000000>; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + + hpdma: dma-controller@40400000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40400000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA1>; + #dma-cells = <3>; + }; + + hpdma2: dma-controller@40410000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40410000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA2>; + #dma-cells = <3>; + }; + + hpdma3: dma-controller@40420000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40420000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA3>; + #dma-cells = <3>; + }; + + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc", "simple-bus"; + reg = <0x42080000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + + i2s2: audio-controller@400b0000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x400b0000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI2_R>; + dmas = <&hpdma 51 0x43 0x12>, + <&hpdma 52 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + spi2: spi@400b0000 { + compatible = "st,stm32mp25-spi"; + reg = <0x400b0000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI2>; + resets = <&rcc SPI2_R>; + dmas = <&hpdma 51 0x20 0x3012>, + <&hpdma 52 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + i2s3: audio-controller@400c0000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x400c0000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI3_R>; + dmas = <&hpdma 53 0x43 0x12>, + <&hpdma 54 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + + spi3: spi@400c0000 { + compatible = "st,stm32mp25-spi"; + reg = <0x400c0000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI3>; + resets = <&rcc SPI3_R>; + dmas = <&hpdma 53 0x20 0x3012>, + <&hpdma 54 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + + spdifrx: audio-controller@400d0000 { + compatible = "st,stm32h7-spdifrx"; + reg = <0x400d0000 0x400>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SPDIFRX>; + clock-names = "kclk"; + interrupts = ; + dmas = <&hpdma 71 0x43 0x212>, + <&hpdma 72 0x43 0x212>; + dma-names = "rx", "rx-ctrl"; + access-controllers = <&rifsc 30>; + status = "disabled"; + }; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART2>; + dmas = <&hpdma 11 0x20 0x10012>, + <&hpdma 12 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 32>; + status = "disabled"; + }; + + usart3: serial@400f0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400f0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART3>; + dmas = <&hpdma 13 0x20 0x10012>, + <&hpdma 14 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 33>; + status = "disabled"; + }; + + uart4: serial@40100000 { + compatible = "st,stm32h7-uart"; + reg = <0x40100000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART4>; + dmas = <&hpdma 15 0x20 0x10012>, + <&hpdma 16 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 34>; + status = "disabled"; + }; + + uart5: serial@40110000 { + compatible = "st,stm32h7-uart"; + reg = <0x40110000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART5>; + dmas = <&hpdma 17 0x20 0x10012>, + <&hpdma 18 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 35>; + status = "disabled"; + }; + + i2c1: i2c@40120000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40120000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C1>; + resets = <&rcc I2C1_R>; + dmas = <&hpdma 27 0x20 0x3012>, + <&hpdma 28 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 41>; + status = "disabled"; + }; + + i2c2: i2c@40130000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40130000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C2>; + resets = <&rcc I2C2_R>; + dmas = <&hpdma 30 0x20 0x3012>, + <&hpdma 31 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 42>; + status = "disabled"; + }; + + i2c7: i2c@40180000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40180000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C7>; + resets = <&rcc I2C7_R>; + dmas = <&hpdma 45 0x20 0x3012>, + <&hpdma 46 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 47>; + status = "disabled"; + }; + + usart6: serial@40220000 { + compatible = "st,stm32h7-uart"; + reg = <0x40220000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART6>; + dmas = <&hpdma 19 0x20 0x10012>, + <&hpdma 20 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 36>; + status = "disabled"; + }; + + i2s1: audio-controller@40230000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x40230000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI1_R>; + dmas = <&hpdma 49 0x43 0x12>, + <&hpdma 50 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi1: spi@40230000 { + compatible = "st,stm32mp25-spi"; + reg = <0x40230000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI1>; + resets = <&rcc SPI1_R>; + dmas = <&hpdma 49 0x20 0x3012>, + <&hpdma 50 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi4: spi@40240000 { + compatible = "st,stm32mp25-spi"; + reg = <0x40240000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI4>; + resets = <&rcc SPI4_R>; + dmas = <&hpdma 55 0x20 0x3012>, + <&hpdma 56 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 25>; + status = "disabled"; + }; + + spi5: spi@40280000 { + compatible = "st,stm32mp25-spi"; + reg = <0x40280000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI5>; + resets = <&rcc SPI5_R>; + dmas = <&hpdma 57 0x20 0x3012>, + <&hpdma 58 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 26>; + status = "disabled"; + }; + + sai1: sai@40290000 { + compatible = "st,stm32mp25-sai"; + reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; + ranges = <0 0x40290000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI1>; + clock-names = "pclk"; + interrupts = ; + resets = <&rcc SAI1_R>; + access-controllers = <&rifsc 49>; + status = "disabled"; + + sai1a: audio-controller@40290004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI1>; + clock-names = "sai_ck"; + dmas = <&hpdma 73 0x43 0x21>; + status = "disabled"; + }; + + sai1b: audio-controller@40290024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI1>; + clock-names = "sai_ck"; + dmas = <&hpdma 74 0x43 0x12>; + status = "disabled"; + }; + }; + + sai2: sai@402a0000 { + compatible = "st,stm32mp25-sai"; + reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; + ranges = <0 0x402a0000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI2>; + clock-names = "pclk"; + interrupts = ; + resets = <&rcc SAI2_R>; + access-controllers = <&rifsc 50>; + status = "disabled"; + + sai2a: audio-controller@402a0004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI2>; + clock-names = "sai_ck"; + dmas = <&hpdma 75 0x43 0x21>; + status = "disabled"; + }; + + sai2b: audio-controller@402a0024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI2>; + clock-names = "sai_ck"; + dmas = <&hpdma 76 0x43 0x12>; + status = "disabled"; + }; + }; + + sai3: sai@402b0000 { + compatible = "st,stm32mp25-sai"; + reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; + ranges = <0 0x402b0000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI3>; + clock-names = "pclk"; + interrupts = ; + resets = <&rcc SAI3_R>; + access-controllers = <&rifsc 51>; + status = "disabled"; + + sai3a: audio-controller@402b0004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI3>; + clock-names = "sai_ck"; + dmas = <&hpdma 77 0x43 0x21>; + status = "disabled"; + }; + + sai3b: audio-controller@502b0024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI3>; + clock-names = "sai_ck"; + dmas = <&hpdma 78 0x43 0x12>; + status = "disabled"; + }; + }; + + usart1: serial@40330000 { + compatible = "st,stm32h7-uart"; + reg = <0x40330000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART1>; + dmas = <&hpdma 9 0x20 0x10012>, + <&hpdma 10 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 31>; + status = "disabled"; + }; + + sai4: sai@40340000 { + compatible = "st,stm32mp25-sai"; + reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; + ranges = <0 0x40340000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI4>; + clock-names = "pclk"; + interrupts = ; + resets = <&rcc SAI4_R>; + access-controllers = <&rifsc 52>; + status = "disabled"; + + sai4a: audio-controller@40340004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI4>; + clock-names = "sai_ck"; + dmas = <&hpdma 79 0x63 0x21>; + status = "disabled"; + }; + + sai4b: audio-controller@40340024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI4>; + clock-names = "sai_ck"; + dmas = <&hpdma 80 0x43 0x12>; + status = "disabled"; + }; + }; + + uart7: serial@40370000 { + compatible = "st,stm32h7-uart"; + reg = <0x40370000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART7>; + dmas = <&hpdma 21 0x20 0x10012>, + <&hpdma 22 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 37>; + status = "disabled"; + }; + + rng: rng@42020000 { + compatible = "st,stm32mp25-rng"; + reg = <0x42020000 0x400>; + clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; + clock-names = "core", "bus"; + resets = <&rcc RNG_R>; + access-controllers = <&rifsc 92>; + status = "disabled"; + }; + + spi8: spi@46020000 { + compatible = "st,stm32mp25-spi"; + reg = <0x46020000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI8>; + resets = <&rcc SPI8_R>; + dmas = <&hpdma 171 0x20 0x3012>, + <&hpdma 172 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 29>; + status = "disabled"; + }; + + i2c8: i2c@46040000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x46040000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C8>; + resets = <&rcc I2C8_R>; + dmas = <&hpdma 168 0x20 0x3012>, + <&hpdma 169 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 48>; + status = "disabled"; + }; + + csi: csi@48020000 { + compatible = "st,stm32mp25-csi"; + reg = <0x48020000 0x2000>; + interrupts = ; + resets = <&rcc CSI_R>; + clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, + <&rcc CK_KER_CSIPHY>; + clock-names = "pclk", "txesc", "csi2phy"; + access-controllers = <&rifsc 86>; + status = "disabled"; + }; + + dcmipp: dcmipp@48030000 { + compatible = "st,stm32mp25-dcmipp"; + reg = <0x48030000 0x1000>; + interrupts = ; + resets = <&rcc DCMIPP_R>; + clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; + clock-names = "kclk", "mclk"; + access-controllers = <&rifsc 87>; + status = "disabled"; + }; + + sdmmc1: mmc@48220000 { + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + reg = <0x48220000 0x400>, <0x44230400 0x8>; + arm,primecell-periphid = <0x00353180>; + interrupts = ; + clocks = <&rcc CK_KER_SDMMC1 >; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + access-controllers = <&rifsc 76>; + status = "disabled"; + }; + + ethernet1: ethernet@482c0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482c0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH1_MAC>, + <&rcc CK_ETH1_TX>, + <&rcc CK_ETH1_RX>, + <&rcc CK_KER_ETH1PTP>, + <&rcc CK_ETH1_STP>, + <&rcc CK_KER_ETH1>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_1>; + snps,mtl-tx-config = <&mtl_tx_setup_1>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3000>; + access-controllers = <&rifsc 60>; + status = "disabled"; + + mtl_rx_setup_1: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_1: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; + }; + + bsec: efuse@44000000 { + compatible = "st,stm32mp25-bsec"; + reg = <0x44000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + part_number_otp@24 { + reg = <0x24 0x4>; + }; + + package_otp@1e8 { + reg = <0x1e8 0x1>; + bits = <0 3>; + }; + }; + + rcc: clock-controller@44200000 { + compatible = "st,stm32mp25-rcc"; + reg = <0x44200000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>, + <&scmi_clk CK_SCMI_HSE_DIV2>, + <&scmi_clk CK_SCMI_ICN_HS_MCU>, + <&scmi_clk CK_SCMI_ICN_LS_MCU>, + <&scmi_clk CK_SCMI_ICN_SDMMC>, + <&scmi_clk CK_SCMI_ICN_DDR>, + <&scmi_clk CK_SCMI_ICN_DISPLAY>, + <&scmi_clk CK_SCMI_ICN_HSL>, + <&scmi_clk CK_SCMI_ICN_NIC>, + <&scmi_clk CK_SCMI_ICN_VID>, + <&scmi_clk CK_SCMI_FLEXGEN_07>, + <&scmi_clk CK_SCMI_FLEXGEN_08>, + <&scmi_clk CK_SCMI_FLEXGEN_09>, + <&scmi_clk CK_SCMI_FLEXGEN_10>, + <&scmi_clk CK_SCMI_FLEXGEN_11>, + <&scmi_clk CK_SCMI_FLEXGEN_12>, + <&scmi_clk CK_SCMI_FLEXGEN_13>, + <&scmi_clk CK_SCMI_FLEXGEN_14>, + <&scmi_clk CK_SCMI_FLEXGEN_15>, + <&scmi_clk CK_SCMI_FLEXGEN_16>, + <&scmi_clk CK_SCMI_FLEXGEN_17>, + <&scmi_clk CK_SCMI_FLEXGEN_18>, + <&scmi_clk CK_SCMI_FLEXGEN_19>, + <&scmi_clk CK_SCMI_FLEXGEN_20>, + <&scmi_clk CK_SCMI_FLEXGEN_21>, + <&scmi_clk CK_SCMI_FLEXGEN_22>, + <&scmi_clk CK_SCMI_FLEXGEN_23>, + <&scmi_clk CK_SCMI_FLEXGEN_24>, + <&scmi_clk CK_SCMI_FLEXGEN_25>, + <&scmi_clk CK_SCMI_FLEXGEN_26>, + <&scmi_clk CK_SCMI_FLEXGEN_27>, + <&scmi_clk CK_SCMI_FLEXGEN_28>, + <&scmi_clk CK_SCMI_FLEXGEN_29>, + <&scmi_clk CK_SCMI_FLEXGEN_30>, + <&scmi_clk CK_SCMI_FLEXGEN_31>, + <&scmi_clk CK_SCMI_FLEXGEN_32>, + <&scmi_clk CK_SCMI_FLEXGEN_33>, + <&scmi_clk CK_SCMI_FLEXGEN_34>, + <&scmi_clk CK_SCMI_FLEXGEN_35>, + <&scmi_clk CK_SCMI_FLEXGEN_36>, + <&scmi_clk CK_SCMI_FLEXGEN_37>, + <&scmi_clk CK_SCMI_FLEXGEN_38>, + <&scmi_clk CK_SCMI_FLEXGEN_39>, + <&scmi_clk CK_SCMI_FLEXGEN_40>, + <&scmi_clk CK_SCMI_FLEXGEN_41>, + <&scmi_clk CK_SCMI_FLEXGEN_42>, + <&scmi_clk CK_SCMI_FLEXGEN_43>, + <&scmi_clk CK_SCMI_FLEXGEN_44>, + <&scmi_clk CK_SCMI_FLEXGEN_45>, + <&scmi_clk CK_SCMI_FLEXGEN_46>, + <&scmi_clk CK_SCMI_FLEXGEN_47>, + <&scmi_clk CK_SCMI_FLEXGEN_48>, + <&scmi_clk CK_SCMI_FLEXGEN_49>, + <&scmi_clk CK_SCMI_FLEXGEN_50>, + <&scmi_clk CK_SCMI_FLEXGEN_51>, + <&scmi_clk CK_SCMI_FLEXGEN_52>, + <&scmi_clk CK_SCMI_FLEXGEN_53>, + <&scmi_clk CK_SCMI_FLEXGEN_54>, + <&scmi_clk CK_SCMI_FLEXGEN_55>, + <&scmi_clk CK_SCMI_FLEXGEN_56>, + <&scmi_clk CK_SCMI_FLEXGEN_57>, + <&scmi_clk CK_SCMI_FLEXGEN_58>, + <&scmi_clk CK_SCMI_FLEXGEN_59>, + <&scmi_clk CK_SCMI_FLEXGEN_60>, + <&scmi_clk CK_SCMI_FLEXGEN_61>, + <&scmi_clk CK_SCMI_FLEXGEN_62>, + <&scmi_clk CK_SCMI_FLEXGEN_63>, + <&scmi_clk CK_SCMI_ICN_APB1>, + <&scmi_clk CK_SCMI_ICN_APB2>, + <&scmi_clk CK_SCMI_ICN_APB3>, + <&scmi_clk CK_SCMI_ICN_APB4>, + <&scmi_clk CK_SCMI_ICN_APBDBG>, + <&scmi_clk CK_SCMI_TIMG1>, + <&scmi_clk CK_SCMI_TIMG2>, + <&scmi_clk CK_SCMI_PLL3>, + <&clk_dsi_txbyte>; + access-controllers = <&rifsc 156>; + }; + + exti1: interrupt-controller@44220000 { + compatible = "st,stm32mp1-exti", "syscon"; + reg = <0x44220000 0x400>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = + <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ + <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ + <0>, + <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_80 */ + <0>, + <0>, + <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp23-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&exti1>; + st,syscfg = <&exti1 0x60 0xff>; + pins-are-numbered; + + gpioa: gpio@44240000 { + reg = <0x0 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOA>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + reg = <0x10000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOB>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + reg = <0x20000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOC>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + reg = <0x30000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOD>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + reg = <0x40000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOE>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + reg = <0x50000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOF>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + reg = <0x60000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOG>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + reg = <0x70000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOH>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + reg = <0x80000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOI>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + reg = <0x90000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOJ>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + reg = <0xa0000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOK>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + rtc: rtc@46000000 { + compatible = "st,stm32mp25-rtc"; + reg = <0x46000000 0x400>; + clocks = <&scmi_clk CK_SCMI_RTC>, + <&scmi_clk CK_SCMI_RTCCK>; + clock-names = "pclk", "rtc_ck"; + interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pinctrl_z: pinctrl@46200000 { + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&exti1>; + st,syscfg = <&exti1 0x60 0xff>; + pins-are-numbered; + + gpioz: gpio@46200000 { + reg = <0 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOZ>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + + exti2: interrupt-controller@46230000 { + compatible = "st,stm32mp1-exti", "syscon"; + reg = <0x46230000 0x400>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = + <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ + <0>, + <0>, + <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ + }; + + intc: interrupt-controller@4ac10000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x4ac10000 0x1000>, + <0x4ac20000 0x2000>, + <0x4ac40000 0x2000>, + <0x4ac60000 0x2000>; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp233.dtsi b/arch/arm64/boot/dts/st/stm32mp233.dtsi new file mode 100644 index 000000000000..78f4059fca5d --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp233.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp231.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + reg = <1>; + device_type = "cpu"; + enable-method = "psci"; + power-domains = <&cpu1_pd>; + power-domain-names = "psci"; + }; + }; + + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + psci { + cpu1_pd: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + }; + }; + + timer { + interrupts = , + , + , + ; + }; +}; + +&optee { + interrupts = ; +}; + +&rifsc { + ethernet2: ethernet@482d0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482d0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH2_MAC>, + <&rcc CK_ETH2_TX>, + <&rcc CK_ETH2_RX>, + <&rcc CK_KER_ETH2PTP>, + <&rcc CK_ETH2_STP>, + <&rcc CK_KER_ETH2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_2>; + snps,mtl-tx-config = <&mtl_tx_setup_2>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3400>; + access-controllers = <&rifsc 61>; + status = "disabled"; + + mtl_rx_setup_2: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_2: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp235.dtsi b/arch/arm64/boot/dts/st/stm32mp235.dtsi new file mode 100644 index 000000000000..2719c088dd59 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp235.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp233.dtsi" + +&rifsc { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = ; + clocks = <&rcc CK_BUS_VDEC>; + access-controllers = <&rifsc 89>; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi new file mode 100644 index 000000000000..e33b00b424e1 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp23xf.dtsi b/arch/arm64/boot/dts/st/stm32mp23xf.dtsi new file mode 100644 index 000000000000..e33b00b424e1 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp23xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; -- cgit From 5fbe1ead4c59954a149e0bcb758a69d07140a799 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 25 Feb 2025 09:54:09 +0100 Subject: dt-bindings: stm32: document stm32mp235f-dk board Add new entry for stm32mp235-dk board. Signed-off-by: Amelie Delaunay Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-6-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 456648e2d1e7..33e794b54bc1 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -191,6 +191,12 @@ properties: - st,stm32mp257f-ev1 - const: st,stm32mp257 + - description: ST STM32MP235 based Boards + items: + - enum: + - st,stm32mp235f-dk + - const: st,stm32mp235 + additionalProperties: true ... -- cgit From c57a222ab80168ff60a2cd1903dc0585faae5c61 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 25 Feb 2025 09:54:10 +0100 Subject: arm64: dts: st: add stm32mp235f-dk board support Add STM32MP235F Discovery Kit board support. It embeds a STM32MP235FAK SoC, with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ... Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-7-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/Makefile | 1 + arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 113 ++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp235f-dk.dts diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile index 0cc12f2b1dfe..063641522069 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_STM32) += \ + stm32mp235f-dk.dtb \ stm32mp257f-dk.dtb \ stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts new file mode 100644 index 000000000000..04d1b434c433 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include +#include +#include "stm32mp235.dtsi" +#include "stm32mp23xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP235F-DK Discovery Board"; + compatible = "st,stm32mp235f-dk", "st,stm32mp235"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = ; + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + }; + + button-user-2 { + label = "User-2"; + linux,code = ; + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vdd_sdcard: regulator@23 { + reg = ; + regulator-name = "vdd_sdcard"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; -- cgit From 7a57b1bb1afbfbb21d0445f68a032c8591b7c9c1 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Tue, 25 Feb 2025 09:54:11 +0100 Subject: arm64: dts: st: introduce stm32mp21 SoCs family STM32MP21 family is composed of 3 SoCs defined as following: -STM32MP211: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP213: STM32MP211 + a second ETH, CAN-FD. -STM32MP215: STM32MP213 + Display and CSI2. A second diversity layer exists for security features/ A35 frequency: -STM32MP21xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-8-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp211.dtsi | 128 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp213.dtsi | 9 +++ arch/arm64/boot/dts/st/stm32mp215.dtsi | 9 +++ arch/arm64/boot/dts/st/stm32mp21xc.dtsi | 8 ++ arch/arm64/boot/dts/st/stm32mp21xf.dtsi | 8 ++ 5 files changed, 162 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp211.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp213.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp215.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp21xc.dtsi create mode 100644 arch/arm64/boot/dts/st/stm32mp21xf.dtsi diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi new file mode 100644 index 000000000000..6dd1377f3e1d --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + reg = <0>; + device_type = "cpu"; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + status = "disabled"; + }; + + ck_flexgen_08: clock-64000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <64000000>; + }; + + ck_flexgen_51: clock-200000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + arm,no-tick-in-suspend; + }; + + soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x0 0x80000000>; + dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <2>; + + rifsc: bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x0 0x1000>; + ranges; + dma-ranges; + #address-cells = <1>; + #size-cells = <2>; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x0 0x400>; + interrupts = ; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp21-syscfg", "syscon"; + reg = <0x44230000 0x0 0x10000>; + }; + + intc: interrupt-controller@4ac10000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x4ac10000 0x0 0x1000>, + <0x4ac20000 0x0 0x2000>, + <0x4ac40000 0x0 0x2000>, + <0x4ac60000 0x0 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + }; + }; +}; diff --git a/arch/arm64/boot/dts/st/stm32mp213.dtsi b/arch/arm64/boot/dts/st/stm32mp213.dtsi new file mode 100644 index 000000000000..fdd2dc432edd --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp213.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp211.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp215.dtsi b/arch/arm64/boot/dts/st/stm32mp215.dtsi new file mode 100644 index 000000000000..a7df77f928c5 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp215.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp213.dtsi" + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp21xc.dtsi b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi new file mode 100644 index 000000000000..e33b00b424e1 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm64/boot/dts/st/stm32mp21xf.dtsi b/arch/arm64/boot/dts/st/stm32mp21xf.dtsi new file mode 100644 index 000000000000..e33b00b424e1 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp21xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; -- cgit From 1a09f577aa65860da3dbfa29388e26ff970af49a Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 25 Feb 2025 09:54:12 +0100 Subject: dt-bindings: stm32: document stm32mp215f-dk board Add new entry for stm32mp215-dk board. Signed-off-by: Amelie Delaunay Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-9-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 33e794b54bc1..5fee2f38ff25 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -197,6 +197,12 @@ properties: - st,stm32mp235f-dk - const: st,stm32mp235 + - description: ST STM32MP215 based Boards + items: + - enum: + - st,stm32mp215f-dk + - const: st,stm32mp215 + additionalProperties: true ... -- cgit From 65954899a157832f68536b488194cf698248a26e Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 25 Feb 2025 09:54:13 +0100 Subject: arm64: dts: st: add stm32mp215f-dk board support Add STM32MP215F Discovery Kit board support. It embeds a STM32MP235FAN SoC, with 2GB of LPDDR4, 1*USB2 peripheral bus powered typeC, 1*ETH, wifi/BT combo, LCD 18bit connector, CSI camera connector, ... Signed-off-by: Amelie Delaunay Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-10-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/Makefile | 1 + arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 49 +++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp215f-dk.dts diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile index 063641522069..63908113ae36 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_STM32) += \ + stm32mp215f-dk.dtb \ stm32mp235f-dk.dtb \ stm32mp257f-dk.dtb \ stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts new file mode 100644 index 000000000000..7bdaeaa5ab0f --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp215.dtsi" +#include "stm32mp21xf.dtsi" + +/ { + model = "STMicroelectronics STM32MP215F-DK Discovery Board"; + compatible = "st,stm32mp215f-dk", "st,stm32mp215"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; -- cgit