From 4c4e17f2701316e0cac16e19366056f464feded5 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 2 Jul 2025 17:25:59 +0200 Subject: clk: amlogic: naming consistency alignment Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-1-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-2-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-3-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-4-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-5-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-6-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-7-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-8-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-9-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-10-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-11-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-12-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-13-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-14-e163c9a1fc21@baylibre.com Reviewed-by: Chuan Liu # For c3 and s4 [jbrunet: squashed all naming alignment changes together] Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8-ddr.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) (limited to 'drivers/clk/meson/meson8-ddr.c') diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c index 1975fc3987e2..6a9efde9b570 100644 --- a/drivers/clk/meson/meson8-ddr.c +++ b/drivers/clk/meson/meson8-ddr.c @@ -12,6 +12,7 @@ #include "clk-regmap.h" #include "clk-pll.h" +#include "meson-clkc-utils.h" #define AM_DDR_PLL_CNTL 0x00 #define AM_DDR_PLL_CNTL1 0x04 @@ -77,15 +78,17 @@ static struct clk_regmap meson8_ddr_pll = { }, }; -static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = { - .hws = { - [DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw, - [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw, - }, - .num = 2, +static struct clk_hw *meson8_ddr_hw_clks[] = { + [DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw, + [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw, +}; + +static struct meson_clk_hw_data meson8_ddr_clks = { + .hws = meson8_ddr_hw_clks, + .num = ARRAY_SIZE(meson8_ddr_hw_clks), }; -static const struct regmap_config meson8_ddr_clkc_regmap_config = { +static const struct regmap_config meson8_ddr_regmap_cfg = { .reg_bits = 8, .val_bits = 32, .reg_stride = 4, @@ -104,13 +107,13 @@ static int meson8_ddr_clkc_probe(struct platform_device *pdev) return PTR_ERR(base); regmap = devm_regmap_init_mmio(&pdev->dev, base, - &meson8_ddr_clkc_regmap_config); + &meson8_ddr_regmap_cfg); if (IS_ERR(regmap)) return PTR_ERR(regmap); /* Register all clks */ - for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) { - hw = meson8_ddr_clk_hw_onecell_data.hws[i]; + for (i = 0; i < meson8_ddr_clks.num; i++) { + hw = meson8_ddr_clks.hws[i]; ret = devm_clk_hw_register(&pdev->dev, hw); if (ret) { @@ -119,8 +122,8 @@ static int meson8_ddr_clkc_probe(struct platform_device *pdev) } } - return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, - &meson8_ddr_clk_hw_onecell_data); + return devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get, + &meson8_ddr_clks); } static const struct of_device_id meson8_ddr_clkc_match_table[] = { -- cgit From d7c001bd76b7f7e6c05f615d472b5daadc87b434 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:28 +0200 Subject: clk: amlogic: use probe helper in mmio based controllers Factorize the probe function of the mmio based amlogic clock controllers using the newly introduced probe helper. This removes a fair amount of duplicated code. Reviewed-by: Chuan Liu Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-3-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8-ddr.c | 57 ++++++++++-------------------------------- 1 file changed, 13 insertions(+), 44 deletions(-) (limited to 'drivers/clk/meson/meson8-ddr.c') diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c index 6a9efde9b570..0f93774f7371 100644 --- a/drivers/clk/meson/meson8-ddr.c +++ b/drivers/clk/meson/meson8-ddr.c @@ -83,57 +83,26 @@ static struct clk_hw *meson8_ddr_hw_clks[] = { [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw, }; -static struct meson_clk_hw_data meson8_ddr_clks = { - .hws = meson8_ddr_hw_clks, - .num = ARRAY_SIZE(meson8_ddr_hw_clks), -}; - -static const struct regmap_config meson8_ddr_regmap_cfg = { - .reg_bits = 8, - .val_bits = 32, - .reg_stride = 4, - .max_register = DDR_CLK_STS, +static const struct meson_clkc_data meson8_ddr_clkc_data = { + .hw_clks = { + .hws = meson8_ddr_hw_clks, + .num = ARRAY_SIZE(meson8_ddr_hw_clks), + }, }; -static int meson8_ddr_clkc_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - void __iomem *base; - struct clk_hw *hw; - int ret, i; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - regmap = devm_regmap_init_mmio(&pdev->dev, base, - &meson8_ddr_regmap_cfg); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* Register all clks */ - for (i = 0; i < meson8_ddr_clks.num; i++) { - hw = meson8_ddr_clks.hws[i]; - - ret = devm_clk_hw_register(&pdev->dev, hw); - if (ret) { - dev_err(&pdev->dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get, - &meson8_ddr_clks); -} - static const struct of_device_id meson8_ddr_clkc_match_table[] = { - { .compatible = "amlogic,meson8-ddr-clkc" }, - { .compatible = "amlogic,meson8b-ddr-clkc" }, + { + .compatible = "amlogic,meson8-ddr-clkc", + .data = &meson8_ddr_clkc_data, + }, { + .compatible = "amlogic,meson8b-ddr-clkc", + .data = &meson8_ddr_clkc_data, + }, { /* sentinel */ } }; static struct platform_driver meson8_ddr_clkc_driver = { - .probe = meson8_ddr_clkc_probe, + .probe = meson_clkc_mmio_probe, .driver = { .name = "meson8-ddr-clkc", .of_match_table = meson8_ddr_clkc_match_table, -- cgit