diff options
| author | Gerald Lejeune <gerald.lejeune@st.com> | 2016-03-22 11:11:46 +0100 |
|---|---|---|
| committer | Gerald Lejeune <gerald.lejeune@st.com> | 2016-03-30 17:32:13 +0200 |
| commit | 6b836cf98892ad50a8bafa3fdf4e1be894601fa4 (patch) | |
| tree | 50d8c94f397f1af668a286fd91d6a23b022d4ffd | |
| parent | 4ca5753576933d8b1f1a8244331f22b9c09e2bdd (diff) | |
Add ISR_EL1 to crash report
Bring ISR bits definition as a mnemonic for troublershooters as well.
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
| -rw-r--r-- | bl31/aarch64/crash_reporting.S | 4 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 5 |
2 files changed, 8 insertions, 1 deletions
diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S index ff915728..b22ce71e 100644 --- a/bl31/aarch64/crash_reporting.S +++ b/bl31/aarch64/crash_reporting.S @@ -70,7 +70,8 @@ non_el3_sys_regs: "tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\ "mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\ "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\ - "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0", "" + "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0",\ + "isr_el1", "" panic_msg: .asciz "PANIC in EL3 at x30 = 0x" @@ -338,6 +339,7 @@ func do_crash_reporting mrs x8, cntkctl_el1 mrs x9, fpexc32_el2 mrs x10, sp_el0 + mrs x11, isr_el1 bl str_in_crash_buf_print /* Get the cpu specific registers to report */ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index a9b2dbb2..f9b8ed6a 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -186,6 +186,11 @@ #define HCR_IMO_BIT (1 << 4) #define HCR_FMO_BIT (1 << 3) +/* ISR definitions */ +#define ISR_A_SHIFT 8 +#define ISR_I_SHIFT 7 +#define ISR_F_SHIFT 6 + /* CNTHCTL_EL2 definitions */ #define EVNTEN_BIT (1 << 2) #define EL1PCEN_BIT (1 << 1) |