diff options
author | danh-arm <dan.handley@arm.com> | 2015-12-09 15:16:08 +0000 |
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committer | danh-arm <dan.handley@arm.com> | 2015-12-09 15:16:08 +0000 |
commit | e4d3c51ddd5525f5c0bf8eeab450e749326f538e (patch) | |
tree | d697ee2c0dba3417499ee13c2314b9601d457bc4 | |
parent | 7e473eaefca8a46106f9e5c8c186511af228baac (diff) | |
parent | 85d80e557803a8f3e966a0b58dc036aa8c33f153 (diff) |
Merge pull request #460 from sandrine-bailleux/sb/init-vttbrel2-vmid
Initialize VTTBR_EL2 when bypassing EL2
-rw-r--r-- | bl31/context_mgmt.c | 8 | ||||
-rw-r--r-- | include/lib/aarch64/arch_helpers.h | 2 |
2 files changed, 10 insertions, 0 deletions
diff --git a/bl31/context_mgmt.c b/bl31/context_mgmt.c index 6d405343..2b619aaa 100644 --- a/bl31/context_mgmt.c +++ b/bl31/context_mgmt.c @@ -330,6 +330,14 @@ void cm_prepare_el3_exit(uint32_t security_state) /* Set VPIDR, VMPIDR to match MIDR, MPIDR */ write_vpidr_el2(read_midr_el1()); write_vmpidr_el2(read_mpidr_el1()); + + /* + * Reset VTTBR_EL2. + * Needed because cache maintenance operations depend on + * the VMID even when non-secure EL1&0 stage 2 address + * translation are disabled. + */ + write_vttbr_el2(0); } } diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h index 43c6917e..067b8302 100644 --- a/include/lib/aarch64/arch_helpers.h +++ b/include/lib/aarch64/arch_helpers.h @@ -270,6 +270,8 @@ DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) +DEFINE_SYSREG_RW_FUNCS(vttbr_el2) + DEFINE_SYSREG_RW_FUNCS(cptr_el2) DEFINE_SYSREG_RW_FUNCS(cptr_el3) |