diff options
author | danh-arm <dan.handley@arm.com> | 2014-07-28 14:27:25 +0100 |
---|---|---|
committer | danh-arm <dan.handley@arm.com> | 2014-07-28 14:27:25 +0100 |
commit | 9fd412770f1a7d9c68731a21f157a326db3c5725 (patch) | |
tree | 745886c81021ef1cd3bffa5ef131b7564812d179 /bl31 | |
parent | d9b1128b438748ce7ccfd33804321da2eed6fcfd (diff) | |
parent | ec3c10039bdc2c1468a8ba95fbbe9de78628eea5 (diff) |
Merge pull request #170 from achingupta/ag/tf-issues#226
Simplify management of SCTLR_EL3 and SCTLR_EL1
Diffstat (limited to 'bl31')
-rw-r--r-- | bl31/aarch64/bl31_arch_setup.c | 14 | ||||
-rw-r--r-- | bl31/aarch64/bl31_entrypoint.S | 20 |
2 files changed, 17 insertions, 17 deletions
diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c index e0382b33..f67881e6 100644 --- a/bl31/aarch64/bl31_arch_setup.c +++ b/bl31/aarch64/bl31_arch_setup.c @@ -42,21 +42,12 @@ ******************************************************************************/ void bl31_arch_setup(void) { - unsigned long tmp_reg = 0; - uint64_t counter_freq; - - /* Enable alignment checks */ - tmp_reg = read_sctlr_el3(); - tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); - write_sctlr_el3(tmp_reg); - /* * Route external abort and SError interrupts to EL3 * other SCR bits will be configured before exiting to a lower exception * level */ - tmp_reg = SCR_RES1_BITS | SCR_EA_BIT; - write_scr(tmp_reg); + write_scr_el3(SCR_RES1_BITS | SCR_EA_BIT); /* * Enable SError and Debug exceptions @@ -65,6 +56,5 @@ void bl31_arch_setup(void) enable_debug_exceptions(); /* Program the counter frequency */ - counter_freq = plat_get_syscnt_freq(); - write_cntfrq_el0(counter_freq); + write_cntfrq_el0(plat_get_syscnt_freq()); } diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 10239837..69d22436 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -52,6 +52,15 @@ func bl31_entrypoint mov x20, x0 mov x21, x1 #else + /* --------------------------------------------- + * Set the CPU endianness before doing anything + * that might involve memory reads or writes. + * --------------------------------------------- + */ + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb /* ----------------------------------------------------- * Perform any processor specific actions upon reset @@ -61,14 +70,15 @@ func bl31_entrypoint */ bl cpu_reset_handler #endif - /* --------------------------------------------- - * Enable the instruction cache. + * Enable the instruction cache, stack pointer + * and data access alignment checks * --------------------------------------------- */ - mrs x1, sctlr_el3 - orr x1, x1, #SCTLR_I_BIT - msr sctlr_el3, x1 + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el3 + orr x0, x0, x1 + msr sctlr_el3, x0 isb /* --------------------------------------------- |