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| author | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-06-04 21:10:52 +0100 |
|---|---|---|
| committer | Andrew Thoelke <andrew.thoelke@arm.com> | 2014-06-23 14:55:44 +0100 |
| commit | 167a935733a6e3e412b8ed6a60034d0d84895f2e (patch) | |
| tree | c443557e8fe8ff50628567aa6ebfc11f6fc9f6dd /include/lib/aarch64/arch.h | |
| parent | 5298f2cb98b9bdc18eb2f25cd28180ba7fd000d8 (diff) | |
Initialise CPU contexts from entry_point_info
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
* The first uses entry_point_info to initialize the relevant
cpu_context for first entry into a lower exception level on a CPU
* The second populates the EL1 and EL2 system registers as needed
from the cpu_context to ensure correct entry into the lower EL
This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).
In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.
Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
Diffstat (limited to 'include/lib/aarch64/arch.h')
| -rw-r--r-- | include/lib/aarch64/arch.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 0bfbd66c..5dc488bb 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -167,6 +167,7 @@ #define HCR_FMO_BIT (1 << 3) /* CNTHCTL_EL2 definitions */ +#define EVNTEN_BIT (1 << 2) #define EL1PCEN_BIT (1 << 1) #define EL1PCTEN_BIT (1 << 0) |