diff options
| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-04-14 14:04:48 +0100 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-04-21 12:59:59 +0100 |
| commit | a8b1c769361c63a69fd73afe37bb4799446ec045 (patch) | |
| tree | 5d36f48e5d726fe162021a28021befe44c76f8fc /lib | |
| parent | df22d602b6b1ee00a0cb31e88bb63e7152f2cf6a (diff) | |
Add support for Cortex-A57 erratum 828024 workaround
Change-Id: I632a8c5bb517ff89c69268e865be33101059be7d
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 35 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
2 files changed, 43 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index d992f98b..ec32ce78 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -193,6 +193,37 @@ apply_826974: ret endfunc errata_a57_826974_wa + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #828024. + * This applies only to revision <= r1p1 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_828024_wa + /* + * Compare x0 against revision r1p1 + */ + cmp x0, #0x11 + b.ls apply_828024 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_828024: + mrs x1, CPUACTLR_EL1 + /* + * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 + * instructions here because the resulting bitmask doesn't fit in a + * 16-bit value so it cannot be encoded in a single instruction. + */ + orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA + orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_828024_wa /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. @@ -232,6 +263,10 @@ func cortex_a57_reset_func bl errata_a57_826974_wa #endif +#if ERRATA_A57_828024 + mov x0, x15 + bl errata_a57_828024_wa +#endif /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 3ea462bb..7d9f2b72 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -78,6 +78,10 @@ ERRATA_A57_813420 ?=0 # only to revision <= r1p1 of the Cortex A57 cpu. ERRATA_A57_826974 ?=0 +# Flag to apply erratum 828024 workaround during reset. This erratum applies +# only to revision <= r1p1 of the Cortex A57 cpu. +ERRATA_A57_828024 ?=0 + # Process ERRATA_A53_826319 flag $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) @@ -97,3 +101,7 @@ $(eval $(call add_define,ERRATA_A57_813420)) # Process ERRATA_A57_826974 flag $(eval $(call assert_boolean,ERRATA_A57_826974)) $(eval $(call add_define,ERRATA_A57_826974)) + +# Process ERRATA_A57_828024 flag +$(eval $(call assert_boolean,ERRATA_A57_828024)) +$(eval $(call add_define,ERRATA_A57_828024)) |