diff options
| -rw-r--r-- | plat/marvell/a8k/common/plat_ble_setup.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c index b681e2e9..17dd5142 100644 --- a/plat/marvell/a8k/common/plat_ble_setup.c +++ b/plat/marvell/a8k/common/plat_ble_setup.c @@ -143,6 +143,17 @@ #define EFUSE_AP_LD0_CLUSTER_DOWN_OFFS 4 +/* Return the AP revision of the chip */ +static unsigned int ble_get_ap_type(void) +{ + unsigned int chip_rev_id; + + chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG); + chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> GWD_IIDR2_CHIP_ID_OFFSET); + + return chip_rev_id; +} + /****************************************************************************** * The routine allows to save the CCU and IO windows configuration during DRAM * setup and restore them afterwards before exiting the BLE stage. @@ -513,7 +524,6 @@ static void aro_to_pll(void) int ble_plat_setup(int *skip) { int ret; - unsigned int chip_rev_id; /* Power down unused CPUs */ plat_marvell_early_cpu_powerdown(); @@ -540,11 +550,8 @@ int ble_plat_setup(int *skip) /* Setup AVS */ ble_plat_svc_config(); - chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG); - chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> GWD_IIDR2_CHIP_ID_OFFSET); - /* work with PLL clock driver in AP807 */ - if (chip_rev_id == CHIP_ID_AP807) + if (ble_get_ap_type() == CHIP_ID_AP807) aro_to_pll(); #if ARO_ENABLE |