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-rw-r--r--include/bl31/services/psci.h3
-rw-r--r--include/lib/bakery_lock.h32
-rw-r--r--include/plat/arm/common/arm_def.h14
-rw-r--r--include/plat/arm/common/plat_arm.h56
4 files changed, 33 insertions, 72 deletions
diff --git a/include/bl31/services/psci.h b/include/bl31/services/psci.h
index 30a53ca2..6298a404 100644
--- a/include/bl31/services/psci.h
+++ b/include/bl31/services/psci.h
@@ -251,9 +251,6 @@ typedef struct psci_cpu_data {
/* The local power state of this CPU */
plat_local_state_t local_state;
-#if !USE_COHERENT_MEM
- bakery_info_t pcpu_bakery_info[PSCI_NUM_NON_CPU_PWR_DOMAINS];
-#endif
} psci_cpu_data_t;
/*******************************************************************************
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h
index 2e1afa21..86adb9cb 100644
--- a/include/lib/bakery_lock.h
+++ b/include/lib/bakery_lock.h
@@ -56,6 +56,11 @@
* External bakery lock interface.
****************************************************************************/
#if USE_COHERENT_MEM
+/*
+ * Bakery locks are stored in coherent memory
+ *
+ * Each lock's data is contiguous and fully allocated by the compiler
+ */
typedef struct bakery_lock {
/*
@@ -67,12 +72,15 @@ typedef struct bakery_lock {
volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
} bakery_lock_t;
-void bakery_lock_init(bakery_lock_t *bakery);
-void bakery_lock_get(bakery_lock_t *bakery);
-void bakery_lock_release(bakery_lock_t *bakery);
-int bakery_lock_try(bakery_lock_t *bakery);
-
#else
+/*
+ * Bakery locks are stored in normal .bss memory
+ *
+ * Each lock's data is spread across multiple cache lines, one per CPU,
+ * but multiple locks can share the same cache line.
+ * The compiler will allocate enough memory for one CPU's bakery locks,
+ * the remaining cache lines are allocated by the linker script
+ */
typedef struct bakery_info {
/*
@@ -84,9 +92,19 @@ typedef struct bakery_info {
volatile uint16_t lock_data;
} bakery_info_t;
-void bakery_lock_get(unsigned int id, unsigned int offset);
-void bakery_lock_release(unsigned int id, unsigned int offset);
+typedef bakery_info_t bakery_lock_t;
#endif /* __USE_COHERENT_MEM__ */
+
+inline void bakery_lock_init(bakery_lock_t *bakery) {}
+void bakery_lock_get(bakery_lock_t *bakery);
+void bakery_lock_release(bakery_lock_t *bakery);
+
+#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name \
+ __attribute__ ((section("bakery_lock")))
+
+#define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name
+
+
#endif /* __ASSEMBLY__ */
#endif /* __BAKERY_LOCK_H__ */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index a22e64ab..c236970a 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -206,14 +206,6 @@
*/
#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
-#if !USE_COHERENT_MEM
-/*
- * Size of the per-cpu data in bytes that should be reserved in the generic
- * per-cpu data structure for the ARM platform port.
- */
-#define PLAT_PCPU_DATA_SIZE 2
-#endif
-
/*******************************************************************************
* BL1 specific defines.
@@ -301,4 +293,10 @@
#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
+/*
+ * One cache line needed for bakery locks on ARM platforms
+ */
+#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
+
+
#endif /* __ARM_DEF_H__ */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 823212cb..ad41f4f0 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -71,14 +71,11 @@ void arm_configure_mmu_el3(unsigned long total_base,
);
#if IMAGE_BL31
-#if USE_COHERENT_MEM
-
/*
* Use this macro to instantiate lock before it is used in below
* arm_lock_xxx() macros
*/
-#define ARM_INSTANTIATE_LOCK bakery_lock_t arm_lock \
- __attribute__ ((section("tzfw_coherent_mem")));
+#define ARM_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_lock);
/*
* These are wrapper macros to the Coherent Memory Bakery Lock API.
@@ -89,58 +86,9 @@ void arm_configure_mmu_el3(unsigned long total_base,
#else
-/*******************************************************************************
- * Constants to specify how many bakery locks this platform implements. These
- * are used if the platform chooses not to use coherent memory for bakery lock
- * data structures.
- ******************************************************************************/
-#define ARM_MAX_BAKERIES 1
-#define ARM_PWRC_BAKERY_ID 0
-
-/* Empty definition */
-#define ARM_INSTANTIATE_LOCK
-
-/*******************************************************************************
- * Definition of structure which holds platform specific per-cpu data. Currently
- * it holds only the bakery lock information for each cpu.
- ******************************************************************************/
-typedef struct arm_cpu_data {
- bakery_info_t pcpu_bakery_info[ARM_MAX_BAKERIES];
-} arm_cpu_data_t;
-
-/* Macro to define the offset of bakery_info_t in arm_cpu_data_t */
-#define ARM_CPU_DATA_LOCK_OFFSET __builtin_offsetof\
- (arm_cpu_data_t, pcpu_bakery_info)
-
-
-/*******************************************************************************
- * Helper macros for bakery lock api when using the above arm_cpu_data_t for
- * bakery lock data structures. It assumes that the bakery_info is at the
- * beginning of the platform specific per-cpu data.
- ******************************************************************************/
-#define arm_lock_init() /* No init required */
-#define arm_lock_get() bakery_lock_get(ARM_PWRC_BAKERY_ID, \
- CPU_DATA_PLAT_PCPU_OFFSET + \
- ARM_CPU_DATA_LOCK_OFFSET)
-#define arm_lock_release() bakery_lock_release(ARM_PWRC_BAKERY_ID, \
- CPU_DATA_PLAT_PCPU_OFFSET + \
- ARM_CPU_DATA_LOCK_OFFSET)
-
/*
- * Ensure that the size of the platform specific per-cpu data structure and
- * the size of the memory allocated in generic per-cpu data for the platform
- * are the same.
+ * Empty macros for all other BL stages other than BL3-1
*/
-CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(arm_cpu_data_t),
- arm_pcpu_data_size_mismatch);
-
-#endif /* USE_COHERENT_MEM */
-
-#else
-
-/*
-* Dummy macros for all other BL stages other than BL3-1
-*/
#define ARM_INSTANTIATE_LOCK
#define arm_lock_init()
#define arm_lock_get()