diff options
Diffstat (limited to 'plat/marvell/a8k/a70x0_cust/board/dram_port.c')
-rw-r--r-- | plat/marvell/a8k/a70x0_cust/board/dram_port.c | 138 |
1 files changed, 138 insertions, 0 deletions
diff --git a/plat/marvell/a8k/a70x0_cust/board/dram_port.c b/plat/marvell/a8k/a70x0_cust/board/dram_port.c new file mode 100644 index 00000000..e235d9a5 --- /dev/null +++ b/plat/marvell/a8k/a70x0_cust/board/dram_port.c @@ -0,0 +1,138 @@ +/* + * *************************************************************************** + * Copyright (C) 2016 Marvell International Ltd. + * *************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of Marvell nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *************************************************************************** + */ + +#include <arch_helpers.h> +#include <plat_marvell.h> +#include <debug.h> +#include <dram_if.h> +#include <plat_def.h> +#include <mmio.h> +#include <a8k_i2c.h> + +#include <mv_ddr_atf_wrapper.h> +#include <apn806/mv_ddr_apn806.h> +#include <apn806/mv_ddr_apn806_topology.h> +#include <ddr3_topology_def.h> + +struct dram_config dram_cfg; + +/* + * This struct provides the DRAM training code with + * the appropriate board DRAM configuration + */ +static struct mv_ddr_topology_map board_topology_map = { +/* FIXME: Customer board with 2CS 4Gb x8 devices of Micron 2133P */ + DEBUG_LEVEL_ERROR, + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ + { { { {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0} }, + SPEED_BIN_DDR_2133P, /* speed_bin */ + MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */ + MV_DDR_DIE_CAP_4GBIT, /* die capacity */ + DDR_FREQ_SAR, /* frequency */ + 0, 0, /* cas_l, cas_wl */ + MV_DDR_TEMP_LOW} }, /* temperature */ + MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */ + MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + { {0} }, /* raw spd data */ + {0} /* timing parameters */ +}; + +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) +{ + /* Return the board topology as defined in the board code */ + return &board_topology_map; +} + +struct dram_config *mv_ddr_dram_config_get(void) +{ + /* Return dram configuration as defined in the board code */ + return &dram_cfg; +} + +static void mpp_config(void) +{ + uint32_t val; + + /* Enable CP0 I2C MPPs (MPP: 37-38) */ + val = mmio_read_32(MVEBU_CP_MPP_REGS(0, 4)); + mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), val | 0x2200000); +} + +/* + * This function may modify the default DRAM parameters + * based on information recieved from SPD or bootloader + * configuration located on non volatile storage + */ +int update_dram_info(struct dram_config *cfg) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + + NOTICE("Gathering DRAM information\n"); + + if (tm->cfg_src == MV_DDR_CFG_SPD) { + /* configure mpps for i2c functionality */ + mpp_config(); + /* initialize ap i2c */ + i2c_init((void *)MVEBU_CP0_I2C_BASE); + /* + * Dummy read to the SPD chip memory page selector. + * It is needed for for selecting the SPD memory page 0 + * prior to accessing the DRAM configuration data + */ + i2c_read(CP0_I2C_SPD_P0_ADDR, 0x0, 2, + tm->spd_data.all_bytes, 1); + /* read data from spd */ + i2c_read(CP0_I2C_SPD_ADDR, 0x0, 2, tm->spd_data.all_bytes, + sizeof(tm->spd_data.all_bytes)); + } + + return 0; +} + +void *plat_get_dram_data(void) +{ + /* Update DRAM for dynamic platforms */ + update_dram_info(&dram_cfg); + + return &dram_cfg; +} |