diff options
Diffstat (limited to 'plat/marvell/a8k/a80x0_cust')
| -rw-r--r-- | plat/marvell/a8k/a80x0_cust/board/dram_port.c | 150 | ||||
| -rw-r--r-- | plat/marvell/a8k/a80x0_cust/board/marvell_plat_config.c | 198 | ||||
| -rw-r--r-- | plat/marvell/a8k/a80x0_cust/plat_def.h | 44 | ||||
| -rw-r--r-- | plat/marvell/a8k/a80x0_cust/platform.mk | 35 |
4 files changed, 427 insertions, 0 deletions
diff --git a/plat/marvell/a8k/a80x0_cust/board/dram_port.c b/plat/marvell/a8k/a80x0_cust/board/dram_port.c new file mode 100644 index 00000000..01cfdc92 --- /dev/null +++ b/plat/marvell/a8k/a80x0_cust/board/dram_port.c @@ -0,0 +1,150 @@ +/* + * *************************************************************************** + * Copyright (C) 2016 Marvell International Ltd. + * *************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of Marvell nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *************************************************************************** + */ + +#include <arch_helpers.h> +#include <plat_marvell.h> +#include <debug.h> +#include <dram_if.h> +#include <plat_def.h> +#include <mmio.h> +#include <a8k_i2c.h> + +#include <mv_ddr_atf_wrapper.h> +#include <apn806/mv_ddr_apn806.h> +#include <apn806/mv_ddr_apn806_topology.h> +#include <ddr3_topology_def.h> + +#define MVEBU_CP_MPP_CTRL37_OFFS 20 +#define MVEBU_CP_MPP_CTRL38_OFFS 24 +#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2 +#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2 + +#define MVEBU_MPP_CTRL_MASK 0xf + +struct dram_config dram_cfg; + +/* + * This struct provides the DRAM training code with + * the appropriate board DRAM configuration + */ +static struct mv_ddr_topology_map board_topology_map = { + /* Board with 1CS 8Gb x4 devices of Micron 2400T */ + DEBUG_LEVEL_ERROR, + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ + { { { {0x1, 0x0, 0, 0}, /* FIXME: change the cs mask for all 64 bit */ + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0} }, + /* TODO: double check if the speed bin is 2400S */ + SPEED_BIN_DDR_2400S, /* speed_bin */ + MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */ + MV_DDR_DIE_CAP_8GBIT, /* die capacity */ + DDR_FREQ_SAR, /* frequency */ + 0, 0, /* cas_l, cas_wl */ + MV_DDR_TEMP_LOW} }, /* temperature */ + MV_DDR_64BIT_BUS_MASK, /* subphys mask */ + MV_DDR_CFG_SPD, /* ddr configuration data source */ + { {0} }, /* raw spd data */ + {0} /* timing parameters */ +}; + +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) +{ + /* Return the board topology as defined in the board code */ + return &board_topology_map; +} + +struct dram_config *mv_ddr_dram_config_get(void) +{ + /* Return dram configuration as defined in the board code */ + return &dram_cfg; +} + +static void mpp_config(void) +{ + uint32_t val; + uintptr_t reg = MVEBU_CP_MPP_REGS(0, 4); + + /* configure CP0 MPP 37 and 38 to i2c */ + val = mmio_read_32(reg); + val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) | + (MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS)); + val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA << MVEBU_CP_MPP_CTRL37_OFFS) | + (MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA << MVEBU_CP_MPP_CTRL38_OFFS); + mmio_write_32(reg, val); +} + +/* + * This function may modify the default DRAM parameters + * based on information recieved from SPD or bootloader + * configuration located on non volatile storage + */ +int update_dram_info(struct dram_config *cfg) +{ + struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + + NOTICE("Gathering DRAM information\n"); + + if (tm->cfg_src == MV_DDR_CFG_SPD) { + /* configure MPPs to enable i2c */ + mpp_config(); + /* initialize the i2c */ + i2c_init((void *)MVEBU_CP0_I2C_BASE); + /* + * Dummy read to the SPD chip memory page selector. + * It is needed for for selecting the SPD memory page 0 + * prior to accessing the DRAM configuration data + */ + i2c_read(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1); + /* read data from spd */ + i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes, + sizeof(tm->spd_data.all_bytes)); + } + + return 0; +} + +void *plat_get_dram_data(void) +{ + /* Update DRAM for dynamic platforms */ + update_dram_info(&dram_cfg); + + return &dram_cfg; +} diff --git a/plat/marvell/a8k/a80x0_cust/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_cust/board/marvell_plat_config.c new file mode 100644 index 00000000..ba4eeac1 --- /dev/null +++ b/plat/marvell/a8k/a80x0_cust/board/marvell_plat_config.c @@ -0,0 +1,198 @@ +/* + * *************************************************************************** + * Copyright (C) 2016 Marvell International Ltd. + * *************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of Marvell nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *************************************************************************** + */ + +#include <plat_config.h> +/* + * If bootrom is currently at BLE there's no need to include the memory + * maps structure at this point + */ +#ifndef IMAGE_BLE +#include <plat_def.h> + +/******************************************************************************* + * AMB Configuration + ******************************************************************************/ +struct amb_win *amb_memory_map; + +uintptr_t marvell_get_amb_reg_offs(int cp_index) +{ + return MVEBU_AMB_ADEC_BASE(cp_index); +} + +int marvell_get_amb_memory_map(struct amb_win **win, uint32_t *size) +{ + *win = amb_memory_map; + if (*win == NULL) + *size = 0; + else + *size = sizeof(amb_memory_map)/sizeof(struct amb_win); + + return 0; +} + +/******************************************************************************* + * RFU Configuration + ******************************************************************************/ + +struct rfu_win rfu_memory_map[] = { + /* CP1 (MCI0) internal regs */ + {0x0, 0xf4000000, 0x0, 0x2000000, MCI_0_TID}, + /* PCIe0 on CP1*/ + {0x0, 0xfa000000, 0x0, 0x1000000, MCI_0_TID}, + /* PCIe1 on CP1*/ + {0x0, 0xfb000000, 0x0, 0x1000000, MCI_0_TID}, + /* PCIe2 on CP1*/ + {0x0, 0xfc000000, 0x0, 0x1000000, MCI_0_TID}, + /* MCI 0 indirect window */ + {0x0, MVEBU_MCI_REG_BASE_REMAP(0), 0x0, 0x100000, MCI_0_TID}, + /* MCI 1 indirect window */ + {0x0, MVEBU_MCI_REG_BASE_REMAP(1), 0x0, 0x100000, MCI_1_TID}, +}; + +uintptr_t marvell_get_rfu_reg_offs(void) +{ + return MVEBU_RFU_BASE; +} + +int marvell_get_rfu_memory_map(struct rfu_win **win, uint32_t *size) +{ + *win = rfu_memory_map; + if (*win == NULL) + *size = 0; + else + *size = sizeof(rfu_memory_map)/sizeof(struct rfu_win); + + return 0; +} + +/******************************************************************************* + * IOB Configuration + ******************************************************************************/ +#define MARVELL_IOB_MAX_WIN 16 + +struct iob_win iob_memory_map_cp0[] = { + /* CP0 */ + /* PEX1_X1 window */ + {0x0, 0xf7000000, 0x0, 0x1000000, PEX1_TID}, + /* PEX2_X1 window */ + {0x0, 0xf8000000, 0x0, 0x1000000, PEX2_TID}, + /* PEX0_X4 window */ + {0x0, 0xf6000000, 0x0, 0x1000000, PEX0_TID} +}; + +struct iob_win iob_memory_map_cp1[] = { + /* CP1 */ + /* PEX1_X1 window */ + {0x0, 0xfb000000, 0x0, 0x1000000, PEX1_TID}, + /* PEX2_X1 window */ + {0x0, 0xfc000000, 0x0, 0x1000000, PEX2_TID}, + /* PEX0_X4 window */ + {0x0, 0xfa000000, 0x0, 0x1000000, PEX0_TID} +}; + +uintptr_t marvell_get_iob_reg_offs(int cp_index) +{ + return MVEBU_IOB_BASE(cp_index); +} + +int marvell_get_iob_max_win(void) +{ + return MARVELL_IOB_MAX_WIN; +} + +int marvell_get_iob_memory_map(struct iob_win **win, + uint32_t *size, int cp_index) +{ + switch (cp_index) { + case 0: + *win = iob_memory_map_cp0; + *size = sizeof(iob_memory_map_cp0)/sizeof(struct iob_win); + return 0; + case 1: + *win = iob_memory_map_cp1; + *size = sizeof(iob_memory_map_cp1)/sizeof(struct iob_win); + return 0; + default: + *size = 0; + *win = 0; + return 1; + } +} + +/******************************************************************************* + * CCU Configuration + ******************************************************************************/ +#define MARVELL_CCU_MAX_WIN 8 + +struct ccu_win ccu_memory_map[] = { + {0x0, 0xf2000000, 0x0, 0xe000000, IO_0_TID}, /* IO window */ +}; + +uintptr_t marvell_get_ccu_reg_offs(void) +{ + return MVEBU_CCU_BASE; +} + +int marvell_get_ccu_max_win(void) +{ + return MARVELL_CCU_MAX_WIN; +} + +int marvell_get_ccu_memory_map(struct ccu_win **win, uint32_t *size) +{ + *win = ccu_memory_map; + *size = sizeof(ccu_memory_map)/sizeof(struct ccu_win); + + return 0; +} +/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */ +#else +/******************************************************************************* + * SKIP IMAGE Configuration + ******************************************************************************/ + +struct skip_image skip_im = { + .detection_method = GPIO, + .info.gpio.num = 33, + .info.gpio.button_state = HIGH, + .info.test.cp_ap = CP, + .info.test.cp_index = 0, +}; + +void *plat_get_skip_image_data(void) +{ + /* Return the skip_image configurations */ + return &skip_im; +} +#endif diff --git a/plat/marvell/a8k/a80x0_cust/plat_def.h b/plat/marvell/a8k/a80x0_cust/plat_def.h new file mode 100644 index 00000000..68987dcf --- /dev/null +++ b/plat/marvell/a8k/a80x0_cust/plat_def.h @@ -0,0 +1,44 @@ +/* + * *************************************************************************** + * Copyright (C) 2016 Marvell International Ltd. + * *************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of Marvell nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *************************************************************************** + */ + +#ifndef __MVEBU_DEF_H__ +#define __MVEBU_DEF_H__ + +#include <a8k_plat_def.h> + +#define CP_COUNT 2 /* A80x0 has both CP0 & CP1 */ +#define I2C_SPD_ADDR 0x53 /* Access SPD data */ +#define I2C_SPD_P0_ADDR 0x36 /* Select SPD data page 0 */ + +#endif /* __MVEBU_DEF_H__ */ diff --git a/plat/marvell/a8k/a80x0_cust/platform.mk b/plat/marvell/a8k/a80x0_cust/platform.mk new file mode 100644 index 00000000..42fe2ce6 --- /dev/null +++ b/plat/marvell/a8k/a80x0_cust/platform.mk @@ -0,0 +1,35 @@ +# +# *************************************************************************** +# Copyright (C) 2016 Marvell International Ltd. +# *************************************************************************** +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of Marvell nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +include plat/marvell/a8k/common/a8k_common.mk + +include plat/marvell/common/marvell_common.mk |