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2018-05-29plat: a8k: add function that retrieves chip revisionatf-v1.4-armada-18.06Christine Gharzuzi
- This function retrieves the AP id (i.e 806/807/810) - This function is needed since retrieving chip id will be used in multiple cases. Change-Id: I13775ed5919ff10ac99e368317f89b359642d658 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/55764 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/55885
2018-05-22Bump atf-v1.4 to release armada-18.05.2Konstantin Porotchkin
Change-Id: Ibe0be617455e13de52351f21f6ef8b3d7173cd97 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/55479
2018-05-22fix: docs: Fix typo in porting documentKonstantin Porotchkin
The porting document refers to "doc" folder instead of "docs" Change-Id: I28e5085ce4be3eed33bc6776e2adc09f36a7ae4f Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/55478 Reviewed-by: Nadav Haklai <nadavh@marvell.com>
2018-05-22a8k: svc: support A806-CP115 AVS configuration.Christine Gharzuzi
- A806-CP115 has a new device_id but same SVC algorithm for AP806-CP110 - This patch integrates the AVS configuration in AP806-CP115 to the existing configuration of AP806-CP110. Change-Id: I722a18606e7cbe236662703009ed87e915217a30 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54511 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> (cherry picked from commit ff3c8cd12fbedf67f93bf0d53e61093debc8d5aa) Reviewed-on: http://vgitil04.il.marvell.com:8080/55043 Reviewed-by: Nadav Haklai <nadavh@marvell.com>
2018-05-10Bump atf-v1.4 to release armada-18.05.1Konstantin Porotchkin
Change-Id: Id7499b34da27e50630d749b6b0db745ebc0bb2b1 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54413 Reviewed-by: Neta Zur Hershkovits <neta@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-05-10Revert "a8k-p: pm: poweroff unused CPUs at early boot stage"Hanna Hawa
Revert poweroff at early boot stage due some issues while poweron This reverts commit b33b8976e4251d2f546cfa3195d8cea7a9822e60. Change-Id: I8e5cfd4fe7b49fcbda59daae3dff473df46e4482 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54320 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54395
2018-05-10fix: ap810: update Aurora2 configuration and set all reads to be uniqueHanna Hawa
Change-Id: I1c74c240e384fd3743c5f30531c73f2472f60a26 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54740 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54842
2018-05-10fix: a3700: correct the offset between eip continuous decode windowsKen Ma
The offset between eip continuous decode windows is 8 bytes but not 16(0x10) bytes, this patch fixes it. Change-Id: I1e42c80bcdb621c5701ac72191c112bef106db8e Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53849 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54839
2018-04-29Bump atf-v1.4 to release devel-18.05.0Konstantin Porotchkin
Change-Id: I2e072a0bef6df74aebaa3b205e46c29b4e68c5e0 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54142 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Neta Zur Hershkovits <neta@marvell.com>
2018-04-29a3900: pm: poweroff unused CPUs at early boot stageChristine Gharzuzi
- bootloader flow uses only CPU0 and CPU1-3 remain in reset (not powered off) which leads to more unnecessary power consuming and in some cases might increase SoC temperature. - this patch powers off CPU1-3 in early BLE stage, and powered back on during Linux PSCI calls to a8k_pwr_domain_on. - since the offsets in power register differs in ap806 and ap807, the offsets are defined per platform and not the common driver. Change-Id: Iae72577fc532be0bdb7f0899eb77b7ea1bb078ba Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53007 Reviewed-by: Hanna Hawa <hannah@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-04-29fix: smmu: ap810: fix SMMU base address in AP810 dieHanna Hawa
Change-Id: I89351902a36208db75652362986d414580189644 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/54019 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-04-26a8k-p: pm: poweroff unused CPUs at early boot stageChristine Gharzuzi
- bootloader flow uses only CPU0 and CPU1-7 (per AP) remain in reset (not powered off) which leads to more unnecessary power consuming and in some cases might increase SoC temperature. - this patch powers off CPU1-7 in early BLE stage, and powered back on during Linux PSCI calls to a8k_pwr_domain_on. Change-Id: Id2415b9703b5033fa77fda00d1fec22e830610a5 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52915 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-25mvebu: cp110: fix comphy offset error checkingGrzegorz Jaszczyk
Change-Id: If62977b92f13409bca90a690b179aa3cfada9be1 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53493 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-25mvebu: cp110: allow to pass SD phys addr instead of COMPHY phys via SMCGrzegorz Jaszczyk
Mainline Linux driver registers only SD address for comphy driver (the COMPHY address is referenced as syscon regmap). To make the RT SVC more flexible allow to pass SD address and convert it to COMPHY addr at the beginning for each comphy FID. Change-Id: I55af0b699188bae35d5251177a7ff5bdeb698d0d Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53492 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-25marvell: psci: disable cache in el3Igal Liberman
Currently, there's an open issue is some setups when cpuidle is enabled - after sometime, one of the cores might fail to come up after suspend. This issue is under debug but generally it caused by cache operations performed on the el3 stack. For now, as a workaround, disable el3 cache, in order to enable cpuidle feature. Change-Id: Icf7dafeab701b34b23b6bcde78f0b8dc8d727e28 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52671 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-22ble: ap810: configure address deconding for DRAM scrubbing and validation ↵Ofir Fedida
purpose 1.Revise plat_dram_temp_addr_decode_cfg function: Add a single GWIN entry from AP1 to AP0 enabling remote AP access Also add a CCU window which will pass all transactions to SRAM through the GWIN window. These widows are needed for DRAM scrubbing and DRAM validation purpose both using XOR which saves descriptors on SRAM located in AP0 Also open a CCU window for each AP to it's DRAM interface 2. Remap DRAM window to end of dram size for ap 0 interfaces 3. Remove the temporary GWIN and CCU windows configured before DRAM training Change-Id: I8de102eb47d39dd61557f96b809f9ad22295c3bf Signed-off-by: Ofir Fedida <ofedida@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53095 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-04-22ble: ap810: remove unused functionsOfir Fedida
Remove functions: - plat_dram_addr_decode_insert - plat_dram_addr_decode_remove These functions sets (and clear) the address decoding in order to execute DRAM scrubbing by ble DRAMS scrubbing will be executed by DRAM driver and ble will set (and clear) the address decooding when executing DRAM training. Also sets the address decoding DRAM window to the default window opneed by BootROM Change-Id: Id17327e1d52796cc754a1c754488763d356b2026 Signed-off-by: Ofir Fedida <ofedida@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53094 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-17plat: marvell: Enable CA72 Errata 859971 handlingKonstantin Porotchkin
Enable handling of CA72 Errata 859971 on A8K and A8K+ platforms 859971: Speculative instruction prefetch to Execute-never (XN) memory could cause deadlock or data integrity issue Category B Rare Products Affected: Cortex-A72 MPCORE. Present in: r0p0, r0p1, r0p2, r0p3 Change-Id: I7fade6519c630c2f3840ac7c3f1fc5b7416eba05 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53238 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2018-04-16mvebu: cp110: fix digital reset RT SVCGrzegorz Jaszczyk
The command argument (x4) was missing and not passed during digital reset function call. Change-Id: I50fa176182ddabe904ab1d2f9cae5d73f6fbb7c0 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53132 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2018-04-16Add support for SMCCC_VERSION in PSCI featuresDimitris Papastamos
On some platforms it may be necessary to discover the SMCCC version via a PSCI features call. Change-Id: I95281ac2263ca9aefda1809eb03464fbdb8ac24d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53237 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16runtime_exceptions: Save x4-x29 unconditionallyDimitris Papastamos
In preparation for SMCCC v1.1 support, save x4 to x29 unconditionally. Previously we expected callers coming from AArch64 mode to preserve x8-x17. This is no longer the case with SMCCC v1.1 as AArch64 callers only need to save x0-x3. Change-Id: Ie62d620776533969ff4a02c635422f1b9208be9c Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53236 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75Dimitris Papastamos
This patch implements a fast path for this SMC call on affected PEs by detecting and returning immediately after executing the workaround. NOTE: The MMU disable/enable workaround now assumes that the MMU was enabled on entry to EL3. This is a valid assumption as the code turns on the MMU after reset and leaves it on until the core powers off. Change-Id: I13c336d06a52297620a9760fb2461b4d606a30b3 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53234 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Implement support for SMCCC v1.1Dimitris Papastamos
SMCCC v1.1 comes with a relaxed calling convention for AArch64 callers. The caller only needs to save x0-x3 before doing an SMC call. This patch adds support for SMCCC_VERSION and SMCCC_ARCH_FEATURES. Refer to "Firmware Interfaces for mitigating CVE_2017_5715 System Software on Arm Systems"[0] for more information. [0] https://developer.arm.com/-/media/developer/pdf/ARM%20DEN%200070A%20Firmware%20interfaces%20for%20mitigating%20CVE-2017-5715_V1.0.pdf Change-Id: If5b1c55c17d6c5c7cb9c2c3ed355d3a91cdad0a9 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53235 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Optimize/cleanup BPIALL workaroundDimitris Papastamos
In the initial implementation of this workaround we used a dedicated workaround context to save/restore state. This patch reduces the footprint as no additional context is needed. Additionally, this patch reduces the memory loads and stores by 20%, reduces the instruction count and exploits static branch prediction to optimize the SMC path. Change-Id: Ia9f6bf06fbf8a9037cfe7f1f1fb32e8aec38ec7d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53233 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Workaround for CVE-2017-5715 on Cortex A73 and A75Dimitris Papastamos
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by temporarily dropping into AArch32 Secure-EL1 and executing the `BPIALL` instruction. This is achieved by using 3 vector tables. There is the runtime vector table which is used to handle exceptions and 2 additional tables which are required to implement this workaround. The additional tables are `vbar0` and `vbar1`. The sequence of events for handling a single exception is as follows: 1) Install vector table `vbar0` which saves the CPU context on entry to EL3 and sets up the Secure-EL1 context to execute in AArch32 mode with the MMU disabled and I$ enabled. This is the default vector table. 2) Before doing an ERET into Secure-EL1, switch vbar to point to another vector table `vbar1`. This is required to restore EL3 state when returning from the workaround, before proceeding with normal EL3 exception handling. 3) While in Secure-EL1, the `BPIALL` instruction is executed and an SMC call back to EL3 is performed. 4) On entry to EL3 from Secure-EL1, the saved context from step 1) is restored. The vbar is switched to point to `vbar0` in preparation to handle further exceptions. Finally a branch to the runtime vector table entry is taken to complete the handling of the original exception. This workaround is enabled by default on the affected CPUs. NOTE ==== There are 4 different stubs in Secure-EL1. Each stub corresponds to an exception type such as Sync/IRQ/FIQ/SError. Each stub will move a different value in `R0` before doing an SMC call back into EL3. Without this piece of information it would not be possible to know what the original exception type was as we cannot use `ESR_EL3` to distinguish between IRQs and FIQs. Change-Id: I90b32d14a3735290b48685d43c70c99daaa4b434 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53232 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Disable workaround for CVE-2017-5715 on unaffected platformsDimitris Papastamos
Change-Id: Ib67b841ab621ca1ace3280e44cf3e1d83052cb73 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53231 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Change the default errata format stringDimitris Papastamos
As we are using the errata framework to handle workarounds in a more general sense, change the default string to reflect that. Change-Id: I2e266af2392c9d95e18fe4e965f9a1d46fd0e95e Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53230 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Print erratum application report for CVE-2017-5715Dimitris Papastamos
Even though the workaround for CVE-2017-5715 is not a CPU erratum, the code is piggybacking on the errata framework to print whether the workaround was applied, missing or not needed. Change-Id: I821197a4b8560c73fd894cd7cd9ecf9503c72fa3 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53229 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Cortex-A72: Implement workaround for erratum 859971Eleanor Bonnici
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53228 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15fix: ble: ap810: change flow and fix dram target idOfir Fedida
in case of not using RAR the dram target id is set for the second interface instead of the first also fixed the flow to be more readable Change-Id: I27d149ee0db27339e7e661d362a0a3af739cd082 Signed-off-by: Ofir Fedida <ofedida@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53079 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-12a3900: switch to PLL clk driver.Christine Gharzuzi
- ap807 default clk driver is ARO - this patch enables PLL clk driver and disables ARO clk driver Change-Id: I45da24f2db436eb24d361261cc289b3ee9b4ceeb Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53113 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-12mvebu: cp110: fix settings for the phy and pipe selectorGrzegorz Jaszczyk
When the pipe selector is configured the phy selector should be cleared (marked as unconnected) and vice-versa. Change-Id: Ie5a6eef2f05042dea3a4e7928d506cd5268fc465 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53133 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-04-08mvebu: cp110: add support for digital resetGrzegorz Jaszczyk
Change-Id: Iaed7504ccd349456e3e16ac96e7f3a423bfb4f94 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52902 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-08mvebu: cp110: add support for AP comphy configurationGrzegorz Jaszczyk
Change-Id: I906e6cc740ba0cde3bced07b117da7dd3aad767e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52903 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-08mvebu: cp110: add support for XFI trainingGrzegorz Jaszczyk
It will be exposed as run time service, so the OS or Bootloader can trigger it. Change-Id: I08143856e3b8f3e51d472acd2182942b6ef358b8 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52901 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-08mvebu: cp110: add support for USB comphy configurationGrzegorz Jaszczyk
Change-Id: I1a3ff0bb832a165bb37e1e6eea1b5c1d438505b5 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52799 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-08mvebu: cp110: add support for RXAUI comphy configurationGrzegorz Jaszczyk
Change-Id: Ie23b3ac7d7235f2dffa040d42049675a2a313a24 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52714 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-03-29fix: ble: ap810: update plat_dram init flowHanna Hawa
Issue found when load Dual AP with 2 DDR DIMM per AP the base address of interface 0 on AP1 is not correct. Update the DRAM init flow and run mmap_config per interface to fix the start address of AP1 Change-Id: I767bcca8f9433457c2ebb53f34e4a41ca145c17e Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52803 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-03-29mvebu: cp110: add support for PCIe comphy configurationGrzegorz Jaszczyk
Change-Id: I3b8545f9eaefc6f312e40f3369c048a691e655ce Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52627 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-03-29mvebu: cp110: improve commentsGrzegorz Jaszczyk
No functional change Change-Id: If8d88bef1451c3dd961092108ebde7d00eee5167 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52626 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-03-28Bump atf-v1.4 to release devel-18.04.1Hanna Hawa
Change-Id: I9265191f03fed50e4dd69446395858f49c5c4267 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52741 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-03-28clocks: a8k-p: align frequency tables to official valuesChristine Gharzuzi
- update frequency tables to be aligned with the official tables for ap810 Change-Id: I777f2faaaa461427b24d1ada02540173850d6db8 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52649 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2018-03-28Makefile: add compilation flag for ARO modeChristine Gharzuzi
- ARO mode is not supported by default anymore in order to use ARO mode a compilation flag is added to Makefile Change-Id: Ie5f542ccbf824c1f30fdfb967ebc05fa41c92f93 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52648 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2018-03-28clocks: a8k-p: switch to PLL mode by defaultChristine Gharzuzi
- switch to PLL mode by default and only use ARO mode by configuring a compilation flag Change-Id: I95465e143f305079e20232a9a74bc7f2f28003c8 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52647 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-03-28clocks: a8k-p: add PLL registers and values for clocks configurationsChristine Gharzuzi
- preparations to switch default mode to PLL mode - adding PLL registers and PLL values to clock driver Change-Id: I3c06e10f9f24e43c4ba516cf17432d9c01a6c6af Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52646 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2018-03-28clocks: a8k-p: modify transactions prepartion in clocks driverChristine Gharzuzi
- previously preparing transctions for EAWG configuration is done from the start of the PLL clocks tables till the specified index in the table. - this patch adds option to specify a start index at the PLL clocks tables. Change-Id: I012203ba13e66440cff7b025d5e572eb4cecdd06 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52645 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-03-28Bump atf-v1.4 to release devel-18.04.0Konstantin Porotchkin
Change-Id: I863815d3a28ba7277a19176213cafbdb6236f0d7 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52654 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2018-03-28fix: Makefile: a3700: align wtmi image with 4 bytesjinghua
To boot from eMMC, there is a limitation that each firmware component size has to be aligned with 4 bytes. Since u-boot image has already been aligned, this patch does it for WTMI image. Change-Id: Ie8f4517d5f04baedc7bca2bd230c5ce2f73b3e3a Signed-off-by: jinghua <jinghua@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52417 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> (cherry picked from commit 1eed2fc33ab121f2792c8829f5dd96796a4a0a7e) Reviewed-on: http://vgitil04.il.marvell.com:8080/52685
2018-03-28plat_pm: ap807: disable PM options for Armada-AP-807Christine Gharzuzi
Disabled CPUs early powerdown and powerup in Linux boot, for AP807 Change-Id: I69f935719772e0ba1619931557b94b63cea5fe58 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52588 Reviewed-by: Hanna Hawa <hannah@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-03-27stream-id: cp110: fix initialization of STREAM-IDDavid Sniatkiwicz
This patch fixes stream id initialization for CP110. - Initialize the Intr-Stream-ID in addition to the Func-Stream-ID. Change-Id: Iab777d0660159cd4d138702b773e7310f11a5fdc Signed-off-by: David Sniatkiwicz <davidsn@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/49299 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
generated by cgit (git 2.34.1) at 2024-04-27 21:44:13 +0000