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Marvell RFU address decoding bindings
=====================================
The RFU includes a description of the address decoding configuration.
Transactions that are decoded by CCU windows as IO peripheral, have an additional
layer of decoding. This additional address decoding layer defines one of the
following targets:
0x0 = BootRom
0x1 = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
0x2 = SPI direct access
0x3 = PCIe registers
0x4 = MCI Port
0x5 = PCIe port
Mandatory functions:
- marvell_get_rfu_reg_offs
returns the base address of the RFU unit
- marvell_get_rfu_memory_map
returns the RFU windows configuration and the number of windows
Mandatory structures:
rfu_memory_map - Array that include the configuration of the windows
every window/entry is a struct which has 5 parameters:
- High base address of the window
- Low base address of the window
- High size of the window
- Low size of the window
- Target-ID of the window
Note: if the base address is more than 32 bits, it divided into high and low.
The same goes for the Size field, if it more that 32 bits, is divided into
high and low.
Base example:
base address: 0x10f0000000 should divided into:
base address high: 0x10
base address low: 0xf0000000
Size example:
size: 0x1E00F00000 should divided into:
size high: 0x1E
size low: 0x00F00000
Example:
struct rfu_win rfu_memory_map[] = {
{0x0, 0xfe000000, 0x0, 0x1f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
{0x0, 0xffe00000, 0x0, 0x100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/
{0x0, 0xf6000000, 0x0, 0x100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/
};
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