diff options
| author | Wladimir J. van der Laan <laanwj@gmail.com> | 2014-01-27 16:59:57 +0100 |
|---|---|---|
| committer | Wladimir J. van der Laan <laanwj@gmail.com> | 2014-01-27 16:59:57 +0100 |
| commit | 5f85b522d13747deaa26229e0c9e9a076ad5a63b (patch) | |
| tree | e22f97976fef14596aa09c5c59492587c0a097c7 /doc | |
| parent | 24ab6f51f93c2873c048f4eaa261c44d01440d67 (diff) | |
Documentatino update
gc2000 have minorFeatures4, document the register,
not that we know any of the bits yet...
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/hardware.md | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/doc/hardware.md b/doc/hardware.md index 8f32c5c..229aced 100644 --- a/doc/hardware.md +++ b/doc/hardware.md @@ -560,3 +560,14 @@ the appropriate cache so that the rendered cache tiles are properly written back - before flushing the TS cache (as before a clear) first make sure that DEPTH and COLOR are flushed, and a stall from RA to PE is done, otherwise a crash will happen. + +Memory alignment +----------------- + +We should take this errata into account moving down the road with GPU drivers. +The GPU3D L1 cache assumes that all memory requests are 16 bytes. If a request is 16 bytes, there +are no issues since the data boundary lines up evenly. If a request is not aligned to 16 bytes, the +memory controller will split those unaligned requests into two requests, doubling the number of +requests processed internally in L1 cache. +(jnettlet) + |