path: root/rnndb/isa.xml

<?xml version="1.0" encoding="UTF-8"?>
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-->
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<!-- Vivante GCxxxx instruction set overview  -->
<domain name="VIV_ISA">
<!-- XXX still unsure if rules-ng is a suitable format for ISA descriptions,
 I don't really think so, but it will initially help to put notes in a more structured format.
 See function assemble() in asm.py and function disassemble() in etnaviv/disasm.py for details on assembling/disassembling
 an instruction using the bitfields and instructions defined in this file.
 -->
<enum name="INST_OPCODE" brief="Main opcode table">
    <!-- TODO: match against TGSI instructions
         http://people.freedesktop.org/~csimpson/gallium-docs/tgsi.html

         Overall the ISA seems to be based on DirectX shader assembly. This is pretty obvious in retrospect
         as Vivante started by marketing DirectX-compatible GPUs for playing desktop PC games.

         Restrictions:
         - only one uniform can be read per instruction, however this single uniform can be used in
           multiple arguments.
            - when violating this restriction it will be as if the uniform in the last source register
              is broadcasted to all arguments that use an uniform.
     -->
    <doc>
        Unused operands of an instruction should have their use flag at 0.

        Unless mentioned otherwise, instructions do the same for all four components of the vector-valued
        operands.

        Operands src0,src1 and src2 can come from a temporary register or an uniform.
    </doc>
    <value value="0x00" name="NOP" brief="No operation"/>
    <value value="0x01" name="ADD" brief="Add">
        <doc>
            dst := src0 + src2

            src0 is added to src1 and the result is put into temporary register dst.
        </doc>
    </value>
    <value value="0x02" name="MAD" brief="Multiply add">
        <doc>
            dst := src0 * src1 + src2

            src0 is multipied with src1, then src2 is added. The result is put into temporary
            register dst.
        </doc>
    </value>
    <value value="0x03" name="MUL" brief="Multiply">
        <doc>
            dst := src0 * src1

            src0 is multipied with src1 and the result is put into temporary register dst.
        </doc>
    </value>
    <value value="0x04" name="DST" brief="Calculates a distance vector">
        <doc>
            dst.x := 1
            dst.y := src0.y * src1.y
            dst.z := src0.z
            dst.w := src1.w

            http://msdn.microsoft.com/en-us/library/windows/desktop/bb219790%28v=vs.85%29.aspx
        </doc>
    </value>
    <value value="0x05" name="DP3" brief="3-component dot product">
        <doc>
            dst := src0.x * src1.x + src0.y * src1.y + src0.z * src1.z

            Computes the component-wise dot product of the first three components between src0 and src1 and
            broadcasts the results to all destination components in temporary register dst.
        </doc>
    </value>
    <value value="0x06" name="DP4" brief="4-component dot product">
        <doc>
            dst := src0.x * src1.x + src0.y * src1.y + src0.z * src1.z + src0.w * src1.w

            Computes the component-wise dot product between src0 and src1 and broadcasts the results to all destination
            components in temporary register dst.
        </doc>
    </value>
    <value value="0x07" name="DSX" brief="Compute derivative relative to X"/>
    <value value="0x08" name="DSY" brief="Compute derivative relative to Y"/>
    <value value="0x09" name="MOV" brief="Move to temporary register">
        <doc>
            dst := src2

            Copies the value of operand src2 to temporary register dst.
        </doc>
    </value>
    <value value="0x0A" name="MOVAR" brief="Move address to address register"/>
    <value value="0x0B" name="MOVAF" brief="Move float to address register">
        <doc>
            dst := src2

            Copies the floating point value of operand src2 to address register dst.
            XXX does this round or floor?
        </doc>
    </value>
    <value value="0x0C" name="RCP" brief="Reciprocal">
        <doc>
            dst := 1.0 / src2

            Computes the reciprocal of src2, and puts the result into temporary register dst.
        </doc>
    </value>
    <value value="0x0D" name="RSQ" brief="Reciprocal square root">
        <doc>
            dst := 1.0 / sqrt(src2)

            Computes the reciprocal of the square root of src2, and puts the result into
            temporary register dst.
        </doc>
    </value>
    <value value="0x0E" name="LITP" brief="Partial lighting computation">
        <doc>
            dst.x := 1
            dst.y := src1.y IF (src1.z > 0 AND src0.y > 0) else 0
            dst.z := exp(src2.x) IF (src1.z > 0 AND src0.z > 0) else 0
            dst.w := 1

            Partial http://msdn.microsoft.com/en-us/library/windows/desktop/bb174703%28v=vs.85%29.aspx
            Note: If src0 is disabled, src0.y > 0 and src0.z > 0 evaluate as true.
        </doc>
    </value>
    <value value="0x0F" name="SELECT" brief="Choose input based on condition">
        <doc>
            dst := src1 COND src0 ? src2 : src1 (binary condition)
            dst := COND(src0) ? src1 : src2 (unary condition)

            Sets temporary register dst to src2 if (src1 COND src0) holds, otherwise to src1.
            This operation is performed per-component. It is used to implement MIN(a,b) and MAX(a,b)
            in the following way:
            - MIN(a,b): SELECT.GT dst, a, b, a   (b > a ? a : b)
            - MAX(a,b): SELECT.LT dst, a, b, a   (b &lt; a ? a : b)
        </doc>
    </value>
    <value value="0x10" name="SET">
        <doc>
            dst := src0 COND src1

            Sets temporary register dst to 1.0 if (src0 COND src1), otherwise to 0.0.
        </doc>
    </value>
    <value value="0x11" name="EXP" brief="2^x">
        <doc>
            dst := exp2(src2.x)

            Sets temporary register dst to the 2-exponent of the x component of src2).
            This is a scalar operation, the result is broadcasted over all active destination components.
        </doc>
    </value>
    <value value="0x12" name="LOG" brief="log2">
        <doc>
            dst := log2(src2.x)

            Sets temporary register dst to the 2-log of the x component of src2).
            This is a scalar operation, the result is broadcasted over all active destination components.
        </doc>
    </value>
    <value value="0x13" name="FRC" brief="Return fractional portion">
        <doc>
            dst := frc(src2)

            Sets temporary register dst to the fractional portion of src2 for positive values. For negative values,
            the returned value will be 1.0 - the fractional portion. For example, 1.5 will become 0.5, and -0.1
            will be turned into 0.9.
        </doc>
    </value>
    <value value="0x14" name="CALL" brief="Function call"/>
    <value value="0x15" name="RET" brief="Return from function"/>
    <value value="0x16" name="BRANCH" brief="Jump to address">
        <doc>
            pc := src2_imm *if src0 COND src1*

            Changes the current value of the instruction pointer if (src0 COND src1) evaluates
            to true.
        </doc>
    </value>
    <value value="0x17" name="TEXKILL" brief="Cancels rendering of the current fragment">
        <doc>
            Discards (kills) the current fragment. Can only be used in PS.

            Kill fragment if src0 *COND* src1.
        </doc>
    </value>
    <value value="0x18" name="TEXLD" brief="Texture load">
        <doc>
            dst := textureND(tex, src0)

            Samples texture coordinate src0 with sampler tex, and returns the sampled color in temporary register dst.
        </doc>
    </value>
    <value value="0x19" name="TEXLDB" brief="Texture load (biased)"/>
    <value value="0x1A" name="TEXLDD" brief="Texture load (manually specified gradients)"/>
    <value value="0x1B" name="TEXLDL" brief="Texture load (at particular LOD)"/>
    <value value="0x1C" name="TEXLDPCF" brief="Texture load"/>
    <value value="0x1D" name="REP" brief="Begins a REPEAT block"/>
    <value value="0x1E" name="ENDREP" brief="Ends a REPEAT block"/>
    <value value="0x1F" name="LOOP" brief="Begins a LOOP block"/>
    <value value="0x20" name="ENDLOOP" brief="Ends a LOOP block"/>
    <value value="0x21" name="SQRT" brief="Square root"> <!-- HAS_SQRT_TRIG -->
        <doc>
            dst := sqrt(src2)

            Computes the square root of src2 and puts the result in temporary register dst.
        </doc>
    </value>
    <value value="0x22" name="SIN" brief="Sine"> <!-- HAS_SQRT_TRIG -->
        <doc>
            dst := sin(src2 * (PI/2))

            Computes the sine of src2 and puts the result in temporary register dst.

            The period of the sine is 4 and not 2 PI, thus to get normal behavior the instruction
            should be prefixed by a division by PI/2.
        </doc>
    </value>
    <value value="0x23" name="COS" brief="Cosine"> <!-- HAS_SQRT_TRIG -->
        <doc>
            dst := cos(src2 * (PI/2))

            Computes the cosine of src2 and puts the result in temporary register dst.

            The period of the cosine is 4 and not 2 PI, thus to get normal behavior the instruction
            should be prefixed by a division by PI/2.
        </doc>
    </value>
    <value value="0x25" name="FLOOR" brief="Largest integral value not greater than the argument"> <!-- HAS_SIGN_FLOOR_CEIL -->
        <doc>
            dst := floor(src2)

            Computes the largest integral value not greater than the argument, and puts the result in temporary
            register dst.
        </doc>
    </value>
    <value value="0x26" name="CEIL" brief="Smallest integral value not less than the argument"> <!-- HAS_SIGN_FLOOR_CEIL -->
        <doc>
            dst := ceil(src2)

            Computes the smallest integral value not less than the argument, and puts the result in temporary
            register dst.
        </doc>
    </value>
    <value value="0x27" name="SIGN" brief="Return sign of the argument"> <!-- HAS_SIGN_FLOOR_CEIL -->
        <doc>
            dst := sign(src2)

            Return 1.0 if the sign is positive or zero, -1.0 if negative.
        </doc>
    </value>
    <!-- OpenCL (GC2000+) -->
    <value value="0x2D" name="I2F" brief="Integer to float">
        <doc>
            dst := float(src0)

            Convert source operand to a float and put the result in temporary register dst.
        </doc>
    </value>
    <value value="0x31" name="CMP" brief="Integer compare"/>
    <value value="0x32" name="LOAD" brief="Memory load"/>
    <value value="0x33" name="STORE" brief="Memory store"/>
    <value value="0x3C" name="IMULLO0" brief="Integer multiply"/>
    <value value="0x40" name="IMULHI0" brief="High half of the product of x and y (mul_hi intrinsic)"/>
    <value value="0x58" name="LEADZERO" brief="Count leading zeros (clz intrinsic)"/>
    <value value="0x59" name="LSHIFT" brief="Bitwise left shift"/>
    <value value="0x5A" name="RSHIFT" brief="Bitwise right shift"/>
    <value value="0x5B" name="ROTATE" brief="Bitwise rotate (rotate intrinsic)"/>
    <value value="0x5C" name="OR" brief="Bitwise or"/>
    <value value="0x5D" name="AND" brief="Bitwise and"/>
    <value value="0x5E" name="XOR" brief="Bitwise exclusive or"/>
    <value value="0x5F" name="NOT" brief="Bitwise not"/>
</enum>

<enum name="INST_CONDITION" brief="Condition code">
    <value value="0x00" name="TRUE"/>
    <value value="0x01" name="GT"/>
    <value value="0x02" name="LT"/>
    <value value="0x03" name="GE"/>
    <value value="0x04" name="LE"/>
    <value value="0x05" name="EQ"/>
    <value value="0x06" name="NE"/>
    <value value="0x07" name="AND"/>
    <value value="0x08" name="OR"/>
    <value value="0x09" name="XOR"/>
    <value value="0x0A" name="NOT"/>
    <value value="0x0B" name="NZ"/>
    <value value="0x0C" name="GEZ"/>
    <value value="0x0D" name="GZ"/>
    <value value="0x0E" name="LEZ"/>
    <value value="0x0F" name="LZ"/>
</enum>

<bitset name="INST_COMPS" brief="Vector components">
    <bitfield pos="0" name="X" brief="Component 0"/>
    <bitfield pos="1" name="Y" brief="Component 1"/>
    <bitfield pos="2" name="Z" brief="Component 2"/>
    <bitfield pos="3" name="W" brief="Component 3"/>
</bitset>

<enum name="INST_RGROUP" brief="Register group">
    <value value="0" name="TEMP" brief="Temporary"/>
    <value value="1" name="INTERNAL" brief="Derived values">
        Only one register in this range is known:
        - 0.x: gl_FrontFacing (PS)
    </value>
    <value value="2" name="UNIFORM_0" brief="Uniforms 0..127"/>
    <value value="3" name="UNIFORM_1" brief="Uniforms 128..255"/>
    <!-- 4..7 alias 0..3 -->
</enum>

<enum name="INST_AMODE" brief="Addressing mode">
    <value value="0" name="DIRECT"/>
    <value value="1" name="ADD_A_X" brief="Add a.x to the sampler or register index"/>
    <value value="2" name="ADD_A_Y" brief="Add a.y to the sampler or register index"/>
    <value value="3" name="ADD_A_Z" brief="Add a.z to the sampler or register index"/>
    <value value="4" name="ADD_A_W" brief="Add a.w to the sampler or register index"/>
</enum>

<enum name="INST_SWIZ_COMP" brief="Swizzle source component">
    <value value="0" name="X" brief="Component 0"/>
    <value value="1" name="Y" brief="Component 1"/>
    <value value="2" name="Z" brief="Component 2"/>
    <value value="3" name="W" brief="Component 3"/>
</enum>
<bitset name="INST_SWIZ" brief="Swizzling mode">
    <bitfield high="1" low="0" name="X" type="INST_SWIZ_COMP" brief="Source for component 0"/>
    <bitfield high="3" low="2" name="Y" type="INST_SWIZ_COMP" brief="Source for component 1"/>
    <bitfield high="5" low="4" name="Z" type="INST_SWIZ_COMP" brief="Source for component 2"/>
    <bitfield high="7" low="6" name="W" type="INST_SWIZ_COMP" brief="Source for component 3"/>
</bitset>

<!-- The four instruction words. Vivante has a fixed-size, predictable instruction format
     with explicit inputs and outputs. This does simplify code generation,
     compared to a weird flow pipe system like the Mali 200/400.
  -->
<reg32 offset="0x00000" name="WORD_0">
    <bitfield high="5" low="0" name="OPCODE" type="INST_OPCODE"/>
    <bitfield high="10" low="6" name="COND" type="INST_CONDITION"/>
    <bitfield high="11" low="11" name="SAT" brief="Saturate"/>
    <bitfield high="12" low="12" name="DST_USE" brief="Destination used"/>
    <bitfield high="15" low="13" name="DST_AMODE" brief="Destination addressing mode"/>
    <bitfield high="22" low="16" name="DST_REG" brief="Destination register"/>
    <bitfield high="26" low="23" name="DST_COMPS" type="INST_COMPS" brief="Destination components"/>
    <bitfield high="31" low="27" name="TEX_ID" brief="Texture sampler id"/>
</reg32>
<reg32 offset="0x00004" name="WORD_1">
    <bitfield high="2" low="0" name="TEX_AMODE" type="INST_AMODE" brief="Texture addressing mode"/>
    <bitfield high="10" low="3" name="TEX_SWIZ" type="INST_SWIZ" brief="Texture swizzle">
        <doc>This swizzle is applied to the components of the value fetched from the texture.</doc>
    </bitfield>
    <!-- operand 0 -->
    <bitfield high="11" low="11" name="SRC0_USE" brief="Source operand 0 used"/>
    <bitfield high="20" low="12" name="SRC0_REG" brief="Source operand 0 register"/>
    <bitfield high="21" low="21" name="UNK1_21"/>
    <bitfield high="29" low="22" name="SRC0_SWIZ" type="INST_SWIZ" brief="Source operand 0 swizzle"/>
    <bitfield high="30" low="30" name="SRC0_NEG" brief="Source operand 0 negate"/>
    <bitfield high="31" low="31" name="SRC0_ABS" brief="Source operand 0 absolute"/>
</reg32>
<reg32 offset="0x00008" name="WORD_2">
    <bitfield high="2" low="0" name="SRC0_AMODE" type="INST_AMODE" brief="Source operand 0 addressing mode"/>
    <bitfield high="5" low="3" name="SRC0_RGROUP" type="INST_RGROUP" brief="Source operand 0 register group"/>
    <!-- operand 1 -->
    <bitfield high="6" low="6" name="SRC1_USE" brief="Source operand 1 used"/>
    <bitfield high="15" low="7" name="SRC1_REG" brief="Source operand 1 register"/>
    <bitfield high="16" low="16" name="OPCODE_BIT6" brief="Opcode bit 6 (GC2000+)"/>
    <bitfield high="24" low="17" name="SRC1_SWIZ" type="INST_SWIZ" brief="Source operand 1 swizzle"/>
    <bitfield high="25" low="25" name="SRC1_NEG" brief="Source operand 1 negate"/>
    <bitfield high="26" low="26" name="SRC1_ABS" brief="Source operand 1 absolute"/>
    <bitfield high="29" low="27" name="SRC1_AMODE" type="INST_AMODE" brief="Source operand 1 addressing mode"/>
    <bitfield high="31" low="30" name="UNK2_30"/>
</reg32>
<reg32 offset="0x0000C" name="WORD_3">
    <bitfield high="2" low="0" name="SRC1_RGROUP" type="INST_RGROUP" brief="Source operand 1 register group"/>
    <!-- bits 7..21: instruction address, effectively takes the place of src2 operand -->
    <bitfield high="21" low="7" name="SRC2_IMM" brief="Immediate (address) operand"/>
    <!-- operand 2 -->
    <bitfield high="3" low="3" name="SRC2_USE" brief="Source operand 2 used"/>
    <bitfield high="12" low="4" name="SRC2_REG" brief="Source operand 2 register"/>
    <bitfield high="13" low="13" name="UNK3_13"/>
    <bitfield high="21" low="14" name="SRC2_SWIZ" type="INST_SWIZ" brief="Source operand 2 swizzle"/>
    <bitfield high="22" low="22" name="SRC2_NEG" brief="Source operand 2 negate"/>
    <bitfield high="23" low="23" name="SRC2_ABS" brief="Source operand 2 absolute"/>
    <bitfield high="24" low="24" name="UNK3_24"/>
    <bitfield high="27" low="25" name="SRC2_AMODE" type="INST_AMODE" brief="Source operand 2 addressing mode"/>
    <bitfield high="30" low="28" name="SRC2_RGROUP" type="INST_RGROUP" brief="Source operand 2 register group"/>
    <bitfield high="31" low="31" name="UNK3_31"/>
</reg32>

</domain>
</database>