diff options
| author | Sai Krishna Musham <sai.krishna.musham@amd.com> | 2025-08-07 13:10:18 +0530 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2025-08-11 16:09:32 +0530 |
| commit | 0b9275edc3543d0d2d03313a7c8de5157d61b189 (patch) | |
| tree | 3926b01260069a0b06f2f957ea362e3c9a79359b | |
| parent | 8f5ae30d69d7543eee0d70083daf4de8fe15d585 (diff) | |
dt-bindings: PCI: amd-mdb: Add example usage of reset-gpios for PCIe RP PERST#
Update the device tree binding example to include usage of the
`reset-gpios` property in PCIe Root Port (RP) bridge node for PERST#
signal handling.
Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250807074019.811672-2-sai.krishna.musham@amd.com
| -rw-r--r-- | Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml index 43dc2585c237..421e1116ae7e 100644 --- a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml +++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml @@ -71,6 +71,17 @@ properties: - "#address-cells" - "#interrupt-cells" +patternProperties: + '^pcie@[0-2],0$': + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + unevaluatedProperties: false + required: - reg - reg-names @@ -87,6 +98,7 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> soc { #address-cells = <2>; @@ -112,6 +124,16 @@ examples: #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; + + pcie@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&tca6416_u37 7 GPIO_ACTIVE_LOW>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + pcie_intc_0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; |