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authorBrad Larson <blarson@amd.com>2023-04-10 11:45:13 -0700
committerUlf Hansson <ulf.hansson@linaro.org>2023-04-17 11:45:43 +0200
commit82e4726b00e9e9bf7bf2ce3cc19532fe084005a4 (patch)
tree0a4969e2aaec0b417721b58aa4e722ce702134a0
parentf695c5f952f28bf4ba74a7862ae20bae27568770 (diff)
dt-bindings: mmc: cdns: Add AMD Pensando Elba SoC
AMD Pensando Elba ARM 64-bit SoC is integrated with this IP and explicitly controls byte-lane enables. Signed-off-by: Brad Larson <blarson@amd.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230410184526.15990-3-blarson@amd.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml27
1 files changed, 23 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
index adacd0535c14..6c40611405a0 100644
--- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
@@ -9,19 +9,18 @@ title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
-allOf:
- - $ref: mmc-controller.yaml
-
properties:
compatible:
items:
- enum:
+ - amd,pensando-elba-sd4hc
- microchip,mpfs-sd4hc
- socionext,uniphier-sd4hc
- const: cdns,sd4hc
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
interrupts:
maxItems: 1
@@ -120,6 +119,26 @@ required:
- interrupts
- clocks
+allOf:
+ - $ref: mmc-controller.yaml
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: amd,pensando-elba-sd4hc
+ then:
+ properties:
+ reg:
+ items:
+ - description: Host controller registers
+ - description: Elba byte-lane enable register for writes
+ required:
+ - resets
+ else:
+ properties:
+ reg:
+ maxItems: 1
+
unevaluatedProperties: false
examples: