diff options
| author | Stephan Gerhold <stephan.gerhold@linaro.org> | 2025-07-09 12:08:55 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-07-16 23:16:15 -0500 |
| commit | 92640a6d4a4f59137867b7025d54cbbf7f23f89e (patch) | |
| tree | de5cb494c3ea6f6241ce0c17b830d5694a3d2305 | |
| parent | b7b0799f0d9f4c6f5ca8b1ee63bc9e961a326f9c (diff) | |
clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100
X1E80100 videocc is identical to the one in SM8550, aside from slightly
different recommended PLL frequencies. Add the separate frequency tables
for that and apply them if the qcom,x1e80100-videocc compatible is used.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-3-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | drivers/clk/qcom/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/clk/qcom/videocc-sm8550.c | 29 |
2 files changed, 30 insertions, 1 deletions
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index aac2e090a1ed..f153ecb3f836 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1429,7 +1429,7 @@ config SM_VIDEOCC_8550 select QCOM_GDSC help Support for the video clock controller on Qualcomm Technologies, Inc. - SM8550 or SM8650 devices. + SM8550 or SM8650 or X1E80100 devices. Say Y if you want to support video devices and functionality such as video encode/decode. diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index 3e5891b43ee4..32a6505abe26 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -145,6 +145,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_x1e80100[] = { + F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1443000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs0_clk_src = { .cmd_rcgr = 0x8000, .mnd_width = 0, @@ -177,6 +187,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_x1e80100[] = { + F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs1_clk_src = { .cmd_rcgr = 0x8018, .mnd_width = 0, @@ -559,12 +578,22 @@ static const struct qcom_cc_desc video_cc_sm8550_desc = { static const struct of_device_id video_cc_sm8550_match_table[] = { { .compatible = "qcom,sm8550-videocc" }, { .compatible = "qcom,sm8650-videocc" }, + { .compatible = "qcom,x1e80100-videocc" }, { } }; MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table); static int video_cc_sm8550_probe(struct platform_device *pdev) { + if (of_device_is_compatible(pdev->dev.of_node, "qcom,x1e80100-videocc")) { + video_cc_pll0_config.l = 0x1e; + video_cc_pll0_config.alpha = 0x0000; + video_cc_pll1_config.l = 0x2b; + video_cc_pll1_config.alpha = 0xc000; + video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_x1e80100; + video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_x1e80100; + } + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) { video_cc_pll0_config.l = 0x1e; video_cc_pll0_config.alpha = 0xa000; |