diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-02-12 01:19:36 +0200 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2025-03-04 15:39:35 +0100 |
| commit | d4ca1a8b334c69c26fb957b3f07f198f3c24adcc (patch) | |
| tree | db863c12a932c497915fc4e4c8a4aa905f55197f | |
| parent | dcf9969259616435ef3197d0f8f2f1b0bcfbb1da (diff) | |
drm/i915: Reoder CHV EU/slice fuse bits
We customarily define the bits of a register in big endian
order. Reorder the CHV fuse bits to match.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-9-ville.syrjala@linux.intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt_regs.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 443849f6c9ed..ab0896335459 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -937,10 +937,10 @@ #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) -#define CHV_SS_PG_ENABLE REG_BIT(1) -#define CHV_EU08_PG_ENABLE REG_BIT(9) -#define CHV_EU19_PG_ENABLE REG_BIT(17) #define CHV_EU210_PG_ENABLE REG_BIT(25) +#define CHV_EU19_PG_ENABLE REG_BIT(17) +#define CHV_EU08_PG_ENABLE REG_BIT(9) +#define CHV_SS_PG_ENABLE REG_BIT(1) #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) #define CHV_EU311_PG_ENABLE REG_BIT(1) @@ -1440,12 +1440,12 @@ #define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) -#define CHV_FGT_DISABLE_SS0 REG_BIT(10) -#define CHV_FGT_DISABLE_SS1 REG_BIT(11) -#define CHV_FGT_EU_DIS_SS0_R0_MASK REG_GENMASK(19, 16) -#define CHV_FGT_EU_DIS_SS0_R1_MASK REG_GENMASK(23, 20) -#define CHV_FGT_EU_DIS_SS1_R0_MASK REG_GENMASK(27, 24) #define CHV_FGT_EU_DIS_SS1_R1_MASK REG_GENMASK(31, 28) +#define CHV_FGT_EU_DIS_SS1_R0_MASK REG_GENMASK(27, 24) +#define CHV_FGT_EU_DIS_SS0_R1_MASK REG_GENMASK(23, 20) +#define CHV_FGT_EU_DIS_SS0_R0_MASK REG_GENMASK(19, 16) +#define CHV_FGT_DISABLE_SS1 REG_BIT(11) +#define CHV_FGT_DISABLE_SS0 REG_BIT(10) #define BCS_SWCTRL _MMIO(0x22200) #define BCS_SRC_Y REG_BIT(0) |