diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-10-14 10:50:20 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-10-14 10:50:20 +0200 |
| commit | daa5a9bc67f31b77649d885cf5f64d542c0524fd (patch) | |
| tree | 509b76d68ec09a0c9eb92a33ac7b04cdb82ad7f2 | |
| parent | 6a636d203cc8d29ae73116bbca8b0ea2c7a90d7f (diff) | |
| parent | c510368bce39cbaf4cb66f4acf788f5efa8692a6 (diff) | |
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag5' into renesas-clk-for-v6.19
Renesas RZ/G3E USB2 PHY Core Clock DT Binding Definitions
USB2 PHY core clock DT binding definitions for the Renesas RZ/G3E
(R9A09G047) SoC, shared by driver and DT source files.
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h index f165df8a6f5a..dab24740de3c 100644 --- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -22,5 +22,7 @@ #define R9A09G047_GBETH_1_CLK_PTP_REF_I 11 #define R9A09G047_USB3_0_REF_ALT_CLK_P 12 #define R9A09G047_USB3_0_CLKCORE 13 +#define R9A09G047_USB2_0_CLK_CORE0 14 +#define R9A09G047_USB2_0_CLK_CORE1 15 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ |