diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-08 11:37:13 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-29 11:51:35 +0200 |
| commit | e8b655803da2cc0f27834c5ec931521dba831b95 (patch) | |
| tree | 1290a4a5b555c9c70c9ccb531c1de5cfa73d42d1 | |
| parent | ebeb40c77b3c3d19a96b92e067dd8161916a56d6 (diff) | |
arm64: dts: renesas: r8a774a1: Add missing iommus properties
Add missing iommus properties to SDHI and Frame Compression Processor
device nodes that still lack them.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/114e9915356670e59dae412c1054afad4ce4c964.1720430758.git.geert+renesas@glider.be
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 1dbf9d56c68d..f065ee90649a 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2277,6 +2277,7 @@ max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 314>; + iommus = <&ipmmu_ds1 32>; status = "disabled"; }; @@ -2290,6 +2291,7 @@ max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 313>; + iommus = <&ipmmu_ds1 33>; status = "disabled"; }; @@ -2303,6 +2305,7 @@ max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 312>; + iommus = <&ipmmu_ds1 34>; status = "disabled"; }; @@ -2316,6 +2319,7 @@ max-frequency = <200000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 311>; + iommus = <&ipmmu_ds1 35>; status = "disabled"; }; @@ -2464,6 +2468,7 @@ clocks = <&cpg CPG_MOD 615>; power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 615>; + iommus = <&ipmmu_vc0 16>; }; fcpvb0: fcp@fe96f000 { @@ -2472,6 +2477,7 @@ clocks = <&cpg CPG_MOD 607>; power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 607>; + iommus = <&ipmmu_vi0 5>; }; fcpvd0: fcp@fea27000 { |