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authorJacky Chou <jacky_chou@aspeedtech.com>2025-07-09 15:08:06 +0800
committerJakub Kicinski <kuba@kernel.org>2025-07-10 18:13:48 -0700
commitfc6c8af6d784961b7f19bf0870baa1cdab5f7ad5 (patch)
tree286185f04d665d1302a9722dcd22ac3bef80311f
parent380a8891fdcb4e81bc30074c497e6892a827eb2a (diff)
dt-bindings: net: ftgmac100: Add resets property
In Aspeed AST2600 design, the MAC internal delay on MAC register cannot fully reset the RMII interfaces, it may cause the RMII incompletely. Therefore, we need to add resets property to do SoC-level reset line to reset the whole MAC function that includes ftgmac, RGMII and RMII. Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250709070809.2560688-2-jacky_chou@aspeedtech.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml21
1 files changed, 18 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml
index 55d6a8379025..d14410018bcf 100644
--- a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml
+++ b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml
@@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Faraday Technology FTGMAC100 gigabit ethernet controller
-allOf:
- - $ref: ethernet-controller.yaml#
-
maintainers:
- Po-Yu Chuang <ratbert@faraday-tech.com>
@@ -35,6 +32,9 @@ properties:
- description: MAC IP clock
- description: RMII RCLK gate for AST2500/2600
+ resets:
+ maxItems: 1
+
clock-names:
minItems: 1
items:
@@ -74,6 +74,21 @@ required:
- reg
- interrupts
+allOf:
+ - $ref: ethernet-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - aspeed,ast2600-mac
+ then:
+ properties:
+ resets: true
+ else:
+ properties:
+ resets: false
+
unevaluatedProperties: false
examples: