diff options
| author | H. Peter Anvin <hpa@linux.intel.com> | 2014-10-24 13:26:37 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2014-10-24 13:26:37 -0700 |
| commit | db65bcfd9563a7531c3dd46c350565705be1fd84 (patch) | |
| tree | ff7b068472764e36ab02a739917e206dd11d6b46 /arch/mips/include/asm/cpu-features.h | |
| parent | b47dcbdc5161d3d5756f430191e2840d9b855492 (diff) | |
| parent | f114040e3ea6e07372334ade75d1ee0775c355e1 (diff) | |
Merge tag 'v3.18-rc1' into x86/urgent
Reason:
Need to apply audit patch on top of v3.18-rc1.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index e079598ae051..3325f3eb248c 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -231,6 +231,16 @@ #define cpu_has_clo_clz cpu_has_mips_r #endif +/* + * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. + * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. + * This indicates the availability of WSBH and in case of 64 bit CPUs also + * DSBH and DSHD. + */ +#ifndef cpu_has_wsbh +#define cpu_has_wsbh cpu_has_mips_r2 +#endif + #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif |