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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-12-16 16:57:55 -0800 | 
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-12-16 16:57:55 -0800 | 
| commit | dde0672bfa3e5c5e8530ebb45518408acb91b083 (patch) | |
| tree | b85f9eb7184245dd65b522f1b32f3974cdefd2e1 /net/lapb/lapb_out.c | |
| parent | 3b8a9b2e6809d281890dd0a1102dc14d2cd11caf (diff) | |
| parent | 8defec031c40913ef10d2f654a5ccc8a2a9730c1 (diff) | |
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
 "A handful of clk fixes, mostly in the rockchip clk driver:
   - Fix a clk name, clk parent, and a register for a clk gate in the
     Rockchip rk3128 clk driver
   - Add a PLL frequency on Rockchip rk3568 to fix some display
     artifacts
   - Fix a kbuild dependency for Qualcomm's SM_CAMCC_8550 symbol so that
     it isn't possible to select the associated GCC driver"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name
  clk: rockchip: rk3128: Fix aclk_peri_src's parent
  clk: qcom: Fix SM_CAMCC_8550 dependencies
  clk: rockchip: rk3128: Fix HCLK_OTG gate register
  clk: rockchip: rk3568: Add PLL rate for 292.5MHz
Diffstat (limited to 'net/lapb/lapb_out.c')
0 files changed, 0 insertions, 0 deletions
