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author | Maxime Chevallier <maxime.chevallier@bootlin.com> | 2022-09-02 10:32:04 +0200 |
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committer | David S. Miller <davem@davemloft.net> | 2022-09-05 10:16:53 +0100 |
commit | fef2998203e17e4298843afb2056fbed44611734 (patch) | |
tree | e0d940703332e6d75ec40061b1f858bc05275c6f /scripts/bpf_doc.py | |
parent | 4a502cf4d77e12119e7061a05d5789cd3129d185 (diff) |
net: altera: tse: convert to phylink
Convert the Altera Triple Speed Ethernet Controller to phylink.
This controller supports MII, GMII and RGMII with its MAC, and
SGMII + 1000BaseX through a small embedded PCS.
The PCS itself has a register set very similar to what is found in a
typical 802.3 ethernet PHY, but this register set memory-mapped instead
of lying on an mdio bus.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'scripts/bpf_doc.py')
0 files changed, 0 insertions, 0 deletions