diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2025-08-01 13:59:07 -0700 | 
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2025-08-01 13:59:07 -0700 | 
| commit | 0bd0a41a5120f78685a132834865b0a631b9026a (patch) | |
| tree | 443c2523ad75bcc00e415e73b9068cdf104e10ac /scripts/checktransupdate.py | |
| parent | 877d94c74e4c6665d2af55c0154363b43b947e60 (diff) | |
| parent | 58d2b6b6b214d8b4914cd4c821a8bd0c75436c2c (diff) | |
Merge tag 'pci-v6.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull PCI updates from Bjorn Helgaas:
 "Enumeration:
   - Allow built-in drivers, not just modular drivers, to use async
     initial probing (Lukas Wunner)
   - Support Immediate Readiness even on devices with no PM Capability
     (Sean Christopherson)
   - Consolidate definition of PCIE_RESET_CONFIG_WAIT_MS (100ms), the
     required delay between a reset and sending config requests to a
     device (Niklas Cassel)
   - Add pci_is_display() to check for "Display" base class and use it
     in ALSA hda, vfio, vga_switcheroo, vt-d (Mario Limonciello)
   - Allow 'isolated PCI functions' (multi-function devices without a
     function 0) for LoongArch, similar to s390 and jailhouse (Huacai
     Chen)
  Power control:
   - Add ability to enable optional slot clock for cases where the PCIe
     host controller and the slot are supplied by different clocks
     (Marek Vasut)
  PCIe native device hotplug:
   - Fix runtime PM ref imbalance on Hot-Plug Capable ports caused by
     misinterpreting a config read failure after a device has been
     removed (Lukas Wunner)
   - Avoid creating a useless PCIe port service device for pciehp if the
     slot is handled by the ACPI hotplug driver (Lukas Wunner)
   - Ignore ACPI hotplug slots when calculating depth of pciehp hotplug
     ports (Lukas Wunner)
  Virtualization:
   - Save VF resizable BAR state and restore it after reset (Michał
     Winiarski)
   - Allow IOV resources (VF BARs) to be resized (Michał Winiarski)
   - Add pci_iov_vf_bar_set_size() so drivers can control VF BAR size
     (Michał Winiarski)
  Endpoint framework:
   - Add RC-to-EP doorbell support using platform MSI controller,
     including a test case (Frank Li)
   - Allow BAR assignment via configfs so platforms have flexibility in
     determining BAR usage (Jerome Brunet)
  Native PCIe controller drivers:
   - Convert amazon,al-alpine-v[23]-pcie, apm,xgene-pcie,
     axis,artpec6-pcie, marvell,armada-3700-pcie, st,spear1340-pcie to
     DT schema format (Rob Herring)
   - Use dev_fwnode() instead of of_fwnode_handle() to remove OF
     dependency in altera (fixes an unused variable), designware-host,
     mediatek, mediatek-gen3, mobiveil, plda, xilinx, xilinx-dma,
     xilinx-nwl (Jiri Slaby, Arnd Bergmann)
   - Convert aardvark, altera, brcmstb, designware-host, iproc,
     mediatek, mediatek-gen3, mobiveil, plda, rcar-host, vmd, xilinx,
     xilinx-dma, xilinx-nwl from using pci_msi_create_irq_domain() to
     using msi_create_parent_irq_domain() instead; this makes the
     interrupt controller per-PCI device, allows dynamic allocation of
     vectors after initialization, and allows support of IMS (Nam Cao)
  APM X-Gene PCIe controller driver:
   - Rewrite MSI handling to MSI CPU affinity, drop useless CPU hotplug
     bits, use device-managed memory allocations, and clean things up
     (Marc Zyngier)
   - Probe xgene-msi as a standard platform driver rather than a
     subsys_initcall (Marc Zyngier)
  Broadcom STB PCIe controller driver:
   - Add optional DT 'num-lanes' property and if present, use it to
     override the Maximum Link Width advertised in Link Capabilities
     (Jim Quinlan)
  Cadence PCIe controller driver:
   - Use PCIe Message routing types from the PCI core rather than
     defining private ones (Hans Zhang)
  Freescale i.MX6 PCIe controller driver:
   - Add IMX8MQ_EP third 64-bit BAR in epc_features (Richard Zhu)
   - Add IMX8MM_EP and IMX8MP_EP fixed 256-byte BAR 4 in epc_features
     (Richard Zhu)
   - Configure LUT for MSI/IOMMU in Endpoint mode so Root Complex can
     trigger doorbel on Endpoint (Frank Li)
   - Remove apps_reset (LTSSM_EN) from
     imx_pcie_{assert,deassert}_core_reset(), which fixes a hotplug
     regression on i.MX8MM (Richard Zhu)
   - Delay Endpoint link start until configfs 'start' written (Richard
     Zhu)
  Intel VMD host bridge driver:
   - Add Intel Panther Lake (PTL)-H/P/U Vendor ID (George D Sworo)
  Qualcomm PCIe controller driver:
   - Add DT binding and driver support for SA8255p, which supports ECAM
     for Configuration Space access (Mayank Rana)
   - Update DT binding and driver to describe PHYs and per-Root Port
     resets in a Root Port stanza and deprecate describing them in the
     host bridge; this makes it possible to support multiple Root Ports
     in the future (Krishna Chaitanya Chundru)
   - Add Qualcomm QCS615 to SM8150 DT binding (Ziyue Zhang)
   - Add Qualcomm QCS8300 to SA8775p DT binding (Ziyue Zhang)
   - Drop TBU and ref clocks from Qualcomm SM8150 and SC8180x DT
     bindings (Konrad Dybcio)
   - Document 'link_down' reset in Qualcomm SA8775P DT binding (Ziyue
     Zhang)
   - Add required PCIE_RESET_CONFIG_WAIT_MS delay after Link up IRQ
     (Niklas Cassel)
  Rockchip PCIe controller driver:
   - Drop unused PCIe Message routing and code definitions (Hans Zhang)
   - Remove several unused header includes (Hans Zhang)
   - Use standard PCIe config register definitions instead of
     rockchip-specific redefinitions (Geraldo Nascimento)
   - Set Target Link Speed to 5.0 GT/s before retraining so we have a
     chance to train at a higher speed (Geraldo Nascimento)
  Rockchip DesignWare PCIe controller driver:
   - Prevent race between link training and register update via DBI by
     inhibiting link training after hot reset and link down (Wilfred
     Mallawa)
   - Add required PCIE_RESET_CONFIG_WAIT_MS delay after Link up IRQ
     (Niklas Cassel)
  Sophgo PCIe controller driver:
   - Add DT binding and driver for Sophgo SG2044 PCIe controller driver
     in Root Complex mode (Inochi Amaoto)
  Synopsys DesignWare PCIe controller driver:
   - Add required PCIE_RESET_CONFIG_WAIT_MS after waiting for Link up on
     Ports that support > 5.0 GT/s. Slower Ports still rely on the
     not-quite-correct PCIE_LINK_WAIT_SLEEP_MS 90ms default delay while
     waiting for the Link (Niklas Cassel)"
* tag 'pci-v6.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (116 commits)
  dt-bindings: PCI: qcom,pcie-sa8775p: Document 'link_down' reset
  dt-bindings: PCI: Remove 83xx-512x-pci.txt
  dt-bindings: PCI: Convert amazon,al-alpine-v[23]-pcie to DT schema
  dt-bindings: PCI: Convert marvell,armada-3700-pcie to DT schema
  dt-bindings: PCI: Convert apm,xgene-pcie to DT schema
  dt-bindings: PCI: Convert axis,artpec6-pcie to DT schema
  dt-bindings: PCI: Convert st,spear1340-pcie to DT schema
  PCI: Move is_pciehp check out of pciehp_is_native()
  PCI: pciehp: Use is_pciehp instead of is_hotplug_bridge
  PCI/portdrv: Use is_pciehp instead of is_hotplug_bridge
  PCI/ACPI: Fix runtime PM ref imbalance on Hot-Plug Capable ports
  selftests: pci_endpoint: Add doorbell test case
  misc: pci_endpoint_test: Add doorbell test case
  PCI: endpoint: pci-epf-test: Add doorbell test support
  PCI: endpoint: Add pci_epf_align_inbound_addr() helper for inbound address alignment
  PCI: endpoint: pci-ep-msi: Add checks for MSI parent and mutability
  PCI: endpoint: Add RC-to-EP doorbell support using platform MSI controller
  PCI: dwc: Add Sophgo SG2044 PCIe controller driver in Root Complex mode
  PCI: vmd: Switch to msi_create_parent_irq_domain()
  PCI: vmd: Convert to lock guards
  ...
Diffstat (limited to 'scripts/checktransupdate.py')
0 files changed, 0 insertions, 0 deletions
