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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2016-11-08 18:22:11 -0200 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2016-11-14 13:20:22 -0200 |
| commit | 2ef32dee97fcf41987722a37eb6ff1a983915e99 (patch) | |
| tree | 9922dd59e409dd73eee43e3a845d790a1fb670ce /scripts/gdb/linux/lists.py | |
| parent | 7a17995a3dc8613f778a9e2fd20e870f17789544 (diff) | |
drm/i915/gen9: fix the WM memory bandwidth WA for Y tiling cases
The previous spec version said "double Ytile planes minimum lines",
and I interpreted this as referring to what the spec calls "Y tile
minimum", but in fact it was referring to what the spec calls "Minimum
Scanlines for Y tile". I noticed that Mahesh Kumar had a different
interpretation, so I sent and email to the spec authors and got
clarification on the correct meaning. Also, BSpec was updated and
should be clear now.
Fixes: ee3d532fcb64 ("drm/i915/gen9: unconditionally apply the memory bandwidth WA")
Cc: stable@vger.kernel.org
Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1478636531-6081-1-git-send-email-paulo.r.zanoni@intel.com
Diffstat (limited to 'scripts/gdb/linux/lists.py')
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