arm64: dts: renesas: sparrow-hawk: Describe split PCIe clock

The Sparrow Hawk board supplies the PCIe controller input clock and PCIe
bus clock from separate outputs of the Renesas 9FGV0441 clock generator.
Describe this split bus configuration in the board DT.
The topology looks as follows:

     ____________                    _____________
    | R-Car PCIe |                  | PCIe device |
    |            |                  |             |
    |    PCIe RX<|==================|>PCIe TX     |
    |    PCIe TX<|==================|>PCIe RX     |
    |            |                  |             |
    |   PCIe CLK<|======..  ..======|>PCIe CLK    |
    '------------'      ||  ||      '-------------'
			||  ||
     ____________       ||  ||
    |  9FGV0441  |      ||  ||
    |            |      ||  ||
    |   CLK DIF0<|======''  ||
    |   CLK DIF1<|==========''
    |   CLK DIF2<|
    |   CLK DIF3<|
    '------------'

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://lore.kernel.org/20250607194541.79176-3-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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