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| author | Tim Harvey <tharvey@gateworks.com> | 2025-07-07 13:16:57 -0700 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2025-07-11 16:34:33 +0800 |
| commit | 81b07d51cda761eecc36bed907a1c88d2adeb689 (patch) | |
| tree | 7c3ca918910cdd578823c34ad229f74c907b38b6 /scripts/gdb/linux/proc.py | |
| parent | c5d9a362c737ec444fcea44c270d28b04a723003 (diff) | |
arm64: dts: imx8mp-venice-gw702x: Increase HS400 USDHC clock speed
The IMX8M reference manuals indicate in the USDHC Clock generator section
that the clock rate for DDR is 1/2 the input clock therefore HS400 rates
clocked at 200Mhz require a 400Mhz SDHC clock.
This showed about a 1.5x improvement in read performance for the eMMC's
used on the various imx8mp-venice boards.
Fixes: 0d5b288c2110 ("arm64: dts: freescale: Add imx8mp-venice-gw7905-2x")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/proc.py')
0 files changed, 0 insertions, 0 deletions