summaryrefslogtreecommitdiff
path: root/scripts/gdb/linux/utils.py
diff options
context:
space:
mode:
authorMathis Foerst <mathis.foerst@mt.com>2025-05-22 16:35:06 +0200
committerHans Verkuil <hverkuil@xs4all.nl>2025-06-30 08:47:40 +0200
commit208119b4a116d2fa708ee4bbe4e12dfd26f03309 (patch)
treef3311cd23c8d1f8afb3e56e3e52b050ad0ebcb9b /scripts/gdb/linux/utils.py
parent3bd71a34baf620b2a85b5b63255a07a4ab194da0 (diff)
media: mt9m114: Bypass PLL if required
The MT9M114 sensor has an internal PLL that generates the required SYSCLK from EXTCLK. It also has the option to bypass the PLL and use EXTCLK directly as SYSCLK. The current driver implementation uses a hardcoded PLL configuration that requires a specific EXTCLK frequency. Depending on the available clocks, it can be desirable to use a different PLL configuration or to bypass it. The link-frequency of the output bus (Parallel or MIPI-CSI) is configured in the device tree. Check if EXTCLK can be used as SYSCLK to achieve this link-frequency. If yes, bypass the PLL. Otherwise, (as before) check if EXTCLK and the default PLL configuration provide the required SYSCLK to achieve the link-frequency. If yes, use the PLL. If no, throw an error. Signed-off-by: Mathis Foerst <mathis.foerst@mt.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions