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| author | Yang Yingliang <yangyingliang@huawei.com> | 2022-10-18 10:31:48 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-11-09 22:01:31 +0000 |
| commit | 756344e7cb1afbb87da8705c20384dddd0dea233 (patch) | |
| tree | 5cf47a2399cd9df46d3a1981731226f490cbc1f1 /scripts/gdb/linux/utils.py | |
| parent | 73e770f085023da327dc9ffeb6cd96b0bb22d97e (diff) | |
soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()
Add missing free_irq() before return error from sifive_ccache_init().
Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions