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author | Matthew Gerlach <matthew.gerlach@altera.com> | 2025-06-25 08:14:42 -0700 |
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committer | Dinh Nguyen <dinguyen@kernel.org> | 2025-07-12 07:24:48 -0500 |
commit | 203b862057d08fbabcd4e475707751c0f2a9258b (patch) | |
tree | b7cc1db5a2bb7fc907eba839029fcd4e4a3ec827 /scripts/gdb/linux/xarray.py | |
parent | 1dfe3ca86a9c43e2e49be6c4235b3170c5059e46 (diff) |
arm64: dts: altera: socfpga_stratix10: update internal oscillators
Add the clock-frequency property to the cb_intosc_ls_clk and
cb_intosc_hs_div2_clk device tree nodes.
The f2s_free_clk is implemented by custom logic in the FPGA; so it
should be disabled in the dtsi by default and enabled by a
dts for a specific FPGA design on a specific board.
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/xarray.py')
0 files changed, 0 insertions, 0 deletions