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authorYannic Moog <y.moog@phytec.de>2025-04-17 14:01:13 +0200
committerShawn Guo <shawnguo@kernel.org>2025-05-09 16:59:33 +0800
commit95727d056c8f5cad668c1f5711b25102b474216f (patch)
tree9b731343964234a1ee8f67e817d98bde9bd5d13d /tools/perf/scripts/python/export-to-postgresql.py
parent6e94adb40a8a24a4cc54459a13b6ca0de8f2fd04 (diff)
arm64: dts: add imx8mp-libra-rdk-fpsc board
Add device tree for the Libra-i.MX 8M Plus FPSC board. The Libra is a pure development board and has hardware to support FPSC-24-A.0 set of features. It can be populated with the phyCORE-i.MX 8M Plus SoM to form a SBC. The phyCORE-i.MX 8M Plus FPSC [1] SoM uses only a subset of the hardware features the Libra board provides. The phyCORE-i.MX8MP FPSC itself is a System on Module based on the i.MX 8M Plus SoC utilizing the Future Proof Solder Core [2] standard. To be able to easily map FPSC interface names to SoC interfaces, the FPSC interface names are added as inline comments. Example: &i2c5 { /* FPSC I2C4 */ pinctrl-0 = <&pinctrl_i2c5>; [...] }; Here, I2C4 is the FPSC interface name. The i2c5 instance of the i.MX 8M Plus SoC is used to fulfill the i2c functionality and its signals are routed to the FPSC I2C4 signal pins: pinctrl_i2c5: i2c5grp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 /* I2C4_SDA */ MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 /* I2C4_SCL */ >; }; The features are almost identical to the existing phyCORE-i.MX 8M Plus SoM (dts: imx8mp-phycore-som.dtsi), but the pin muxing is different due to the FPSC standard as well as 1.8V IO voltage instead of 3.3V. [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/ [2] https://www.phytec.eu/en/produkte/system-on-modules/fpsc/ Signed-off-by: Yannic Moog <y.moog@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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