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| author | George Shen <George.Shen@amd.com> | 2022-06-02 11:10:25 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-10-06 12:02:32 -0400 |
| commit | f638fe27b817c755e017b8a6ae4b9b4224461941 (patch) | |
| tree | f4298dc29e078382dd669ddf20bbb614bc4fc713 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | fe674c0b6f5382b7c377ca2c418c26dd78b428b4 (diff) | |
drm/amd/display: Add missing SDP registers to DCN32 reglist
[Why]
Certain features require the additional DP SDP configuration registers
DP_SEC_CNTL1 and DP_SEC_CNTL5 in order to function correctly.
The DCN32 DIO stream encoder reglist is currently missing these two
registers.
[How]
Add the missing registers to the DCN32 DIO stream encoder reglist.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: George Shen <George.Shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions