diff options
| author | Zhang Rui <rui.zhang@intel.com> | 2022-08-20 18:11:21 +0800 |
|---|---|---|
| committer | Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> | 2023-03-22 13:36:47 -0700 |
| commit | 7c7e7c0d396b99d5b41d052dbf2b2bddcd5f7f3c (patch) | |
| tree | fc417b22363928d59f8db5ee2be786b1a8136f2e /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 6f561677c2f234bcf215350b76f2a2fea95fbebf (diff) | |
tools/power/x86/intel-speed-select: Unify TRL levels
TRL supports different levels including SSE/AVX2/AVX512.
Avoid using hardcoded level name and structure fields, so that a loop can
be used to parse each TRL level instead. This reduces several lines of
source code.
No functional changes are expected.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
[srinivas.pandruvada@linux.intel.com: changelog edits]
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions