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| author | Kuogee Hsieh <quic_khsieh@quicinc.com> | 2023-05-25 10:40:49 -0700 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-06-04 05:02:43 +0300 |
| commit | 12cef323c903bd8b13d1f6ff24a9695c2cdc360b (patch) | |
| tree | 3a4f8c13ba6f0cd1564d6723d9789de709f43696 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 5fe0faa62461adb578785169f29f3c4638ca4e9a (diff) | |
drm/msm/dpu: set DSC flush bit correctly at MDP CTL flush register
The CTL_FLUSH register should be programmed with the 22th bit
(DSC_IDX) to flush the DSC hardware blocks, not the literal value of
22 (which corresponds to flushing VIG1, VIG2 and RGB1 instead).
Changes in V12:
-- split this patch out of "separate DSC flush update out of interface"
Changes in V13:
-- rewording the commit text
Changes in V14:
-- drop 'DSC" from "The DSC CTL_FLUSH register" at commit text
Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl")
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/539496/
Link: https://lore.kernel.org/r/1685036458-22683-2-git-send-email-quic_khsieh@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions