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-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml55
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml52
-rw-r--r--drivers/clk/rockchip/Kconfig14
-rw-r--r--drivers/clk/rockchip/Makefile2
-rw-r--r--drivers/clk/rockchip/clk-cpu.c165
-rw-r--r--drivers/clk/rockchip/clk-rk3506.c869
-rw-r--r--drivers/clk/rockchip/clk-rk3568.c5
-rw-r--r--drivers/clk/rockchip/clk-rv1126b.c1117
-rw-r--r--drivers/clk/rockchip/clk.c24
-rw-r--r--drivers/clk/rockchip/clk.h96
-rw-r--r--drivers/clk/rockchip/rst-rk3506.c226
-rw-r--r--drivers/clk/rockchip/rst-rv1126b.c443
-rw-r--r--include/dt-bindings/clock/rk3568-cru.h6
-rw-r--r--include/dt-bindings/clock/rockchip,rk3506-cru.h285
-rw-r--r--include/dt-bindings/clock/rockchip,rv1126b-cru.h392
-rw-r--r--include/dt-bindings/reset/rockchip,rk3506-cru.h211
-rw-r--r--include/dt-bindings/reset/rockchip,rv1126b-cru.h405
17 files changed, 4365 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml
new file mode 100644
index 000000000000..ca940475336c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3506 Clock and Reset Unit (CRU)
+
+maintainers:
+ - Finley Xiao <finley.xiao@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description:
+ The RK3506 CRU generates the clock and also implements reset for SoC
+ peripherals.
+
+properties:
+ compatible:
+ const: rockchip,rk3506-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@ff9a0000 {
+ compatible = "rockchip,rk3506-cru";
+ reg = <0xff9a0000 0x20000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&xin24m>;
+ clock-names = "xin";
+ };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
new file mode 100644
index 000000000000..04b0a5c51e4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1126b-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RV1126B Clock and Reset Unit
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description:
+ The rv1126b clock controller generates the clock and also implements a
+ reset controller for SoC peripherals.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rv1126b-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@20000000 {
+ compatible = "rockchip,rv1126b-cru";
+ reg = <0x20000000 0xc0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index febb7944f34b..5cf1e0fd6fb3 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -30,6 +30,13 @@ config CLK_RV1126
help
Build the driver for RV1126 Clock Driver.
+config CLK_RV1126B
+ bool "Rockchip RV1126B clock controller support"
+ depends on ARM64 || COMPILE_TEST
+ default y
+ help
+ Build the driver for RV1126B Clock Driver.
+
config CLK_RK3036
bool "Rockchip RK3036 clock controller support"
depends on ARM || COMPILE_TEST
@@ -93,6 +100,13 @@ config CLK_RK3399
help
Build the driver for RK3399 Clock Driver.
+config CLK_RK3506
+ bool "Rockchip RK3506 clock controller support"
+ depends on ARM || COMPILE_TEST
+ default y
+ help
+ Build the driver for RK3506 Clock Driver.
+
config CLK_RK3528
bool "Rockchip RK3528 clock controller support"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index c281a9738d9f..4d8cbb2044c7 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -20,6 +20,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-$(CONFIG_CLK_PX30) += clk-px30.o
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
+obj-$(CONFIG_CLK_RV1126B) += clk-rv1126b.o rst-rv1126b.o
obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
@@ -29,6 +30,7 @@ obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
+obj-$(CONFIG_CLK_RK3506) += clk-rk3506.o rst-rk3506.o
obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o rst-rk3528.o
obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o rst-rk3562.o
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index dcc9dcb597ae..6e91a3041a03 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -396,3 +396,168 @@ free_cpuclk:
kfree(cpuclk);
return ERR_PTR(ret);
}
+
+static int rockchip_cpuclk_multi_pll_pre_rate_change(struct rockchip_cpuclk *cpuclk,
+ struct clk_notifier_data *ndata)
+{
+ unsigned long new_rate = roundup(ndata->new_rate, 1000);
+ const struct rockchip_cpuclk_rate_table *rate;
+ unsigned long flags;
+
+ rate = rockchip_get_cpuclk_settings(cpuclk, new_rate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for cpuclk\n",
+ __func__, new_rate);
+ return -EINVAL;
+ }
+
+ if (new_rate > ndata->old_rate) {
+ spin_lock_irqsave(cpuclk->lock, flags);
+ rockchip_cpuclk_set_dividers(cpuclk, rate);
+ spin_unlock_irqrestore(cpuclk->lock, flags);
+ }
+
+ return 0;
+}
+
+static int rockchip_cpuclk_multi_pll_post_rate_change(struct rockchip_cpuclk *cpuclk,
+ struct clk_notifier_data *ndata)
+{
+ unsigned long new_rate = roundup(ndata->new_rate, 1000);
+ const struct rockchip_cpuclk_rate_table *rate;
+ unsigned long flags;
+
+ rate = rockchip_get_cpuclk_settings(cpuclk, new_rate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for cpuclk\n",
+ __func__, new_rate);
+ return -EINVAL;
+ }
+
+ if (new_rate < ndata->old_rate) {
+ spin_lock_irqsave(cpuclk->lock, flags);
+ rockchip_cpuclk_set_dividers(cpuclk, rate);
+ spin_unlock_irqrestore(cpuclk->lock, flags);
+ }
+
+ return 0;
+}
+
+static int rockchip_cpuclk_multi_pll_notifier_cb(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct clk_notifier_data *ndata = data;
+ struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);
+ int ret = 0;
+
+ pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
+ __func__, event, ndata->old_rate, ndata->new_rate);
+ if (event == PRE_RATE_CHANGE)
+ ret = rockchip_cpuclk_multi_pll_pre_rate_change(cpuclk, ndata);
+ else if (event == POST_RATE_CHANGE)
+ ret = rockchip_cpuclk_multi_pll_post_rate_change(cpuclk, ndata);
+
+ return notifier_from_errno(ret);
+}
+
+struct clk *rockchip_clk_register_cpuclk_multi_pll(const char *name,
+ const char *const *parent_names,
+ u8 num_parents, void __iomem *base,
+ int muxdiv_offset, u8 mux_shift,
+ u8 mux_width, u8 mux_flags,
+ int div_offset, u8 div_shift,
+ u8 div_width, u8 div_flags,
+ unsigned long flags, spinlock_t *lock,
+ const struct rockchip_cpuclk_rate_table *rates,
+ int nrates)
+{
+ struct rockchip_cpuclk *cpuclk;
+ struct clk_hw *hw;
+ struct clk_mux *mux = NULL;
+ struct clk_divider *div = NULL;
+ const struct clk_ops *mux_ops = NULL, *div_ops = NULL;
+ int ret;
+
+ if (num_parents > 1) {
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ mux->reg = base + muxdiv_offset;
+ mux->shift = mux_shift;
+ mux->mask = BIT(mux_width) - 1;
+ mux->flags = mux_flags;
+ mux->lock = lock;
+ mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
+ : &clk_mux_ops;
+ }
+
+ if (div_width > 0) {
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div) {
+ ret = -ENOMEM;
+ goto free_mux;
+ }
+
+ div->flags = div_flags;
+ if (div_offset)
+ div->reg = base + div_offset;
+ else
+ div->reg = base + muxdiv_offset;
+ div->shift = div_shift;
+ div->width = div_width;
+ div->lock = lock;
+ div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
+ ? &clk_divider_ro_ops
+ : &clk_divider_ops;
+ }
+
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? &mux->hw : NULL, mux_ops,
+ div ? &div->hw : NULL, div_ops,
+ NULL, NULL, flags);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto free_div;
+ }
+
+ cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
+ if (!cpuclk) {
+ ret = -ENOMEM;
+ goto unregister_clk;
+ }
+
+ cpuclk->reg_base = base;
+ cpuclk->lock = lock;
+ cpuclk->clk_nb.notifier_call = rockchip_cpuclk_multi_pll_notifier_cb;
+ ret = clk_notifier_register(hw->clk, &cpuclk->clk_nb);
+ if (ret) {
+ pr_err("%s: failed to register clock notifier for %s\n",
+ __func__, name);
+ goto free_cpuclk;
+ }
+
+ if (nrates > 0) {
+ cpuclk->rate_count = nrates;
+ cpuclk->rate_table = kmemdup(rates,
+ sizeof(*rates) * nrates,
+ GFP_KERNEL);
+ if (!cpuclk->rate_table) {
+ ret = -ENOMEM;
+ goto free_cpuclk;
+ }
+ }
+
+ return hw->clk;
+
+free_cpuclk:
+ kfree(cpuclk);
+unregister_clk:
+ clk_hw_unregister_composite(hw);
+free_div:
+ kfree(div);
+free_mux:
+ kfree(mux);
+
+ return ERR_PTR(ret);
+}
diff --git a/drivers/clk/rockchip/clk-rk3506.c b/drivers/clk/rockchip/clk-rk3506.c
new file mode 100644
index 000000000000..dd59bd60382e
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3506.c
@@ -0,0 +1,869 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
+#include <dt-bindings/clock/rockchip,rk3506-cru.h>
+#include "clk.h"
+
+#define PVTPLL_SRC_SEL_PVTPLL (BIT(7) | BIT(23))
+
+enum rk3506_plls {
+ gpll, v0pll, v1pll,
+};
+
+/*
+ * [FRAC PLL]: GPLL, V0PLL, V1PLL
+ * - VCO Frequency: 950MHz to 3800MHZ
+ * - Output Frequency: 19MHz to 3800MHZ
+ * - refdiv: 1 to 63 (Int Mode), 1 to 2 (Frac Mode)
+ * - fbdiv: 16 to 3800 (Int Mode), 20 to 380 (Frac Mode)
+ * - post1div: 1 to 7
+ * - post2div: 1 to 7
+ */
+static struct rockchip_pll_rate_table rk3506_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1350000000, 4, 225, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137),
+ RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 3, 125, 1, 1, 1, 0),
+ RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355),
+ RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127),
+ RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185),
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(96000000, 1, 48, 6, 2, 1, 0),
+ { /* sentinel */ },
+};
+
+#define RK3506_DIV_ACLK_CORE_MASK 0xf
+#define RK3506_DIV_ACLK_CORE_SHIFT 9
+#define RK3506_DIV_PCLK_CORE_MASK 0xf
+#define RK3506_DIV_PCLK_CORE_SHIFT 0
+
+#define RK3506_CLKSEL15(_aclk_core_div) \
+{ \
+ .reg = RK3506_CLKSEL_CON(15), \
+ .val = HIWORD_UPDATE(_aclk_core_div, RK3506_DIV_ACLK_CORE_MASK, \
+ RK3506_DIV_ACLK_CORE_SHIFT), \
+}
+
+#define RK3506_CLKSEL16(_pclk_core_div) \
+{ \
+ .reg = RK3506_CLKSEL_CON(16), \
+ .val = HIWORD_UPDATE(_pclk_core_div, RK3506_DIV_PCLK_CORE_MASK, \
+ RK3506_DIV_PCLK_CORE_SHIFT), \
+}
+
+/* SIGN-OFF: aclk_core: 500M, pclk_core: 125M, */
+#define RK3506_CPUCLK_RATE(_prate, _aclk_core_div, _pclk_core_div) \
+{ \
+ .prate = _prate, \
+ .divs = { \
+ RK3506_CLKSEL15(_aclk_core_div), \
+ RK3506_CLKSEL16(_pclk_core_div), \
+ }, \
+}
+
+static struct rockchip_cpuclk_rate_table rk3506_cpuclk_rates[] __initdata = {
+ RK3506_CPUCLK_RATE(1608000000, 3, 12),
+ RK3506_CPUCLK_RATE(1512000000, 3, 12),
+ RK3506_CPUCLK_RATE(1416000000, 2, 11),
+ RK3506_CPUCLK_RATE(1296000000, 2, 10),
+ RK3506_CPUCLK_RATE(1200000000, 2, 9),
+ RK3506_CPUCLK_RATE(1179648000, 2, 9),
+ RK3506_CPUCLK_RATE(1008000000, 1, 7),
+ RK3506_CPUCLK_RATE(903168000, 1, 7),
+ RK3506_CPUCLK_RATE(800000000, 1, 6),
+ RK3506_CPUCLK_RATE(750000000, 1, 5),
+ RK3506_CPUCLK_RATE(589824000, 1, 4),
+ RK3506_CPUCLK_RATE(400000000, 1, 3),
+ RK3506_CPUCLK_RATE(200000000, 1, 1),
+};
+
+PNAME(mux_pll_p) = { "xin24m" };
+PNAME(gpll_v0pll_v1pll_parents_p) = { "gpll", "v0pll", "v1pll" };
+PNAME(gpll_v0pll_v1pll_g_parents_p) = { "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" };
+PNAME(gpll_v0pll_v1pll_div_parents_p) = { "clk_gpll_div", "clk_v0pll_div", "clk_v1pll_div" };
+PNAME(xin24m_gpll_v0pll_v1pll_g_parents_p) = { "xin24m", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" };
+PNAME(xin24m_g_gpll_v0pll_v1pll_g_parents_p) = { "xin24m_gate", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" };
+PNAME(xin24m_g_gpll_v0pll_v1pll_div_parents_p) = { "xin24m_gate", "clk_gpll_div", "clk_v0pll_div", "clk_v1pll_div" };
+PNAME(xin24m_400k_32k_parents_p) = { "xin24m", "clk_rc", "clk_32k" };
+PNAME(clk_frac_uart_matrix0_mux_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate" };
+PNAME(clk_timer0_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai0_mclk_in", "sai0_sclk_in" };
+PNAME(clk_timer1_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai1_mclk_in", "sai1_sclk_in" };
+PNAME(clk_timer2_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai2_mclk_in", "sai2_sclk_in" };
+PNAME(clk_timer3_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai3_mclk_in", "sai3_sclk_in" };
+PNAME(clk_timer4_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "mclk_asrc0" };
+PNAME(clk_timer5_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "mclk_asrc1" };
+PNAME(sclk_uart_parents_p) = { "xin24m", "clk_gpll_gate", "clk_v0pll_gate", "clk_frac_uart_matrix0", "clk_frac_uart_matrix1",
+ "clk_frac_common_matrix0", "clk_frac_common_matrix1", "clk_frac_common_matrix2" };
+PNAME(clk_mac_ptp_root_parents_p) = { "gpll", "v0pll", "v1pll" };
+PNAME(clk_pwm_parents_p) = { "clk_rc", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "sai0_sclk_in", "sai1_sclk_in",
+ "sai2_sclk_in", "sai3_sclk_in", "mclk_asrc0", "mclk_asrc1" };
+PNAME(clk_can_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate", "clk_frac_voice_matrix1",
+ "clk_frac_common_matrix0", "clk_frac_common_matrix1", "clk_frac_common_matrix2" };
+PNAME(clk_pdm_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2",
+ "clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1",
+ "clk_frac_common_matrix2", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "clk_gpll_div" };
+PNAME(mclk_sai_asrc_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2",
+ "clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1",
+ "clk_frac_common_matrix2", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in" };
+PNAME(lrck_asrc_parents_p) = { "mclk_asrc0", "mclk_asrc1", "mclk_asrc2", "mclk_asrc3", "mclk_spdiftx", "clk_spdifrx_to_asrc", "clkout_pdm",
+ "sai0_fs", "sai1_fs", "sai2_fs", "sai3_fs", "sai4_fs" };
+PNAME(cclk_src_sdmmc_parents_p) = { "xin24m_gate", "gpll", "clk_v0pll_gate", "clk_v1pll_gate" };
+PNAME(dclk_vop_parents_p) = { "xin24m_gate", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate", "dummy_vop_dclk",
+ "dummy_vop_dclk", "dummy_vop_dclk", "dummy_vop_dclk" };
+PNAME(dbclk_gpio0_parents_p) = { "xin24m", "clk_rc", "clk_32k_pmu" };
+PNAME(clk_pmu_hp_timer_parents_p) = { "xin24m", "gpll_div_100m", "clk_core_pvtpll" };
+PNAME(clk_ref_out_parents_p) = { "xin24m", "gpll", "v0pll", "v1pll" };
+PNAME(clk_32k_frac_parents_p) = { "xin24m", "v0pll", "v1pll", "clk_rc" };
+PNAME(clk_32k_parents_p) = { "xin32k", "clk_32k_rc", "clk_32k_frac" };
+PNAME(clk_ref_phy_pmu_mux_parents_p) = { "xin24m", "clk_ref_phy_pll" };
+PNAME(clk_vpll_ref_parents_p) = { "xin24m", "clk_pll_ref_io" };
+PNAME(mux_armclk_p) = { "armclk_pll", "clk_core_pvtpll" };
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_pll_clock rk3506_pll_clks[] __initdata = {
+ [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+ CLK_IS_CRITICAL, RK3506_PLL_CON(0),
+ RK3506_MODE_CON, 0, 2, 0, rk3506_pll_rates),
+ [v0pll] = PLL(pll_rk3328, PLL_V0PLL, "v0pll", mux_pll_p,
+ CLK_IS_CRITICAL, RK3506_PLL_CON(8),
+ RK3506_MODE_CON, 2, 0, 0, rk3506_pll_rates),
+ [v1pll] = PLL(pll_rk3328, PLL_V1PLL, "v1pll", mux_pll_p,
+ CLK_IS_CRITICAL, RK3506_PLL_CON(16),
+ RK3506_MODE_CON, 4, 1, 0, rk3506_pll_rates),
+};
+
+static struct rockchip_clk_branch rk3506_armclk __initdata =
+ MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ RK3506_CLKSEL_CON(15), 8, 1, MFLAGS);
+
+static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
+ /*
+ * CRU Clock-Architecture
+ */
+ /* top */
+ GATE(XIN24M_GATE, "xin24m_gate", "xin24m", CLK_IS_CRITICAL,
+ RK3506_CLKGATE_CON(0), 1, GFLAGS),
+ GATE(CLK_GPLL_GATE, "clk_gpll_gate", "gpll", CLK_IS_CRITICAL,
+ RK3506_CLKGATE_CON(0), 2, GFLAGS),
+ GATE(CLK_V0PLL_GATE, "clk_v0pll_gate", "v0pll", CLK_IS_CRITICAL,
+ RK3506_CLKGATE_CON(0), 3, GFLAGS),
+ GATE(CLK_V1PLL_GATE, "clk_v1pll_gate", "v1pll", 0,
+ RK3506_CLKGATE_CON(0), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV, "clk_gpll_div", "clk_gpll_gate", CLK_IS_CRITICAL,
+ RK3506_CLKSEL_CON(0), 6, 4, DFLAGS,
+ RK3506_CLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV_100M, "clk_gpll_div_100m", "clk_gpll_div", 0,
+ RK3506_CLKSEL_CON(0), 10, 4, DFLAGS,
+ RK3506_CLKGATE_CON(0), 6, GFLAGS),
+ COMPOSITE_NOMUX(CLK_V0PLL_DIV, "clk_v0pll_div", "clk_v0pll_gate", CLK_IS_CRITICAL,
+ RK3506_CLKSEL_CON(1), 0, 4, DFLAGS,
+ RK3506_CLKGATE_CON(0), 7, GFLAGS),
+ COMPOSITE_NOMUX(CLK_V1PLL_DIV, "clk_v1pll_div", "clk_v1pll_gate", 0,
+ RK3506_CLKSEL_CON(1), 4, 4, DFLAGS,
+ RK3506_CLKGATE_CON(0), 8, GFLAGS),
+ COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX0, "clk_int_voice_matrix0", "clk_v0pll_gate", 0,
+ RK3506_CLKSEL_CON(1), 8, 5, DFLAGS,
+ RK3506_CLKGATE_CON(0), 9, GFLAGS),
+ COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX1, "clk_int_voice_matrix1", "clk_v1pll_gate", 0,
+ RK3506_CLKSEL_CON(2), 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(0), 10, GFLAGS),
+ COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX2, "clk_int_voice_matrix2", "clk_v0pll_gate", 0,
+ RK3506_CLKSEL_CON(2), 5, 5, DFLAGS,
+ RK3506_CLKGATE_CON(0), 11, GFLAGS),
+ MUX(CLK_FRAC_UART_MATRIX0_MUX, "clk_frac_uart_matrix0_mux", clk_frac_uart_matrix0_mux_parents_p, 0,
+ RK3506_CLKSEL_CON(3), 9, 2, MFLAGS),
+ MUX(CLK_FRAC_UART_MATRIX1_MUX, "clk_frac_uart_matrix1_mux", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(3), 11, 2, MFLAGS),
+ MUX(CLK_FRAC_VOICE_MATRIX0_MUX, "clk_frac_voice_matrix0_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(3), 13, 2, MFLAGS),
+ MUX(CLK_FRAC_VOICE_MATRIX1_MUX, "clk_frac_voice_matrix1_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(4), 0, 2, MFLAGS),
+ MUX(CLK_FRAC_COMMON_MATRIX0_MUX, "clk_frac_common_matrix0_mux", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(4), 2, 2, MFLAGS),
+ MUX(CLK_FRAC_COMMON_MATRIX1_MUX, "clk_frac_common_matrix1_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(4), 4, 2, MFLAGS),
+ MUX(CLK_FRAC_COMMON_MATRIX2_MUX, "clk_frac_common_matrix2_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(4), 6, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_FRAC_UART_MATRIX0, "clk_frac_uart_matrix0", "clk_frac_uart_matrix0_mux", 0,
+ RK3506_CLKSEL_CON(5), 0,
+ RK3506_CLKGATE_CON(0), 13, GFLAGS),
+ COMPOSITE_FRAC(CLK_FRAC_UART_MATRIX1, "clk_frac_uart_matrix1", "clk_frac_uart_matrix1_mux", 0,
+ RK3506_CLKSEL_CON(6), 0,
+ RK3506_CLKGATE_CON(0), 14, GFLAGS),
+ COMPOSITE_FRAC(CLK_FRAC_VOICE_MATRIX0, "clk_frac_voice_matrix0", "clk_frac_voice_matrix0_mux", 0,
+ RK3506_CLKSEL_CON(7), 0,
+ RK3506_CLKGATE_CON(0), 15, GFLAGS),
+ COMPOSITE_FRAC(CLK_FRAC_VOICE_MATRIX1, "clk_frac_voice_matrix1", "clk_frac_voice_matrix1_mux", 0,
+ RK3506_CLKSEL_CON(9), 0,
+ RK3506_CLKGATE_CON(1), 0, GFLAGS),
+ COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX0, "clk_frac_common_matrix0", "clk_frac_common_matrix0_mux", 0,
+ RK3506_CLKSEL_CON(11), 0,
+ RK3506_CLKGATE_CON(1), 1, GFLAGS),
+ COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX1, "clk_frac_common_matrix1", "clk_frac_common_matrix1_mux", 0,
+ RK3506_CLKSEL_CON(12), 0,
+ RK3506_CLKGATE_CON(1), 2, GFLAGS),
+ COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX2, "clk_frac_common_matrix2", "clk_frac_common_matrix2_mux", 0,
+ RK3506_CLKSEL_CON(13), 0,
+ RK3506_CLKGATE_CON(1), 3, GFLAGS),
+ GATE(CLK_REF_USBPHY_TOP, "clk_ref_usbphy_top", "xin24m", 0,
+ RK3506_CLKGATE_CON(1), 4, GFLAGS),
+ GATE(CLK_REF_DPHY_TOP, "clk_ref_dphy_top", "xin24m", 0,
+ RK3506_CLKGATE_CON(1), 5, GFLAGS),
+
+ /* core */
+ COMPOSITE_NOGATE(0, "armclk_pll", gpll_v0pll_v1pll_parents_p, CLK_IS_CRITICAL,
+ RK3506_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS),
+ COMPOSITE_NOMUX(ACLK_CORE_ROOT, "aclk_core_root", "armclk", CLK_IGNORE_UNUSED,
+ RK3506_CLKSEL_CON(15), 9, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3506_CLKGATE_CON(2), 11, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_CORE_ROOT, "pclk_core_root", "armclk", CLK_IGNORE_UNUSED,
+ RK3506_CLKSEL_CON(16), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3506_CLKGATE_CON(2), 12, GFLAGS),
+ GATE(PCLK_DBG, "pclk_dbg", "pclk_core_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(3), 1, GFLAGS),
+ GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_core_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(3), 4, GFLAGS),
+ GATE(PCLK_CORE_CRU, "pclk_core_cru", "pclk_core_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(3), 5, GFLAGS),
+ GATE(CLK_CORE_EMA_DETECT, "clk_core_ema_detect", "xin24m_gate", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(3), 6, GFLAGS),
+ GATE(PCLK_GPIO1, "pclk_gpio1", "aclk_core_root", 0,
+ RK3506_CLKGATE_CON(3), 8, GFLAGS),
+ GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m_gate", 0,
+ RK3506_CLKGATE_CON(3), 9, GFLAGS),
+
+ /* core peri */
+ COMPOSITE(ACLK_CORE_PERI_ROOT, "aclk_core_peri_root", gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(18), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(4), 0, GFLAGS),
+ GATE(HCLK_CORE_PERI_ROOT, "hclk_core_peri_root", "aclk_core_peri_root", 0,
+ RK3506_CLKGATE_CON(4), 1, GFLAGS),
+ GATE(PCLK_CORE_PERI_ROOT, "pclk_core_peri_root", "aclk_core_peri_root", 0,
+ RK3506_CLKGATE_CON(4), 2, GFLAGS),
+ COMPOSITE(CLK_DSMC, "clk_dsmc", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(18), 12, 2, MFLAGS, 7, 5, DFLAGS,
+ RK3506_CLKGATE_CON(4), 4, GFLAGS),
+ GATE(ACLK_DSMC, "aclk_dsmc", "aclk_core_peri_root", 0,
+ RK3506_CLKGATE_CON(4), 5, GFLAGS),
+ GATE(PCLK_DSMC, "pclk_dsmc", "pclk_core_peri_root", 0,
+ RK3506_CLKGATE_CON(4), 6, GFLAGS),
+ COMPOSITE(CLK_FLEXBUS_TX, "clk_flexbus_tx", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(19), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(4), 7, GFLAGS),
+ COMPOSITE(CLK_FLEXBUS_RX, "clk_flexbus_rx", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(19), 12, 2, MFLAGS, 7, 5, DFLAGS,
+ RK3506_CLKGATE_CON(4), 8, GFLAGS),
+ GATE(ACLK_FLEXBUS, "aclk_flexbus", "aclk_core_peri_root", 0,
+ RK3506_CLKGATE_CON(4), 9, GFLAGS),
+ GATE(HCLK_FLEXBUS, "hclk_flexbus", "hclk_core_peri_root", 0,
+ RK3506_CLKGATE_CON(4), 10, GFLAGS),
+ GATE(ACLK_DSMC_SLV, "aclk_dsmc_slv", "aclk_core_peri_root", 0,
+ RK3506_CLKGATE_CON(4), 11, GFLAGS),
+ GATE(HCLK_DSMC_SLV, "hclk_dsmc_slv", "hclk_core_peri_root", 0,
+ RK3506_CLKGATE_CON(4), 12, GFLAGS),
+
+ /* bus */
+ COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
+ RK3506_CLKSEL_CON(21), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(5), 0, GFLAGS),
+ COMPOSITE(HCLK_BUS_ROOT, "hclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
+ RK3506_CLKSEL_CON(21), 12, 2, MFLAGS, 7, 5, DFLAGS,
+ RK3506_CLKGATE_CON(5), 1, GFLAGS),
+ COMPOSITE(PCLK_BUS_ROOT, "pclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
+ RK3506_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(5), 2, GFLAGS),
+ GATE(ACLK_SYSRAM, "aclk_sysram", "aclk_bus_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(5), 6, GFLAGS),
+ GATE(HCLK_SYSRAM, "hclk_sysram", "aclk_bus_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(5), 7, GFLAGS),
+ GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0,
+ RK3506_CLKGATE_CON(5), 8, GFLAGS),
+ GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0,
+ RK3506_CLKGATE_CON(5), 9, GFLAGS),
+ GATE(HCLK_M0, "hclk_m0", "aclk_bus_root", 0,
+ RK3506_CLKGATE_CON(5), 10, GFLAGS),
+ GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_bus_root", 0,
+ RK3506_CLKGATE_CON(5), 14, GFLAGS),
+ GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_bus_root", 0,
+ RK3506_CLKGATE_CON(5), 15, GFLAGS),
+ GATE(HCLK_RNG, "hclk_rng", "hclk_bus_root", 0,
+ RK3506_CLKGATE_CON(6), 0, GFLAGS),
+ GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(6), 1, GFLAGS),
+ GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0,
+ RK3506_CLKGATE_CON(6), 2, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER0_CH0, "clk_timer0_ch0", clk_timer0_parents_p, 0,
+ RK3506_CLKSEL_CON(22), 7, 3, MFLAGS,
+ RK3506_CLKGATE_CON(6), 3, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER0_CH1, "clk_timer0_ch1", clk_timer1_parents_p, 0,
+ RK3506_CLKSEL_CON(22), 10, 3, MFLAGS,
+ RK3506_CLKGATE_CON(6), 4, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER0_CH2, "clk_timer0_ch2", clk_timer2_parents_p, 0,
+ RK3506_CLKSEL_CON(22), 13, 3, MFLAGS,
+ RK3506_CLKGATE_CON(6), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER0_CH3, "clk_timer0_ch3", clk_timer3_parents_p, 0,
+ RK3506_CLKSEL_CON(23), 0, 3, MFLAGS,
+ RK3506_CLKGATE_CON(6), 6, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER0_CH4, "clk_timer0_ch4", clk_timer4_parents_p, 0,
+ RK3506_CLKSEL_CON(23), 3, 3, MFLAGS,
+ RK3506_CLKGATE_CON(6), 7, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER0_CH5, "clk_timer0_ch5", clk_timer5_parents_p, 0,
+ RK3506_CLKSEL_CON(23), 6, 3, MFLAGS,
+ RK3506_CLKGATE_CON(6), 8, GFLAGS),
+ GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0,
+ RK3506_CLKGATE_CON(6), 9, GFLAGS),
+ GATE(TCLK_WDT0, "tclk_wdt0", "xin24m_gate", 0,
+ RK3506_CLKGATE_CON(6), 10, GFLAGS),
+ GATE(PCLK_WDT1, "pclk_wdt1", "pclk_bus_root", 0,
+ RK3506_CLKGATE_CON(6), 11, GFLAGS),
+ GATE(TCLK_WDT1, "tclk_wdt1", "xin24m_gate", 0,
+ RK3506_CLKGATE_CON(6), 12, GFLAGS),
+ GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus_root", 0,
+ RK3506_CLKGATE_CON(6), 13, GFLAGS),
+ GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", 0,
+ RK3506_CLKGATE_CON(6), 14, GFLAGS),
+ GATE(PCLK_SPINLOCK, "pclk_spinlock", "pclk_bus_root", 0,
+ RK3506_CLKGATE_CON(6), 15, GFLAGS),
+ GATE(PCLK_DDRC, "pclk_ddrc", "pclk_bus_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(7), 0, GFLAGS),
+ GATE(HCLK_DDRPHY, "hclk_ddrphy", "hclk_bus_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(7), 1, GFLAGS),
+ GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_bus_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(7), 2, GFLAGS),
+ GATE(CLK_DDRMON_OSC, "clk_ddrmon_osc", "xin24m_gate", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(7), 3, GFLAGS),
+ GATE(PCLK_STDBY, "pclk_stdby", "pclk_bus_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(7), 4, GFLAGS),
+ GATE(HCLK_USBOTG0, "hclk_usbotg0", "hclk_bus_root", 0,
+ RK3506_CLKGATE_CON(7), 5, GFLAGS),
+ GATE(HCLK_USBOTG0_PMU, "hclk_usbotg0_pmu", "hclk_bus_root", 0,
+ RK3506_CLKGATE_CON(7), 6, GFLAGS),
+ GATE(CLK_USBOTG0_ADP, "clk_usbotg0_adp", "clk_32k", 0,
+ RK3506_CLKGATE_CON(7), 7, GFLAGS),
+ GATE(HCLK_USBOTG1, "hclk_usbotg1", "hclk_bus_root", 0,
+ RK3506_CLKGATE_CON(7), 8, GFLAGS),
+ GATE(HCLK_USBOTG1_PMU, "hclk_usbotg1_pmu", "hclk_bus_root", 0,
+ RK3506_CLKGATE_CON(7), 9, GFLAGS),
+ GATE(CLK_USBOTG1_ADP, "clk_usbotg1_adp", "clk_32k", 0,
+ RK3506_CLKGATE_CON(7), 10, GFLAGS),
+ GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_bus_root", 0,
+ RK3506_CLKGATE_CON(7), 11, GFLAGS),
+ GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(8), 0, GFLAGS),
+ GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(8), 1, GFLAGS),
+ COMPOSITE_NOMUX(STCLK_M0, "stclk_m0", "xin24m_gate", 0,
+ RK3506_CLKSEL_CON(23), 9, 6, DFLAGS,
+ RK3506_CLKGATE_CON(8), 2, GFLAGS),
+ COMPOSITE(CLK_DDRPHY, "clk_ddrphy", gpll_v0pll_v1pll_parents_p, CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKSEL_CON(4), 4, 2, MFLAGS, 0, 4, DFLAGS,
+ RK3506_PMU_CLKGATE_CON(1), 10, GFLAGS),
+ FACTOR(CLK_DDRC_SRC, "clk_ddrc_src", "clk_ddrphy", 0, 1, 4),
+ GATE(ACLK_DDRC_0, "aclk_ddrc_0", "clk_ddrc_src", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(10), 0, GFLAGS),
+ GATE(ACLK_DDRC_1, "aclk_ddrc_1", "clk_ddrc_src", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(10), 1, GFLAGS),
+ GATE(CLK_DDRC, "clk_ddrc", "clk_ddrc_src", CLK_IS_CRITICAL,
+ RK3506_CLKGATE_CON(10), 3, GFLAGS),
+ GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IGNORE_UNUSED,
+ RK3506_CLKGATE_CON(10), 4, GFLAGS),
+
+ /* ls peri */
+ COMPOSITE(HCLK_LSPERI_ROOT, "hclk_lsperi_root", gpll_v0pll_v1pll_div_parents_p, 0,
+ RK3506_CLKSEL_CON(29), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(11), 0, GFLAGS),
+ GATE(PCLK_LSPERI_ROOT, "pclk_lsperi_root", "hclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(11), 1, GFLAGS),
+ GATE(PCLK_UART0, "pclk_uart0", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(11), 4, GFLAGS),
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(11), 5, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(11), 6, GFLAGS),
+ GATE(PCLK_UART3, "pclk_uart3", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(11), 7, GFLAGS),
+ GATE(PCLK_UART4, "pclk_uart4", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(11), 8, GFLAGS),
+ COMPOSITE(SCLK_UART0, "sclk_uart0", sclk_uart_parents_p, 0,
+ RK3506_CLKSEL_CON(29), 12, 3, MFLAGS, 7, 5, DFLAGS,
+ RK3506_CLKGATE_CON(11), 9, GFLAGS),
+ COMPOSITE(SCLK_UART1, "sclk_uart1", sclk_uart_parents_p, 0,
+ RK3506_CLKSEL_CON(30), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(11), 10, GFLAGS),
+ COMPOSITE(SCLK_UART2, "sclk_uart2", sclk_uart_parents_p, 0,
+ RK3506_CLKSEL_CON(30), 13, 3, MFLAGS, 8, 5, DFLAGS,
+ RK3506_CLKGATE_CON(11), 11, GFLAGS),
+ COMPOSITE(SCLK_UART3, "sclk_uart3", sclk_uart_parents_p, 0,
+ RK3506_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(11), 12, GFLAGS),
+ COMPOSITE(SCLK_UART4, "sclk_uart4", sclk_uart_parents_p, 0,
+ RK3506_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS,
+ RK3506_CLKGATE_CON(11), 13, GFLAGS),
+ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(11), 14, GFLAGS),
+ COMPOSITE(CLK_I2C0, "clk_i2c0", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
+ RK3506_CLKSEL_CON(32), 4, 2, MFLAGS, 0, 4, DFLAGS,
+ RK3506_CLKGATE_CON(11), 15, GFLAGS),
+ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(12), 0, GFLAGS),
+ COMPOSITE(CLK_I2C1, "clk_i2c1", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
+ RK3506_CLKSEL_CON(32), 10, 2, MFLAGS, 6, 4, DFLAGS,
+ RK3506_CLKGATE_CON(12), 1, GFLAGS),
+ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(12), 2, GFLAGS),
+ COMPOSITE(CLK_I2C2, "clk_i2c2", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
+ RK3506_CLKSEL_CON(33), 4, 2, MFLAGS, 0, 4, DFLAGS,
+ RK3506_CLKGATE_CON(12), 3, GFLAGS),
+ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(12), 4, GFLAGS),
+ COMPOSITE(CLK_PWM1, "clk_pwm1", gpll_v0pll_v1pll_div_parents_p, 0,
+ RK3506_CLKSEL_CON(33), 10, 2, MFLAGS, 6, 4, DFLAGS,
+ RK3506_CLKGATE_CON(12), 5, GFLAGS),
+ GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
+ RK3506_CLKGATE_CON(12), 6, GFLAGS),
+ GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_rc", 0,
+ RK3506_CLKGATE_CON(12), 7, GFLAGS),
+ COMPOSITE_NODIV(CLK_FREQ_PWM1, "clk_freq_pwm1", clk_pwm_parents_p, 0,
+ RK3506_CLKSEL_CON(33), 12, 4, MFLAGS,
+ RK3506_CLKGATE_CON(12), 8, GFLAGS),
+ COMPOSITE_NODIV(CLK_COUNTER_PWM1, "clk_counter_pwm1", clk_pwm_parents_p, 0,
+ RK3506_CLKSEL_CON(34), 0, 4, MFLAGS,
+ RK3506_CLKGATE_CON(12), 9, GFLAGS),
+ GATE(PCLK_SPI0, "pclk_spi0", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(12), 10, GFLAGS),
+ COMPOSITE(CLK_SPI0, "clk_spi0", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
+ RK3506_CLKSEL_CON(34), 8, 2, MFLAGS, 4, 4, DFLAGS,
+ RK3506_CLKGATE_CON(12), 11, GFLAGS),
+ GATE(PCLK_SPI1, "pclk_spi1", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(12), 12, GFLAGS),
+ COMPOSITE(CLK_SPI1, "clk_spi1", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
+ RK3506_CLKSEL_CON(34), 14, 2, MFLAGS, 10, 4, DFLAGS,
+ RK3506_CLKGATE_CON(12), 13, GFLAGS),
+ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(12), 14, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", xin24m_400k_32k_parents_p, 0,
+ RK3506_CLKSEL_CON(35), 0, 2, MFLAGS,
+ RK3506_CLKGATE_CON(12), 15, GFLAGS),
+ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(13), 0, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", xin24m_400k_32k_parents_p, 0,
+ RK3506_CLKSEL_CON(35), 2, 2, MFLAGS,
+ RK3506_CLKGATE_CON(13), 1, GFLAGS),
+ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(13), 2, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", xin24m_400k_32k_parents_p, 0,
+ RK3506_CLKSEL_CON(35), 4, 2, MFLAGS,
+ RK3506_CLKGATE_CON(13), 3, GFLAGS),
+ GATE(HCLK_CAN0, "hclk_can0", "hclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(13), 4, GFLAGS),
+ COMPOSITE(CLK_CAN0, "clk_can0", clk_can_parents_p, 0,
+ RK3506_CLKSEL_CON(35), 11, 3, MFLAGS, 6, 5, DFLAGS,
+ RK3506_CLKGATE_CON(13), 5, GFLAGS),
+ GATE(HCLK_CAN1, "hclk_can1", "hclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(13), 6, GFLAGS),
+ COMPOSITE(CLK_CAN1, "clk_can1", clk_can_parents_p, 0,
+ RK3506_CLKSEL_CON(36), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(13), 7, GFLAGS),
+ GATE(HCLK_PDM, "hclk_pdm", "hclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(13), 8, GFLAGS),
+ COMPOSITE(MCLK_PDM, "mclk_pdm", clk_pdm_parents_p, 0,
+ RK3506_CLKSEL_CON(37), 5, 4, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(13), 9, GFLAGS),
+ COMPOSITE(CLKOUT_PDM, "clkout_pdm", clk_pdm_parents_p, 0,
+ RK3506_CLKSEL_CON(38), 10, 4, MFLAGS, 0, 10, DFLAGS,
+ RK3506_CLKGATE_CON(13), 10, GFLAGS),
+ COMPOSITE(MCLK_SPDIFTX, "mclk_spdiftx", mclk_sai_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(39), 5, 4, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(13), 11, GFLAGS),
+ GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(13), 12, GFLAGS),
+ GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(13), 13, GFLAGS),
+ COMPOSITE(MCLK_SPDIFRX, "mclk_spdifrx", gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(39), 14, 2, MFLAGS, 9, 5, DFLAGS,
+ RK3506_CLKGATE_CON(13), 14, GFLAGS),
+ COMPOSITE(MCLK_SAI0, "mclk_sai0", mclk_sai_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(40), 8, 4, MFLAGS, 0, 8, DFLAGS,
+ RK3506_CLKGATE_CON(13), 15, GFLAGS),
+ GATE(HCLK_SAI0, "hclk_sai0", "hclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(14), 0, GFLAGS),
+ GATE(MCLK_OUT_SAI0, "mclk_out_sai0", "mclk_sai0", 0,
+ RK3506_CLKGATE_CON(14), 1, GFLAGS),
+ COMPOSITE(MCLK_SAI1, "mclk_sai1", mclk_sai_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(41), 8, 4, MFLAGS, 0, 8, DFLAGS,
+ RK3506_CLKGATE_CON(14), 2, GFLAGS),
+ GATE(HCLK_SAI1, "hclk_sai1", "hclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(14), 3, GFLAGS),
+ GATE(MCLK_OUT_SAI1, "mclk_out_sai1", "mclk_sai1", 0,
+ RK3506_CLKGATE_CON(14), 4, GFLAGS),
+ GATE(HCLK_ASRC0, "hclk_asrc0", "hclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(14), 5, GFLAGS),
+ COMPOSITE(CLK_ASRC0, "clk_asrc0", gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(42), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(14), 6, GFLAGS),
+ GATE(HCLK_ASRC1, "hclk_asrc1", "hclk_lsperi_root", 0,
+ RK3506_CLKGATE_CON(14), 7, GFLAGS),
+ COMPOSITE(CLK_ASRC1, "clk_asrc1", gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(42), 12, 2, MFLAGS, 7, 5, DFLAGS,
+ RK3506_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(PCLK_CRU, "pclk_cru", "pclk_lsperi_root", CLK_IS_CRITICAL,
+ RK3506_CLKGATE_CON(14), 9, GFLAGS),
+ GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "pclk_lsperi_root", CLK_IS_CRITICAL,
+ RK3506_CLKGATE_CON(14), 10, GFLAGS),
+ COMPOSITE_NODIV(MCLK_ASRC0, "mclk_asrc0", mclk_sai_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(46), 0, 4, MFLAGS,
+ RK3506_CLKGATE_CON(16), 0, GFLAGS),
+ COMPOSITE_NODIV(MCLK_ASRC1, "mclk_asrc1", mclk_sai_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(46), 4, 4, MFLAGS,
+ RK3506_CLKGATE_CON(16), 1, GFLAGS),
+ COMPOSITE_NODIV(MCLK_ASRC2, "mclk_asrc2", mclk_sai_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(46), 8, 4, MFLAGS,
+ RK3506_CLKGATE_CON(16), 2, GFLAGS),
+ COMPOSITE_NODIV(MCLK_ASRC3, "mclk_asrc3", mclk_sai_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(46), 12, 4, MFLAGS,
+ RK3506_CLKGATE_CON(16), 3, GFLAGS),
+ COMPOSITE_NODIV(LRCK_ASRC0_SRC, "lrck_asrc0_src", lrck_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(47), 0, 4, MFLAGS,
+ RK3506_CLKGATE_CON(16), 4, GFLAGS),
+ COMPOSITE_NODIV(LRCK_ASRC0_DST, "lrck_asrc0_dst", lrck_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(47), 4, 4, MFLAGS,
+ RK3506_CLKGATE_CON(16), 5, GFLAGS),
+ COMPOSITE_NODIV(LRCK_ASRC1_SRC, "lrck_asrc1_src", lrck_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(47), 8, 4, MFLAGS,
+ RK3506_CLKGATE_CON(16), 6, GFLAGS),
+ COMPOSITE_NODIV(LRCK_ASRC1_DST, "lrck_asrc1_dst", lrck_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(47), 12, 4, MFLAGS,
+ RK3506_CLKGATE_CON(16), 7, GFLAGS),
+
+ /* hs peri */
+ COMPOSITE(ACLK_HSPERI_ROOT, "aclk_hsperi_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
+ RK3506_CLKSEL_CON(49), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(17), 0, GFLAGS),
+ GATE(HCLK_HSPERI_ROOT, "hclk_hsperi_root", "aclk_hsperi_root", CLK_IS_CRITICAL,
+ RK3506_CLKGATE_CON(17), 1, GFLAGS),
+ GATE(PCLK_HSPERI_ROOT, "pclk_hsperi_root", "hclk_hsperi_root", CLK_IS_CRITICAL,
+ RK3506_CLKGATE_CON(17), 2, GFLAGS),
+ COMPOSITE(CCLK_SRC_SDMMC, "cclk_src_sdmmc", cclk_src_sdmmc_parents_p, 0,
+ RK3506_CLKSEL_CON(49), 13, 2, MFLAGS, 7, 6, DFLAGS,
+ RK3506_CLKGATE_CON(17), 6, GFLAGS),
+ GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(17), 7, GFLAGS),
+ GATE(HCLK_FSPI, "hclk_fspi", "hclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(17), 8, GFLAGS),
+ COMPOSITE(SCLK_FSPI, "sclk_fspi", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(50), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(17), 9, GFLAGS),
+ GATE(PCLK_SPI2, "pclk_spi2", "pclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(17), 10, GFLAGS),
+ GATE(ACLK_MAC0, "aclk_mac0", "aclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(17), 11, GFLAGS),
+ GATE(ACLK_MAC1, "aclk_mac1", "aclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(17), 12, GFLAGS),
+ GATE(PCLK_MAC0, "pclk_mac0", "pclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(17), 13, GFLAGS),
+ GATE(PCLK_MAC1, "pclk_mac1", "pclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(17), 14, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MAC_ROOT, "clk_mac_root", "gpll", 0,
+ RK3506_CLKSEL_CON(50), 7, 5, DFLAGS,
+ RK3506_CLKGATE_CON(17), 15, GFLAGS),
+ GATE(CLK_MAC0, "clk_mac0", "clk_mac_root", 0,
+ RK3506_CLKGATE_CON(18), 0, GFLAGS),
+ GATE(CLK_MAC1, "clk_mac1", "clk_mac_root", 0,
+ RK3506_CLKGATE_CON(18), 1, GFLAGS),
+ COMPOSITE(MCLK_SAI2, "mclk_sai2", mclk_sai_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(51), 8, 4, MFLAGS, 0, 8, DFLAGS,
+ RK3506_CLKGATE_CON(18), 2, GFLAGS),
+ GATE(HCLK_SAI2, "hclk_sai2", "hclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(18), 3, GFLAGS),
+ GATE(MCLK_OUT_SAI2, "mclk_out_sai2", "mclk_sai2", 0,
+ RK3506_CLKGATE_CON(18), 4, GFLAGS),
+ COMPOSITE(MCLK_SAI3_SRC, "mclk_sai3_src", mclk_sai_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(52), 8, 4, MFLAGS, 0, 8, DFLAGS,
+ RK3506_CLKGATE_CON(18), 5, GFLAGS),
+ GATE(HCLK_SAI3, "hclk_sai3", "hclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(18), 6, GFLAGS),
+ GATE(MCLK_SAI3, "mclk_sai3", "mclk_sai3_src", 0,
+ RK3506_CLKGATE_CON(18), 7, GFLAGS),
+ GATE(MCLK_OUT_SAI3, "mclk_out_sai3", "mclk_sai3_src", 0,
+ RK3506_CLKGATE_CON(18), 8, GFLAGS),
+ COMPOSITE(MCLK_SAI4_SRC, "mclk_sai4_src", mclk_sai_asrc_parents_p, 0,
+ RK3506_CLKSEL_CON(53), 8, 4, MFLAGS, 0, 8, DFLAGS,
+ RK3506_CLKGATE_CON(18), 9, GFLAGS),
+ GATE(HCLK_SAI4, "hclk_sai4", "hclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(18), 10, GFLAGS),
+ GATE(MCLK_SAI4, "mclk_sai4", "mclk_sai4_src", 0,
+ RK3506_CLKGATE_CON(18), 11, GFLAGS),
+ GATE(HCLK_DSM, "hclk_dsm", "hclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(18), 12, GFLAGS),
+ GATE(MCLK_DSM, "mclk_dsm", "mclk_sai3_src", 0,
+ RK3506_CLKGATE_CON(18), 13, GFLAGS),
+ GATE(PCLK_AUDIO_ADC, "pclk_audio_adc", "pclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(18), 14, GFLAGS),
+ GATE(MCLK_AUDIO_ADC, "mclk_audio_adc", "mclk_sai4_src", 0,
+ RK3506_CLKGATE_CON(18), 15, GFLAGS),
+ FACTOR(MCLK_AUDIO_ADC_DIV4, "mclk_audio_adc_div4", "mclk_audio_adc", 0, 1, 4),
+ GATE(PCLK_SARADC, "pclk_saradc", "pclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(19), 0, GFLAGS),
+ COMPOSITE(CLK_SARADC, "clk_saradc", xin24m_400k_32k_parents_p, 0,
+ RK3506_CLKSEL_CON(54), 4, 2, MFLAGS, 0, 4, DFLAGS,
+ RK3506_CLKGATE_CON(19), 1, GFLAGS),
+ GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(19), 3, GFLAGS),
+ GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m_gate", 0,
+ RK3506_CLKGATE_CON(19), 4, GFLAGS),
+ FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns", 0, 1, 2),
+ GATE(PCLK_UART5, "pclk_uart5", "pclk_hsperi_root", 0,
+ RK3506_CLKGATE_CON(19), 6, GFLAGS),
+ COMPOSITE(SCLK_UART5, "sclk_uart5", sclk_uart_parents_p, 0,
+ RK3506_CLKSEL_CON(54), 11, 3, MFLAGS, 6, 5, DFLAGS,
+ RK3506_CLKGATE_CON(19), 7, GFLAGS),
+ GATE(PCLK_GPIO234_IOC, "pclk_gpio234_ioc", "pclk_hsperi_root", CLK_IS_CRITICAL,
+ RK3506_CLKGATE_CON(19), 8, GFLAGS),
+ COMPOSITE(CLK_MAC_PTP_ROOT, "clk_mac_ptp_root", clk_mac_ptp_root_parents_p, 0,
+ RK3506_CLKSEL_CON(55), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(19), 9, GFLAGS),
+ GATE(CLK_MAC0_PTP, "clk_mac0_ptp", "clk_mac_ptp_root", 0,
+ RK3506_CLKGATE_CON(19), 10, GFLAGS),
+ GATE(CLK_MAC1_PTP, "clk_mac1_ptp", "clk_mac_ptp_root", 0,
+ RK3506_CLKGATE_CON(19), 11, GFLAGS),
+ COMPOSITE(ACLK_VIO_ROOT, "aclk_vio_root", gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(58), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(21), 0, GFLAGS),
+ COMPOSITE(HCLK_VIO_ROOT, "hclk_vio_root", gpll_v0pll_v1pll_div_parents_p, 0,
+ RK3506_CLKSEL_CON(58), 12, 2, MFLAGS, 7, 5, DFLAGS,
+ RK3506_CLKGATE_CON(21), 1, GFLAGS),
+ GATE(PCLK_VIO_ROOT, "pclk_vio_root", "hclk_vio_root", 0,
+ RK3506_CLKGATE_CON(21), 2, GFLAGS),
+ GATE(HCLK_RGA, "hclk_rga", "hclk_vio_root", 0,
+ RK3506_CLKGATE_CON(21), 6, GFLAGS),
+ GATE(ACLK_RGA, "aclk_rga", "aclk_vio_root", 0,
+ RK3506_CLKGATE_CON(21), 7, GFLAGS),
+ COMPOSITE(CLK_CORE_RGA, "clk_core_rga", gpll_v0pll_v1pll_g_parents_p, 0,
+ RK3506_CLKSEL_CON(59), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3506_CLKGATE_CON(21), 8, GFLAGS),
+ GATE(ACLK_VOP, "aclk_vop", "aclk_vio_root", 0,
+ RK3506_CLKGATE_CON(21), 9, GFLAGS),
+ GATE(HCLK_VOP, "hclk_vop", "hclk_vio_root", 0,
+ RK3506_CLKGATE_CON(21), 10, GFLAGS),
+ COMPOSITE(DCLK_VOP, "dclk_vop", dclk_vop_parents_p, 0,
+ RK3506_CLKSEL_CON(60), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3506_CLKGATE_CON(21), 11, GFLAGS),
+ GATE(PCLK_DPHY, "pclk_dphy", "pclk_vio_root", 0,
+ RK3506_CLKGATE_CON(21), 12, GFLAGS),
+ GATE(PCLK_DSI_HOST, "pclk_dsi_host", "pclk_vio_root", 0,
+ RK3506_CLKGATE_CON(21), 13, GFLAGS),
+ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vio_root", 0,
+ RK3506_CLKGATE_CON(21), 14, GFLAGS),
+ COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m_gate", 0,
+ RK3506_CLKSEL_CON(61), 0, 8, DFLAGS,
+ RK3506_CLKGATE_CON(21), 15, GFLAGS),
+ COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m_gate", 0,
+ RK3506_CLKSEL_CON(61), 8, 3, DFLAGS,
+ RK3506_CLKGATE_CON(22), 0, GFLAGS),
+ GATE(PCLK_GPIO1_IOC, "pclk_gpio1_ioc", "pclk_vio_root", CLK_IS_CRITICAL,
+ RK3506_CLKGATE_CON(22), 1, GFLAGS),
+
+ /* pmu */
+ GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKGATE_CON(0), 1, GFLAGS),
+ GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKGATE_CON(0), 2, GFLAGS),
+ GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKGATE_CON(0), 4, GFLAGS),
+ GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKGATE_CON(0), 5, GFLAGS),
+ GATE(PCLK_GPIO0_IOC, "pclk_gpio0_ioc", "pclk_pmu_root", CLK_IS_CRITICAL,
+ RK3506_PMU_CLKGATE_CON(0), 7, GFLAGS),
+ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0,
+ RK3506_PMU_CLKGATE_CON(0), 8, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", dbclk_gpio0_parents_p, 0,
+ RK3506_PMU_CLKSEL_CON(0), 0, 2, MFLAGS,
+ RK3506_PMU_CLKGATE_CON(0), 9, GFLAGS),
+ GATE(PCLK_GPIO1_SHADOW, "pclk_gpio1_shadow", "pclk_pmu_root", 0,
+ RK3506_PMU_CLKGATE_CON(0), 10, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO1_SHADOW, "dbclk_gpio1_shadow", dbclk_gpio0_parents_p, 0,
+ RK3506_PMU_CLKSEL_CON(0), 2, 2, MFLAGS,
+ RK3506_PMU_CLKGATE_CON(0), 11, GFLAGS),
+ GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKGATE_CON(0), 12, GFLAGS),
+ MUX(CLK_PMU_HP_TIMER, "clk_pmu_hp_timer", clk_pmu_hp_timer_parents_p, CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKSEL_CON(0), 4, 2, MFLAGS),
+ GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pmu_root", 0,
+ RK3506_PMU_CLKGATE_CON(0), 15, GFLAGS),
+ COMPOSITE_NOMUX(CLK_PWM0, "clk_pwm0", "clk_gpll_div_100m", 0,
+ RK3506_PMU_CLKSEL_CON(0), 6, 4, DFLAGS,
+ RK3506_PMU_CLKGATE_CON(1), 0, GFLAGS),
+ GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0,
+ RK3506_PMU_CLKGATE_CON(1), 1, GFLAGS),
+ GATE(CLK_RC_PWM0, "clk_rc_pwm0", "clk_rc", 0,
+ RK3506_PMU_CLKGATE_CON(1), 2, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MAC_OUT, "clk_mac_out", "gpll", 0,
+ RK3506_PMU_CLKSEL_CON(0), 10, 6, DFLAGS,
+ RK3506_PMU_CLKGATE_CON(1), 3, GFLAGS),
+ COMPOSITE(CLK_REF_OUT0, "clk_ref_out0", clk_ref_out_parents_p, 0,
+ RK3506_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3506_PMU_CLKGATE_CON(1), 4, GFLAGS),
+ COMPOSITE(CLK_REF_OUT1, "clk_ref_out1", clk_ref_out_parents_p, 0,
+ RK3506_PMU_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3506_PMU_CLKGATE_CON(1), 5, GFLAGS),
+ MUX(CLK_32K_FRAC_MUX, "clk_32k_frac_mux", clk_32k_frac_parents_p, 0,
+ RK3506_PMU_CLKSEL_CON(3), 0, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_32K_FRAC, "clk_32k_frac", "clk_32k_frac_mux", 0,
+ RK3506_PMU_CLKSEL_CON(2), 0,
+ RK3506_PMU_CLKGATE_CON(1), 6, GFLAGS),
+ COMPOSITE_NOMUX(CLK_32K_RC, "clk_32k_rc", "clk_rc", CLK_IS_CRITICAL,
+ RK3506_PMU_CLKSEL_CON(3), 2, 5, DFLAGS,
+ RK3506_PMU_CLKGATE_CON(1), 7, GFLAGS),
+ COMPOSITE_NODIV(CLK_32K, "clk_32k", clk_32k_parents_p, CLK_IS_CRITICAL,
+ RK3506_PMU_CLKSEL_CON(3), 7, 2, MFLAGS,
+ RK3506_PMU_CLKGATE_CON(1), 8, GFLAGS),
+ COMPOSITE_NODIV(CLK_32K_PMU, "clk_32k_pmu", clk_32k_parents_p, CLK_IS_CRITICAL,
+ RK3506_PMU_CLKSEL_CON(3), 9, 2, MFLAGS,
+ RK3506_PMU_CLKGATE_CON(1), 9, GFLAGS),
+ GATE(CLK_PMU_32K, "clk_pmu_32k", "clk_32k_pmu", CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKGATE_CON(0), 3, GFLAGS),
+ GATE(CLK_PMU_HP_TIMER_32K, "clk_pmu_hp_timer_32k", "clk_32k_pmu", CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKGATE_CON(0), 14, GFLAGS),
+ GATE(PCLK_TOUCH_KEY, "pclk_touch_key", "pclk_pmu_root", CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKGATE_CON(1), 12, GFLAGS),
+ GATE(CLK_TOUCH_KEY, "clk_touch_key", "xin24m", CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKGATE_CON(1), 13, GFLAGS),
+ COMPOSITE(CLK_REF_PHY_PLL, "clk_ref_phy_pll", gpll_v0pll_v1pll_parents_p, 0,
+ RK3506_PMU_CLKSEL_CON(4), 13, 2, MFLAGS, 6, 7, DFLAGS,
+ RK3506_PMU_CLKGATE_CON(1), 14, GFLAGS),
+ MUX(CLK_REF_PHY_PMU_MUX, "clk_ref_phy_pmu_mux", clk_ref_phy_pmu_mux_parents_p, 0,
+ RK3506_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
+ GATE(CLK_WIFI_OUT, "clk_wifi_out", "xin24m", 0,
+ RK3506_PMU_CLKGATE_CON(2), 0, GFLAGS),
+ MUX(CLK_V0PLL_REF, "clk_v0pll_ref", clk_vpll_ref_parents_p, CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKSEL_CON(6), 0, 1, MFLAGS),
+ MUX(CLK_V1PLL_REF, "clk_v1pll_ref", clk_vpll_ref_parents_p, CLK_IGNORE_UNUSED,
+ RK3506_PMU_CLKSEL_CON(6), 1, 1, MFLAGS),
+
+ /* secure ns */
+ GATE(CLK_CORE_CRYPTO_NS, "clk_core_crypto_ns", "clk_core_crypto", 0,
+ RK3506_CLKGATE_CON(5), 12, GFLAGS),
+ GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_pka_crypto", 0,
+ RK3506_CLKGATE_CON(5), 13, GFLAGS),
+
+ /* io */
+ GATE(CLK_SPI2, "clk_spi2", "clk_spi2_io", 0,
+ RK3506_CLKGATE_CON(20), 0, GFLAGS),
+};
+
+static void __init rk3506_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ unsigned long clk_nr_clks;
+ void __iomem *reg_base;
+
+ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3506_clk_branches,
+ ARRAY_SIZE(rk3506_clk_branches)) + 1;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rk3506_pll_clks,
+ ARRAY_SIZE(rk3506_pll_clks),
+ 0);
+
+ rockchip_clk_register_armclk_multi_pll(ctx, &rk3506_armclk,
+ rk3506_cpuclk_rates,
+ ARRAY_SIZE(rk3506_cpuclk_rates));
+
+ rockchip_clk_register_branches(ctx, rk3506_clk_branches,
+ ARRAY_SIZE(rk3506_clk_branches));
+
+ rk3506_rst_init(np, reg_base);
+
+ rockchip_register_restart_notifier(ctx, RK3506_GLB_SRST_FST, NULL);
+
+ rockchip_clk_of_add_provider(np, ctx);
+
+ /* pvtpll src init */
+ writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RK3506_CLKSEL_CON(15));
+}
+
+CLK_OF_DECLARE(rk3506_cru, "rockchip,rk3506-cru", rk3506_clk_init);
+
+struct clk_rk3506_inits {
+ void (*inits)(struct device_node *np);
+};
+
+static const struct clk_rk3506_inits clk_rk3506_cru_init = {
+ .inits = rk3506_clk_init,
+};
+
+static const struct of_device_id clk_rk3506_match_table[] = {
+ {
+ .compatible = "rockchip,rk3506-cru",
+ .data = &clk_rk3506_cru_init,
+ },
+ { }
+};
+
+static int clk_rk3506_probe(struct platform_device *pdev)
+{
+ const struct clk_rk3506_inits *init_data;
+ struct device *dev = &pdev->dev;
+
+ init_data = device_get_match_data(dev);
+ if (!init_data)
+ return -EINVAL;
+
+ if (init_data->inits)
+ init_data->inits(dev->of_node);
+
+ return 0;
+}
+
+static struct platform_driver clk_rk3506_driver = {
+ .probe = clk_rk3506_probe,
+ .driver = {
+ .name = "clk-rk3506",
+ .of_match_table = clk_rk3506_match_table,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(clk_rk3506_driver, clk_rk3506_probe);
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 97d279399ae8..74eabf9b2ae2 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1652,6 +1652,7 @@ CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init);
static void __init rk3568_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
+ unsigned long clk_nr_clks;
void __iomem *reg_base;
reg_base = of_iomap(np, 0);
@@ -1660,7 +1661,9 @@ static void __init rk3568_clk_init(struct device_node *np)
return;
}
- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3568_clk_branches,
+ ARRAY_SIZE(rk3568_clk_branches)) + 1;
+ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(reg_base);
diff --git a/drivers/clk/rockchip/clk-rv1126b.c b/drivers/clk/rockchip/clk-rv1126b.c
new file mode 100644
index 000000000000..3e27bfc14854
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rv1126b.c
@@ -0,0 +1,1117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/syscore_ops.h>
+#include <dt-bindings/clock/rockchip,rv1126b-cru.h>
+#include "clk.h"
+
+#define RV1126B_FRAC_MAX_PRATE 1200000000
+
+#define PVTPLL_SRC_SEL_PVTPLL (BIT(0) | BIT(16))
+
+enum rv1126b_plls {
+ gpll, cpll, aupll, dpll
+};
+
+static struct rockchip_pll_rate_table rv1126b_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137),
+ RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355),
+ RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127),
+ RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185),
+ { /* sentinel */ },
+};
+
+#define RV1126B_DIV_ACLK_CORE_MASK 0x1f
+#define RV1126B_DIV_ACLK_CORE_SHIFT 0
+#define RV1126B_DIV_PCLK_CORE_MASK 0x1f
+#define RV1126B_DIV_PCLK_CORE_SHIFT 8
+#define RV1126B_CORE_SEL_MASK 0x1
+#define RV1126B_CORE_SEL_SHIFT 1
+
+#define RV1126B_CLKSEL0(_aclk_core) \
+{ \
+ .reg = RV1126B_CORECLKSEL_CON(2), \
+ .val = HIWORD_UPDATE(_aclk_core - 1, RV1126B_DIV_ACLK_CORE_MASK, \
+ RV1126B_DIV_ACLK_CORE_SHIFT), \
+}
+
+#define RV1126B_CLKSEL1(_pclk_dbg) \
+{ \
+ .reg = RV1126B_CORECLKSEL_CON(2), \
+ .val = HIWORD_UPDATE(_pclk_dbg - 1, RV1126B_DIV_PCLK_CORE_MASK, \
+ RV1126B_DIV_PCLK_CORE_SHIFT), \
+}
+
+#define RV1126B_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
+{ \
+ .prate = _prate, \
+ .divs = { \
+ RV1126B_CLKSEL0(_aclk_core), \
+ RV1126B_CLKSEL1(_pclk_dbg), \
+ }, \
+}
+
+static struct rockchip_cpuclk_rate_table rv1126b_cpuclk_rates[] __initdata = {
+ RV1126B_CPUCLK_RATE(1608000000, 4, 10),
+ RV1126B_CPUCLK_RATE(1512000000, 4, 10),
+ RV1126B_CPUCLK_RATE(1416000000, 4, 10),
+ RV1126B_CPUCLK_RATE(1296000000, 3, 10),
+ RV1126B_CPUCLK_RATE(1200000000, 3, 10),
+ RV1126B_CPUCLK_RATE(1188000000, 3, 8),
+ RV1126B_CPUCLK_RATE(1104000000, 2, 8),
+ RV1126B_CPUCLK_RATE(1008000000, 2, 8),
+ RV1126B_CPUCLK_RATE(816000000, 2, 6),
+ RV1126B_CPUCLK_RATE(600000000, 2, 4),
+ RV1126B_CPUCLK_RATE(594000000, 2, 4),
+ RV1126B_CPUCLK_RATE(408000000, 1, 3),
+ RV1126B_CPUCLK_RATE(396000000, 1, 3),
+};
+
+PNAME(mux_pll_p) = { "xin24m" };
+PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
+PNAME(mux_gpll_aupll_p) = { "gpll", "aupll" };
+PNAME(mux_gpll_aupll_cpll_p) = { "gpll", "aupll", "cpll" };
+PNAME(mux_gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };
+PNAME(mux_cpll_24m_p) = { "cpll", "xin24m" };
+PNAME(mux_24m_gpll_aupll_cpll_p) = { "xin24m", "gpll", "aupll", "cpll" };
+PNAME(mux_24m_gpll_cpll_p) = { "xin24m", "gpll", "cpll" };
+PNAME(mux_24m_gpll_aupll_p) = { "xin24m", "gpll", "aupll" };
+PNAME(mux_sclk_uart_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
+ "clk_cm_frac2", "clk_uart_frac0", "clk_uart_frac1" };
+PNAME(mclk_sai0_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
+ "clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1",
+ "clk_audio_int0", "clk_audio_int1",
+ "mclk_sai0_from_io" };
+PNAME(mclk_sai1_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
+ "clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1",
+ "clk_audio_int0", "clk_audio_int1",
+ "mclk_sai1_from_io" };
+PNAME(mclk_sai2_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
+ "clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1",
+ "clk_audio_int0", "clk_audio_int1",
+ "mclk_sai2_from_io" };
+PNAME(mux_sai_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
+ "clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1",
+ "clk_audio_int0", "clk_audio_int1", "mclk_sai0_from_io",
+ "mclk_sai1_from_io", "mclk_sai2_from_io"};
+PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" };
+PNAME(mux_200m_24m_p) = { "clk_gpll_div6", "xin24m" };
+PNAME(mux_500m_400m_200m_p) = { "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div6" };
+PNAME(mux_300m_200m_p) = { "clk_gpll_div4", "clk_gpll_div6" };
+PNAME(mux_500m_400m_300m_p) = { "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div4" };
+PNAME(mux_333m_200m_p) = { "clk_cpll_div3", "clk_gpll_div6" };
+PNAME(mux_600m_400m_200m_p) = { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div6" };
+PNAME(mux_400m_300m_200m_p) = { "clk_gpll_div3", "clk_gpll_div4", "clk_gpll_div6" };
+PNAME(mux_200m_100m_p) = { "clk_gpll_div6", "clk_cpll_div10" };
+PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20",
+ "xin24m" };
+PNAME(mux_600m_24m_p) = { "clk_gpll_div2", "xin24m" };
+PNAME(mux_armclk_p) = { "clk_core_pll", "clk_core_pvtpll" };
+PNAME(aclk_npu_root_p) = { "clk_npu_pll", "clk_npu_pvtpll" };
+PNAME(clk_saradc0_p) = { "clk_saradc0_src", "clk_saradc0_rcosc_io" };
+PNAME(clk_core_vepu_p) = { "clk_vepu_pll", "clk_vepu_pvtpll" };
+PNAME(clk_core_fec_p) = { "clk_core_fec_src", "clk_vcp_pvtpll" };
+PNAME(clk_core_aisp_p) = { "clk_aisp_pll", "clk_vcp_pvtpll" };
+PNAME(clk_core_isp_root_p) = { "clk_isp_pll", "clk_isp_pvtpll" };
+PNAME(clk_gmac_ptp_ref_p) = { "clk_gmac_ptp_ref_src", "clk_gmac_ptp_from_io" };
+PNAME(clk_saradc1_p) = { "clk_saradc1_src", "clk_saradc1_rcosc_io" };
+PNAME(clk_saradc2_p) = { "clk_saradc2_src", "clk_saradc2_rcosc_io" };
+PNAME(clk_rcosc_src_p) = { "xin24m", "clk_rcosc", "clk_rcosc_div2",
+ "clk_rcosc_div3", "clk_rcosc_div4" };
+PNAME(busclk_pmu_mux_p) = { "clk_cpll_div10", "clk_rcosc_src" };
+PNAME(clk_xin_rc_div_p) = { "xin24m", "clk_rcosc_src" };
+PNAME(clk_32k_p) = { "clk_xin_rc_div", "clk_32k_rtc", "clk_32k_io" };
+PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
+PNAME(mux_24m_rcosc_buspmu_p) = { "xin24m", "clk_rcosc_src", "busclk_pmu_src" };
+PNAME(mux_24m_rcosc_buspmu_32k_p) = { "xin24m", "clk_rcosc_src", "busclk_pmu_src",
+ "clk_32k" };
+PNAME(sclk_uart0_p) = { "sclk_uart0_src", "xin24m", "clk_rcosc_src" };
+PNAME(clk_osc_rcosc_ctrl_p) = { "clk_rcosc_src", "clk_testout_out" };
+PNAME(lrck_src_asrc_p) = { "mclk_asrc0", "mclk_asrc1", "mclk_asrc2", "mclk_asrc3",
+ "fs_inter_from_sai0", "fs_inter_from_sai1",
+ "fs_inter_from_sai2", "clkout_pdm"};
+PNAME(clk_ref_pipephy_p) = { "clk_ref_pipephy_cpll_src", "xin24m" };
+PNAME(clk_timer0_parents_p) = { "clk_timer_root", "mclk_sai0_from_io",
+ "sclk_sai0_from_io" };
+PNAME(clk_timer1_parents_p) = { "clk_timer_root", "mclk_sai1_from_io",
+ "sclk_sai1_from_io" };
+PNAME(clk_timer2_parents_p) = { "clk_timer_root", "mclk_sai2_from_io",
+ "sclk_sai2_from_io" };
+PNAME(clk_timer3_parents_p) = { "clk_timer_root", "mclk_asrc0", "mclk_asrc1" };
+PNAME(clk_timer4_parents_p) = { "clk_timer_root", "mclk_asrc2", "mclk_asrc3" };
+PNAME(clk_macphy_p) = { "xin24m", "clk_cpll_div20" };
+PNAME(clk_cpll_div10_p) = { "gpll", "clk_aisp_pll_src" };
+
+static struct rockchip_pll_clock rv1126b_pll_clks[] __initdata = {
+ [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+ CLK_IS_CRITICAL, RV1126B_PLL_CON(8),
+ RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates),
+ [aupll] = PLL(pll_rk3328, PLL_AUPLL, "aupll", mux_pll_p,
+ CLK_IS_CRITICAL, RV1126B_PLL_CON(0),
+ RV1126B_MODE_CON, 0, 10, 0, rv1126b_pll_rates),
+ [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
+ CLK_IS_CRITICAL, RV1126B_PERIPLL_CON(0),
+ RV1126B_MODE_CON, 4, 10, 0, rv1126b_pll_rates),
+ [dpll] = PLL(pll_rk3328, 0, "dpll", mux_pll_p,
+ CLK_IS_CRITICAL, RV1126B_SUBDDRPLL_CON(0),
+ RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rv1126b_rcdiv_pmu_fracmux __initdata =
+ MUX(CLK_32K, "clk_32k", clk_32k_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ RV1126B_PMUCLKSEL_CON(2), 1, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
+
+ FACTOR(0, "clk_rcosc_div2", "clk_rcosc", 0, 1, 2),
+ FACTOR(0, "clk_rcosc_div3", "clk_rcosc", 0, 1, 3),
+ FACTOR(0, "clk_rcosc_div4", "clk_rcosc", 0, 1, 4),
+
+ /* Clock Definition */
+ COMPOSITE_NODIV(CLK_AISP_PLL_SRC, "clk_aisp_pll_src", mux_gpll_aupll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(62), 4, 2, MFLAGS,
+ RV1126B_CLKGATE_CON(5), 4, GFLAGS),
+ DIV(CLK_AISP_PLL, "clk_aisp_pll", "clk_aisp_pll_src", 0,
+ RV1126B_CLKSEL_CON(62), 0, 3, DFLAGS),
+
+ COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", clk_cpll_div10_p, 0,
+ RV1126B_CLKSEL_CON(1), 15, 1, MFLAGS, 5, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(0), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_CPLL_DIV20, "clk_cpll_div20", "cpll", 0,
+ RV1126B_CLKSEL_CON(1), 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(0), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_CPLL_DIV8, "clk_cpll_div8", "cpll", 0,
+ RV1126B_CLKSEL_CON(1), 10, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(0), 2, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV8, "clk_gpll_div8", "gpll", 0,
+ RV1126B_CLKSEL_CON(2), 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(0), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV6, "clk_gpll_div6", "gpll", 0,
+ RV1126B_CLKSEL_CON(2), 5, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(0), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV4, "clk_gpll_div4", "gpll", 0,
+ RV1126B_CLKSEL_CON(2), 10, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE_NOMUX(CLK_CPLL_DIV3, "clk_cpll_div3", "cpll", 0,
+ RV1126B_CLKSEL_CON(3), 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(0), 6, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV3, "clk_gpll_div3", "gpll", 0,
+ RV1126B_CLKSEL_CON(3), 5, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(0), 7, GFLAGS),
+ COMPOSITE_NOMUX(CLK_CPLL_DIV2, "clk_cpll_div2", "cpll", 0,
+ RV1126B_CLKSEL_CON(3), 10, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(0), 8, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPLL_DIV2, "clk_gpll_div2", "gpll", 0,
+ RV1126B_CLKSEL_CON(4), 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(0), 9, GFLAGS),
+ MUX(CLK_CM_FRAC0_SRC, "clk_cm_frac0_src", mux_24m_gpll_aupll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(10), 0, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_CM_FRAC0, "clk_cm_frac0", "clk_cm_frac0_src", 0,
+ RV1126B_CLKSEL_CON(25), 0,
+ RV1126B_CLKGATE_CON(1), 0, GFLAGS),
+ MUX(CLK_CM_FRAC1_SRC, "clk_cm_frac1_src", mux_24m_gpll_aupll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(10), 2, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_CM_FRAC1, "clk_cm_frac1", "clk_cm_frac1_src", 0,
+ RV1126B_CLKSEL_CON(26), 0,
+ RV1126B_CLKGATE_CON(1), 1, GFLAGS),
+ MUX(CLK_CM_FRAC2_SRC, "clk_cm_frac2_src", mux_24m_gpll_aupll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(10), 4, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_CM_FRAC2, "clk_cm_frac2", "clk_cm_frac2_src", 0,
+ RV1126B_CLKSEL_CON(27), 0,
+ RV1126B_CLKGATE_CON(1), 2, GFLAGS),
+ MUX(CLK_UART_FRAC0_SRC, "clk_uart_frac0_src", mux_24m_gpll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(10), 6, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_UART_FRAC0, "clk_uart_frac0", "clk_uart_frac0_src", 0,
+ RV1126B_CLKSEL_CON(28), 0,
+ RV1126B_CLKGATE_CON(1), 3, GFLAGS),
+ MUX(CLK_UART_FRAC1_SRC, "clk_uart_frac1_src", mux_24m_gpll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(10), 8, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_UART_FRAC1, "clk_uart_frac1", "clk_uart_frac1_src", 0,
+ RV1126B_CLKSEL_CON(29), 0,
+ RV1126B_CLKGATE_CON(1), 4, GFLAGS),
+ MUX(CLK_AUDIO_FRAC0_SRC, "clk_audio_frac0_src", mux_24m_gpll_aupll_p, 0,
+ RV1126B_CLKSEL_CON(10), 10, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_AUDIO_FRAC0, "clk_audio_frac0", "clk_audio_frac0_src", 0,
+ RV1126B_CLKSEL_CON(30), 0,
+ RV1126B_CLKGATE_CON(1), 5, GFLAGS),
+ MUX(CLK_AUDIO_FRAC1_SRC, "clk_audio_frac1_src", mux_24m_gpll_aupll_p, 0,
+ RV1126B_CLKSEL_CON(10), 12, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_AUDIO_FRAC1, "clk_audio_frac1", "clk_audio_frac1_src", 0,
+ RV1126B_CLKSEL_CON(31), 0,
+ RV1126B_CLKGATE_CON(1), 6, GFLAGS),
+ COMPOSITE(CLK_AUDIO_INT0, "clk_audio_int0", mux_24m_gpll_aupll_p, 0,
+ RV1126B_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(1), 7, GFLAGS),
+ COMPOSITE(CLK_AUDIO_INT1, "clk_audio_int1", mux_24m_gpll_aupll_p, 0,
+ RV1126B_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(1), 8, GFLAGS),
+ COMPOSITE(SCLK_UART0_SRC, "sclk_uart0_src", mux_sclk_uart_src_p, 0,
+ RV1126B_CLKSEL_CON(12), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(1), 9, GFLAGS),
+ COMPOSITE(SCLK_UART1, "sclk_uart1", mux_sclk_uart_src_p, 0,
+ RV1126B_CLKSEL_CON(12), 13, 3, MFLAGS, 8, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(1), 10, GFLAGS),
+ COMPOSITE(SCLK_UART2, "sclk_uart2", mux_sclk_uart_src_p, 0,
+ RV1126B_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(1), 11, GFLAGS),
+ COMPOSITE(SCLK_UART3, "sclk_uart3", mux_sclk_uart_src_p, 0,
+ RV1126B_CLKSEL_CON(13), 13, 3, MFLAGS, 8, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(1), 12, GFLAGS),
+ COMPOSITE(SCLK_UART4, "sclk_uart4", mux_sclk_uart_src_p, 0,
+ RV1126B_CLKSEL_CON(14), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(1), 13, GFLAGS),
+ COMPOSITE(SCLK_UART5, "sclk_uart5", mux_sclk_uart_src_p, 0,
+ RV1126B_CLKSEL_CON(14), 13, 3, MFLAGS, 8, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(1), 14, GFLAGS),
+ COMPOSITE(SCLK_UART6, "sclk_uart6", mux_sclk_uart_src_p, 0,
+ RV1126B_CLKSEL_CON(15), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(2), 0, GFLAGS),
+ COMPOSITE(SCLK_UART7, "sclk_uart7", mux_sclk_uart_src_p, 0,
+ RV1126B_CLKSEL_CON(15), 13, 3, MFLAGS, 8, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(2), 1, GFLAGS),
+ COMPOSITE(MCLK_SAI0, "mclk_sai0", mclk_sai0_src_p, 0,
+ RV1126B_CLKSEL_CON(16), 8, 4, MFLAGS, 0, 8, DFLAGS,
+ RV1126B_CLKGATE_CON(2), 2, GFLAGS),
+ COMPOSITE(MCLK_SAI1, "mclk_sai1", mclk_sai1_src_p, 0,
+ RV1126B_CLKSEL_CON(17), 8, 4, MFLAGS, 0, 8, DFLAGS,
+ RV1126B_CLKGATE_CON(2), 3, GFLAGS),
+ COMPOSITE(MCLK_SAI2, "mclk_sai2", mclk_sai2_src_p, 0,
+ RV1126B_CLKSEL_CON(18), 8, 4, MFLAGS, 0, 8, DFLAGS,
+ RV1126B_CLKGATE_CON(2), 4, GFLAGS),
+ COMPOSITE(MCLK_PDM, "mclk_pdm", mux_sai_src_p, 0,
+ RV1126B_CLKSEL_CON(19), 6, 4, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(2), 5, GFLAGS),
+ COMPOSITE_NOGATE(0, "clkout_pdm_src", mux_sai_src_p, 0,
+ RV1126B_CLKSEL_CON(20), 8, 4, MFLAGS, 0, 8, DFLAGS),
+ GATE(CLKOUT_PDM, "clkout_pdm", "clkout_pdm_src", 0,
+ RV1126B_CLKGATE_CON(2), 6, GFLAGS),
+ COMPOSITE_NODIV(MCLK_ASRC0, "mclk_asrc0", mux_sai_src_p, 0,
+ RV1126B_CLKSEL_CON(16), 12, 4, MFLAGS,
+ RV1126B_CLKGATE_CON(2), 7, GFLAGS),
+ COMPOSITE_NODIV(MCLK_ASRC1, "mclk_asrc1", mux_sai_src_p, 0,
+ RV1126B_CLKSEL_CON(17), 12, 4, MFLAGS,
+ RV1126B_CLKGATE_CON(2), 8, GFLAGS),
+ COMPOSITE_NODIV(MCLK_ASRC2, "mclk_asrc2", mux_sai_src_p, 0,
+ RV1126B_CLKSEL_CON(18), 12, 4, MFLAGS,
+ RV1126B_CLKGATE_CON(2), 9, GFLAGS),
+ COMPOSITE_NODIV(MCLK_ASRC3, "mclk_asrc3", mux_sai_src_p, 0,
+ RV1126B_CLKSEL_CON(19), 12, 4, MFLAGS,
+ RV1126B_CLKGATE_CON(2), 10, GFLAGS),
+ COMPOSITE(CLK_ASRC0, "clk_asrc0", mux_gpll_aupll_p, 0,
+ RV1126B_CLKSEL_CON(21), 6, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(2), 11, GFLAGS),
+ COMPOSITE(CLK_ASRC1, "clk_asrc1", mux_gpll_aupll_p, 0,
+ RV1126B_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(2), 12, GFLAGS),
+ COMPOSITE_NOMUX(CLK_CORE_PLL, "clk_core_pll", "gpll", CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(60), 0, 3, DFLAGS,
+ RV1126B_CLKGATE_CON(5), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_NPU_PLL, "clk_npu_pll", "gpll", CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(60), 6, 3, DFLAGS,
+ RV1126B_CLKGATE_CON(5), 1, GFLAGS),
+ COMPOSITE(CLK_VEPU_PLL, "clk_vepu_pll", mux_gpll_aupll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(61), 4, 2, MFLAGS, 0, 3, DFLAGS,
+ RV1126B_CLKGATE_CON(5), 2, GFLAGS),
+ COMPOSITE(CLK_ISP_PLL, "clk_isp_pll", mux_gpll_aupll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(61), 10, 2, MFLAGS, 6, 4, DFLAGS,
+ RV1126B_CLKGATE_CON(5), 3, GFLAGS),
+ COMPOSITE(CLK_SARADC0_SRC, "clk_saradc0_src", mux_200m_24m_p, 0,
+ RV1126B_CLKSEL_CON(63), 12, 1, MFLAGS, 0, 3, DFLAGS,
+ RV1126B_CLKGATE_CON(5), 6, GFLAGS),
+ COMPOSITE(CLK_SARADC1_SRC, "clk_saradc1_src", mux_200m_24m_p, 0,
+ RV1126B_CLKSEL_CON(63), 13, 1, MFLAGS, 4, 3, DFLAGS,
+ RV1126B_CLKGATE_CON(5), 7, GFLAGS),
+ COMPOSITE(CLK_SARADC2_SRC, "clk_saradc2_src", mux_200m_24m_p, 0,
+ RV1126B_CLKSEL_CON(63), 14, 1, MFLAGS, 8, 3, DFLAGS,
+ RV1126B_CLKGATE_CON(5), 8, GFLAGS),
+ GATE(HCLK_RKNN, "hclk_rknn", "clk_gpll_div8", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(5), 10, GFLAGS),
+ GATE(PCLK_NPU_ROOT, "pclk_npu_root", "clk_cpll_div10", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(5), 11, GFLAGS),
+ COMPOSITE_NODIV(ACLK_VEPU_ROOT, "aclk_vepu_root", mux_500m_400m_200m_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(40), 0, 2, MFLAGS,
+ RV1126B_CLKGATE_CON(5), 12, GFLAGS),
+ GATE(HCLK_VEPU_ROOT, "hclk_vepu_root", "clk_gpll_div8", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(5), 13, GFLAGS),
+ GATE(PCLK_VEPU_ROOT, "pclk_vepu_root", "clk_cpll_div10", 0,
+ RV1126B_CLKGATE_CON(5), 14, GFLAGS),
+ COMPOSITE(CLK_CORE_RGA_SRC, "clk_core_rga_src", mux_gpll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(40), 5, 1, MFLAGS, 2, 3, DFLAGS,
+ RV1126B_CLKGATE_CON(6), 0, GFLAGS),
+ COMPOSITE_NODIV(ACLK_GMAC_ROOT, "aclk_gmac_root", mux_300m_200m_p, 0,
+ RV1126B_CLKSEL_CON(40), 6, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(6), 1, GFLAGS),
+ COMPOSITE_NODIV(ACLK_VI_ROOT, "aclk_vi_root", mux_500m_400m_300m_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(40), 7, 2, MFLAGS,
+ RV1126B_CLKGATE_CON(6), 2, GFLAGS),
+ GATE(HCLK_VI_ROOT, "hclk_vi_root", "clk_gpll_div8", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(6), 3, GFLAGS),
+ GATE(PCLK_VI_ROOT, "pclk_vi_root", "clk_cpll_div10", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(6), 4, GFLAGS),
+ COMPOSITE_NODIV(DCLK_VICAP_ROOT, "dclk_vicap_root", mux_333m_200m_p, 0,
+ RV1126B_CLKSEL_CON(42), 5, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(6), 5, GFLAGS),
+ COMPOSITE(CLK_SYS_DSMC_ROOT, "clk_sys_dsmc_root", mux_24m_gpll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(40), 14, 2, MFLAGS, 9, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(6), 6, GFLAGS),
+ COMPOSITE(ACLK_VDO_ROOT, "aclk_vdo_root", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(42), 4, 1, MFLAGS, 0, 4, DFLAGS,
+ RV1126B_CLKGATE_CON(6), 7, GFLAGS),
+ COMPOSITE(ACLK_RKVDEC_ROOT, "aclk_rkvdec_root", mux_gpll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(42), 10, 1, MFLAGS, 6, 4, DFLAGS,
+ RV1126B_CLKGATE_CON(6), 8, GFLAGS),
+ GATE(HCLK_VDO_ROOT, "hclk_vdo_root", "clk_gpll_div8", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(6), 9, GFLAGS),
+ GATE(PCLK_VDO_ROOT, "pclk_vdo_root", "clk_cpll_div10", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(6), 10, GFLAGS),
+ COMPOSITE(DCLK_VOP, "dclk_vop", mux_gpll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(43), 8, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1126B_CLKGATE_CON(6), 12, GFLAGS),
+ COMPOSITE(DCLK_OOC_SRC, "dclk_ooc_src", mux_gpll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(62), 7, 1, MFLAGS, 8, 8, DFLAGS,
+ RV1126B_CLKGATE_CON(6), 13, GFLAGS),
+ GATE(DCLK_DECOM_SRC, "dclk_decom_src", "clk_gpll_div3", 0,
+ RV1126B_CLKGATE_CON(6), 14, GFLAGS),
+ GATE(PCLK_DDR_ROOT, "pclk_ddr_root", "clk_cpll_div10", 0,
+ RV1126B_CLKGATE_CON(7), 0, GFLAGS),
+ COMPOSITE(ACLK_SYSMEM, "aclk_sysmem", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(44), 3, 1, MFLAGS, 0, 3, DFLAGS,
+ RV1126B_CLKGATE_CON(7), 1, GFLAGS),
+ COMPOSITE_NODIV(ACLK_TOP_ROOT, "aclk_top_root", mux_600m_400m_200m_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(44), 6, 2, MFLAGS,
+ RV1126B_CLKGATE_CON(7), 3, GFLAGS),
+ COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_400m_300m_200m_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(44), 8, 2, MFLAGS,
+ RV1126B_CLKGATE_CON(7), 4, GFLAGS),
+ COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(44), 10, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(7), 5, GFLAGS),
+ GATE(PCLK_BUS_ROOT, "pclk_bus_root", "clk_cpll_div10", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(7), 6, GFLAGS),
+ COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", mux_gpll_cpll_24m_p, 0,
+ RV1126B_CLKSEL_CON(45), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RV1126B_CLKGATE_CON(7), 7, GFLAGS),
+ COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", mux_gpll_cpll_24m_p, 0,
+ RV1126B_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RV1126B_CLKGATE_CON(7), 8, GFLAGS),
+ COMPOSITE(CCLK_EMMC, "cclk_emmc", mux_gpll_cpll_24m_p, 0,
+ RV1126B_CLKSEL_CON(47), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RV1126B_CLKGATE_CON(7), 9, GFLAGS),
+ COMPOSITE(SCLK_2X_FSPI0, "sclk_2x_fspi0", mux_gpll_cpll_24m_p, 0,
+ RV1126B_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RV1126B_CLKGATE_CON(7), 10, GFLAGS),
+ COMPOSITE(CLK_GMAC_PTP_REF_SRC, "clk_gmac_ptp_ref_src", mux_cpll_24m_p, 0,
+ RV1126B_CLKSEL_CON(45), 10, 1, MFLAGS, 11, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(7), 11, GFLAGS),
+ GATE(CLK_GMAC_125M, "clk_gmac_125m", "clk_cpll_div8", 0,
+ RV1126B_CLKGATE_CON(7), 12, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER_ROOT, "clk_timer_root", mux_100m_24m_p, 0,
+ RV1126B_CLKSEL_CON(46), 11, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(7), 13, GFLAGS),
+ COMPOSITE_NODIV(TCLK_WDT_NS_SRC, "tclk_wdt_ns_src", mux_100m_24m_p, 0,
+ RV1126B_CLKSEL_CON(46), 12, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(8), 0, GFLAGS),
+ COMPOSITE_NODIV(TCLK_WDT_S_SRC, "tclk_wdt_s_src", mux_100m_24m_p, 0,
+ RV1126B_CLKSEL_CON(46), 13, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(8), 1, GFLAGS),
+ COMPOSITE_NODIV(TCLK_WDT_HPMCU, "tclk_wdt_hpmcu", mux_100m_24m_p, 0,
+ RV1126B_CLKSEL_CON(46), 14, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(8), 2, GFLAGS),
+ COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_24m_p, 0,
+ RV1126B_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(8), 4, GFLAGS),
+ COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_24m_p, 0,
+ RV1126B_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(8), 5, GFLAGS),
+ COMPOSITE_NODIV(PCLK_PERI_ROOT, "pclk_peri_root", mux_100m_24m_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(47), 12, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(8), 6, GFLAGS),
+ COMPOSITE_NODIV(ACLK_PERI_ROOT, "aclk_peri_root", mux_200m_24m_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(47), 13, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(8), 7, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C_BUS_SRC, "clk_i2c_bus_src", mux_200m_24m_p, 0,
+ RV1126B_CLKSEL_CON(50), 1, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(8), 9, GFLAGS),
+ COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
+ RV1126B_CLKSEL_CON(50), 2, 2, MFLAGS,
+ RV1126B_CLKGATE_CON(8), 10, GFLAGS),
+ COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
+ RV1126B_CLKSEL_CON(50), 4, 2, MFLAGS,
+ RV1126B_CLKGATE_CON(8), 11, GFLAGS),
+ GATE(BUSCLK_PMU_SRC, "busclk_pmu_src", "clk_cpll_div10", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(8), 12, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_24m_p, 0,
+ RV1126B_CLKSEL_CON(50), 8, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(9), 0, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_24m_p, 0,
+ RV1126B_CLKSEL_CON(50), 10, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(9), 2, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_24m_p, 0,
+ RV1126B_CLKSEL_CON(50), 11, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(9), 3, GFLAGS),
+ COMPOSITE_NODIV(CLK_PKA_RKCE_SRC, "clk_pka_rkce_src", mux_300m_200m_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(50), 12, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(9), 4, GFLAGS),
+ COMPOSITE_NODIV(ACLK_RKCE_SRC, "aclk_rkce_src", mux_200m_24m_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(50), 13, 1, MFLAGS,
+ RV1126B_CLKGATE_CON(9), 5, GFLAGS),
+ COMPOSITE_NODIV(ACLK_VCP_ROOT, "aclk_vcp_root", mux_500m_400m_200m_p, CLK_IS_CRITICAL,
+ RV1126B_CLKSEL_CON(48), 12, 2, MFLAGS,
+ RV1126B_CLKGATE_CON(9), 6, GFLAGS),
+ GATE(HCLK_VCP_ROOT, "hclk_vcp_root", "clk_gpll_div8", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(9), 7, GFLAGS),
+ GATE(PCLK_VCP_ROOT, "pclk_vcp_root", "clk_cpll_div10", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(9), 8, GFLAGS),
+ COMPOSITE(CLK_CORE_FEC_SRC, "clk_core_fec_src", mux_gpll_cpll_p, 0,
+ RV1126B_CLKSEL_CON(51), 3, 1, MFLAGS, 0, 3, DFLAGS,
+ RV1126B_CLKGATE_CON(9), 9, GFLAGS),
+ GATE(CLK_50M_GMAC_IOBUF_VI, "clk_50m_gmac_iobuf_vi", "clk_cpll_div20", 0,
+ RV1126B_CLKGATE_CON(9), 11, GFLAGS),
+ GATE(PCLK_TOP_ROOT, "pclk_top_root", "clk_cpll_div10", CLK_IS_CRITICAL,
+ RV1126B_CLKGATE_CON(15), 0, GFLAGS),
+ COMPOSITE(CLK_MIPI0_OUT2IO, "clk_mipi0_out2io", mux_600m_24m_p, 0,
+ RV1126B_CLKSEL_CON(67), 11, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(15), 3, GFLAGS),
+ COMPOSITE(CLK_MIPI1_OUT2IO, "clk_mipi1_out2io", mux_600m_24m_p, 0,
+ RV1126B_CLKSEL_CON(67), 12, 1, MFLAGS, 6, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(15), 4, GFLAGS),
+ COMPOSITE(CLK_MIPI2_OUT2IO, "clk_mipi2_out2io", mux_600m_24m_p, 0,
+ RV1126B_CLKSEL_CON(68), 11, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(15), 5, GFLAGS),
+ COMPOSITE(CLK_MIPI3_OUT2IO, "clk_mipi3_out2io", mux_600m_24m_p, 0,
+ RV1126B_CLKSEL_CON(68), 12, 1, MFLAGS, 6, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(15), 6, GFLAGS),
+ COMPOSITE(CLK_CIF_OUT2IO, "clk_cif_out2io", mux_600m_24m_p, 0,
+ RV1126B_CLKSEL_CON(69), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126B_CLKGATE_CON(15), 7, GFLAGS),
+ COMPOSITE(CLK_MAC_OUT2IO, "clk_mac_out2io", mux_gpll_cpll_24m_p, 0,
+ RV1126B_CLKSEL_CON(69), 6, 2, MFLAGS, 8, 7, DFLAGS,
+ RV1126B_CLKGATE_CON(15), 8, GFLAGS),
+ COMPOSITE_NOMUX(MCLK_SAI0_OUT2IO, "mclk_sai0_out2io", "mclk_sai0", CLK_SET_RATE_PARENT,
+ RV1126B_CLKSEL_CON(70), 0, 4, DFLAGS,
+ RV1126B_CLKGATE_CON(15), 9, GFLAGS),
+ COMPOSITE_NOMUX(MCLK_SAI1_OUT2IO, "mclk_sai1_out2io", "mclk_sai1", CLK_SET_RATE_PARENT,
+ RV1126B_CLKSEL_CON(70), 5, 4, DFLAGS,
+ RV1126B_CLKGATE_CON(15), 10, GFLAGS),
+ COMPOSITE_NOMUX(MCLK_SAI2_OUT2IO, "mclk_sai2_out2io", "mclk_sai2", CLK_SET_RATE_PARENT,
+ RV1126B_CLKSEL_CON(70), 10, 4, DFLAGS,
+ RV1126B_CLKGATE_CON(15), 11, GFLAGS),
+
+ /* pd _npu */
+ MUX(ACLK_RKNN, "aclk_rknn", aclk_npu_root_p, CLK_SET_RATE_PARENT,
+ RV1126B_NPUCLKSEL_CON(0), 1, 1, MFLAGS),
+
+ /* pd_vepu */
+ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vepu_root", 0,
+ RV1126B_VEPUCLKGATE_CON(0), 7, GFLAGS),
+ GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
+ RV1126B_VEPUCLKGATE_CON(0), 8, GFLAGS),
+ GATE(PCLK_IOC_VCCIO3, "pclk_ioc_vccio3", "pclk_vepu_root", CLK_IS_CRITICAL,
+ RV1126B_VEPUCLKGATE_CON(0), 9, GFLAGS),
+ GATE(PCLK_SARADC0, "pclk_saradc0", "pclk_vepu_root", 0,
+ RV1126B_VEPUCLKGATE_CON(0), 10, GFLAGS),
+ MUX(CLK_SARADC0, "clk_saradc0", clk_saradc0_p, CLK_SET_RATE_PARENT,
+ RV1126B_VEPUCLKSEL_CON(0), 2, 1, MFLAGS),
+ GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_vepu_root", 0,
+ RV1126B_VEPUCLKGATE_CON(0), 12, GFLAGS),
+ GATE(HCLK_VEPU, "hclk_vepu", "hclk_vepu_root", 0,
+ RV1126B_VEPUCLKGATE_CON(1), 1, GFLAGS),
+ GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_root", 0,
+ RV1126B_VEPUCLKGATE_CON(1), 2, GFLAGS),
+ COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", clk_core_vepu_p, CLK_SET_RATE_PARENT,
+ RV1126B_VEPUCLKSEL_CON(0), 1, 1, MFLAGS,
+ RV1126B_VEPUCLKGATE_CON(1), 3, GFLAGS),
+
+ /* pd_vcp */
+ GATE(HCLK_FEC, "hclk_fec", "hclk_vcp_root", 0,
+ RV1126B_VCPCLKGATE_CON(1), 0, GFLAGS),
+ GATE(ACLK_FEC, "aclk_fec", "aclk_vcp_root", 0,
+ RV1126B_VCPCLKGATE_CON(1), 1, GFLAGS),
+ COMPOSITE_NODIV(CLK_CORE_FEC, "clk_core_fec", clk_core_fec_p, CLK_SET_RATE_PARENT,
+ RV1126B_VCPCLKSEL_CON(0), 13, 1, MFLAGS,
+ RV1126B_VCPCLKGATE_CON(1), 2, GFLAGS),
+ GATE(HCLK_AVSP, "hclk_avsp", "hclk_vcp_root", 0,
+ RV1126B_VCPCLKGATE_CON(1), 3, GFLAGS),
+ GATE(ACLK_AVSP, "aclk_avsp", "aclk_vcp_root", 0,
+ RV1126B_VCPCLKGATE_CON(1), 4, GFLAGS),
+ GATE(HCLK_AISP, "hclk_aisp", "hclk_vcp_root", 0,
+ RV1126B_VCPCLKGATE_CON(0), 11, GFLAGS),
+ GATE(ACLK_AISP, "aclk_aisp", "aclk_vcp_root", 0,
+ RV1126B_VCPCLKGATE_CON(0), 12, GFLAGS),
+ COMPOSITE_NODIV(CLK_CORE_AISP, "clk_core_aisp", clk_core_aisp_p, CLK_SET_RATE_PARENT,
+ RV1126B_VCPCLKSEL_CON(0), 15, 1, MFLAGS,
+ RV1126B_VCPCLKGATE_CON(0), 13, GFLAGS),
+
+ /* pd_vi */
+ MUX(CLK_CORE_ISP_ROOT, "clk_core_isp_root", clk_core_isp_root_p, CLK_SET_RATE_PARENT,
+ RV1126B_VICLKSEL_CON(0), 1, 1, MFLAGS),
+ GATE(PCLK_DSMC, "pclk_dsmc", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(0), 8, GFLAGS),
+ GATE(ACLK_DSMC, "aclk_dsmc", "hclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(0), 9, GFLAGS),
+ GATE(HCLK_CAN0, "hclk_can0", "hclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(0), 10, GFLAGS),
+ GATE(HCLK_CAN1, "hclk_can1", "hclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(0), 11, GFLAGS),
+ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(1), 0, GFLAGS),
+ GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
+ RV1126B_VICLKGATE_CON(1), 1, GFLAGS),
+ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(1), 2, GFLAGS),
+ GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
+ RV1126B_VICLKGATE_CON(1), 3, GFLAGS),
+ GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(1), 4, GFLAGS),
+ GATE(DBCLK_GPIO5, "dbclk_gpio5", "xin24m", 0,
+ RV1126B_VICLKGATE_CON(1), 5, GFLAGS),
+ GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(1), 6, GFLAGS),
+ GATE(DBCLK_GPIO6, "dbclk_gpio6", "xin24m", 0,
+ RV1126B_VICLKGATE_CON(1), 7, GFLAGS),
+ GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(1), 8, GFLAGS),
+ GATE(DBCLK_GPIO7, "dbclk_gpio7", "xin24m", 0,
+ RV1126B_VICLKGATE_CON(1), 9, GFLAGS),
+ GATE(PCLK_IOC_VCCIO2, "pclk_ioc_vccio2", "pclk_vi_root", CLK_IS_CRITICAL,
+ RV1126B_VICLKGATE_CON(1), 10, GFLAGS),
+ GATE(PCLK_IOC_VCCIO4, "pclk_ioc_vccio4", "pclk_vi_root", CLK_IS_CRITICAL,
+ RV1126B_VICLKGATE_CON(1), 11, GFLAGS),
+ GATE(PCLK_IOC_VCCIO5, "pclk_ioc_vccio5", "pclk_vi_root", CLK_IS_CRITICAL,
+ RV1126B_VICLKGATE_CON(1), 12, GFLAGS),
+ GATE(PCLK_IOC_VCCIO6, "pclk_ioc_vccio6", "pclk_vi_root", CLK_IS_CRITICAL,
+ RV1126B_VICLKGATE_CON(1), 13, GFLAGS),
+ GATE(PCLK_IOC_VCCIO7, "pclk_ioc_vccio7", "pclk_vi_root", CLK_IS_CRITICAL,
+ RV1126B_VICLKGATE_CON(1), 14, GFLAGS),
+ GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(2), 0, GFLAGS),
+ GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(2), 1, GFLAGS),
+ GATE(CLK_CORE_ISP, "clk_core_isp", "clk_core_isp_root", 0,
+ RV1126B_VICLKGATE_CON(2), 2, GFLAGS),
+ GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(2), 3, GFLAGS),
+ GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(2), 4, GFLAGS),
+ GATE(DCLK_VICAP, "dclk_vicap", "dclk_vicap_root", 0,
+ RV1126B_VICLKGATE_CON(2), 5, GFLAGS),
+ GATE(ISP0CLK_VICAP, "isp0clk_vicap", "clk_core_isp_root", 0,
+ RV1126B_VICLKGATE_CON(2), 6, GFLAGS),
+ GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(2), 7, GFLAGS),
+ GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(2), 8, GFLAGS),
+ GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_core_isp_root", 0,
+ RV1126B_VICLKGATE_CON(2), 9, GFLAGS),
+ GATE(HCLK_VPSL, "hclk_vpsl", "hclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(2), 10, GFLAGS),
+ GATE(ACLK_VPSL, "aclk_vpsl", "aclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(2), 11, GFLAGS),
+ GATE(CLK_CORE_VPSL, "clk_core_vpsl", "clk_core_isp_root", 0,
+ RV1126B_VICLKGATE_CON(2), 12, GFLAGS),
+ GATE(PCLK_CSI2HOST0, "pclk_csi2host0", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(3), 0, GFLAGS),
+ GATE(DCLK_CSI2HOST0, "dclk_csi2host0", "dclk_vicap_root", 0,
+ RV1126B_VICLKGATE_CON(3), 1, GFLAGS),
+ GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(3), 2, GFLAGS),
+ GATE(DCLK_CSI2HOST1, "dclk_csi2host1", "dclk_vicap_root", 0,
+ RV1126B_VICLKGATE_CON(3), 3, GFLAGS),
+ GATE(PCLK_CSI2HOST2, "pclk_csi2host2", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(3), 4, GFLAGS),
+ GATE(DCLK_CSI2HOST2, "dclk_csi2host2", "dclk_vicap_root", 0,
+ RV1126B_VICLKGATE_CON(3), 5, GFLAGS),
+ GATE(PCLK_CSI2HOST3, "pclk_csi2host3", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(3), 6, GFLAGS),
+ GATE(DCLK_CSI2HOST3, "dclk_csi2host3", "dclk_vicap_root", 0,
+ RV1126B_VICLKGATE_CON(3), 7, GFLAGS),
+ GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(3), 8, GFLAGS),
+ GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_root", 0,
+ RV1126B_VICLKGATE_CON(3), 9, GFLAGS),
+ GATE(PCLK_GMAC, "pclk_gmac", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(3), 10, GFLAGS),
+ MUX(CLK_GMAC_PTP_REF, "clk_gmac_ptp_ref", clk_gmac_ptp_ref_p, CLK_SET_RATE_PARENT,
+ RV1126B_VICLKSEL_CON(0), 14, 1, MFLAGS),
+ GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(3), 11, GFLAGS),
+ GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(3), 12, GFLAGS),
+ GATE(PCLK_MACPHY, "pclk_macphy", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(3), 13, GFLAGS),
+ GATE(PCLK_SARADC1, "pclk_saradc1", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(4), 0, GFLAGS),
+ MUX(CLK_SARADC1, "clk_saradc1", clk_saradc1_p, CLK_SET_RATE_PARENT,
+ RV1126B_VICLKSEL_CON(0), 2, 1, MFLAGS),
+ GATE(PCLK_SARADC2, "pclk_saradc2", "pclk_vi_root", 0,
+ RV1126B_VICLKGATE_CON(4), 2, GFLAGS),
+ MUX(CLK_SARADC2, "clk_saradc2", clk_saradc2_p, CLK_SET_RATE_PARENT,
+ RV1126B_VICLKSEL_CON(0), 3, 1, MFLAGS),
+ COMPOSITE_NODIV(CLK_MACPHY, "clk_macphy", clk_macphy_p, 0,
+ RV1126B_VICLKSEL_CON(1), 1, 1, MFLAGS,
+ RV1126B_VICLKGATE_CON(0), 12, GFLAGS),
+
+ /* pd_vdo */
+ GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_root", 0,
+ RV1126B_VDOCLKGATE_CON(0), 7, GFLAGS),
+ GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(0), 8, GFLAGS),
+ GATE(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", "aclk_rkvdec_root", 0,
+ RV1126B_VDOCLKGATE_CON(0), 9, GFLAGS),
+ GATE(ACLK_VOP, "aclk_vop", "aclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(0), 10, GFLAGS),
+ GATE(HCLK_VOP, "hclk_vop", "hclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(0), 11, GFLAGS),
+ GATE(ACLK_OOC, "aclk_ooc", "aclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(0), 13, GFLAGS),
+ GATE(HCLK_OOC, "hclk_ooc", "hclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(0), 14, GFLAGS),
+ GATE(HCLK_RKJPEG, "hclk_rkjpeg", "hclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(1), 3, GFLAGS),
+ GATE(ACLK_RKJPEG, "aclk_rkjpeg", "aclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(1), 4, GFLAGS),
+ GATE(ACLK_RKMMU_DECOM, "aclk_rkmmu_decom", "aclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(1), 5, GFLAGS),
+ GATE(HCLK_RKMMU_DECOM, "hclk_rkmmu_decom", "hclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(1), 6, GFLAGS),
+ GATE(DCLK_DECOM, "dclk_decom", "dclk_decom_src", 0,
+ RV1126B_VDOCLKGATE_CON(1), 8, GFLAGS),
+ GATE(ACLK_DECOM, "aclk_decom", "aclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(1), 9, GFLAGS),
+ GATE(PCLK_DECOM, "pclk_decom", "pclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(1), 10, GFLAGS),
+ GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(1), 12, GFLAGS),
+ GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_vdo_root", 0,
+ RV1126B_VDOCLKGATE_CON(1), 13, GFLAGS),
+
+ /* pd_ddr */
+ GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL,
+ RV1126B_DDRCLKGATE_CON(0), 2, GFLAGS),
+ GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IS_CRITICAL,
+ RV1126B_DDRCLKGATE_CON(0), 3, GFLAGS),
+ GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
+ RV1126B_DDRCLKGATE_CON(0), 4, GFLAGS),
+ GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL,
+ RV1126B_DDRCLKGATE_CON(0), 5, GFLAGS),
+ GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL,
+ RV1126B_DDRCLKGATE_CON(0), 8, GFLAGS),
+ GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_ddr_root", CLK_IS_CRITICAL,
+ RV1126B_DDRCLKGATE_CON(0), 9, GFLAGS),
+
+ /* pd_pmu*/
+ COMPOSITE_NODIV(CLK_RCOSC_SRC, "clk_rcosc_src", clk_rcosc_src_p, 0,
+ RV1126B_PMUCLKSEL_CON(1), 0, 3, MFLAGS,
+ RV1126B_PMUCLKGATE_CON(0), 0, GFLAGS),
+ COMPOSITE_NOGATE(BUSCLK_PMU_MUX, "busclk_pmu_mux", busclk_pmu_mux_p, 0,
+ RV1126B_PMUCLKSEL_CON(1), 3, 1, MFLAGS, 4, 2, DFLAGS),
+ GATE(BUSCLK_PMU_ROOT, "busclk_pmu_root", "busclk_pmu_mux", 0,
+ RV1126B_PMUCLKGATE_CON(0), 1, GFLAGS),
+ GATE(BUSCLK_PMU1_ROOT, "busclk_pmu1_root", "busclk_pmu_mux", CLK_IS_CRITICAL,
+ RV1126B_PMUCLKGATE_CON(3), 11, GFLAGS),
+ GATE(PCLK_PMU, "pclk_pmu", "busclk_pmu_root", CLK_IS_CRITICAL,
+ RV1126B_PMUCLKGATE_CON(0), 6, GFLAGS),
+ MUX(0, "xin_rc_src", clk_xin_rc_div_p, 0,
+ RV1126B_PMUCLKSEL_CON(2), 0, 1, MFLAGS),
+ COMPOSITE_FRACMUX_NOGATE(CLK_XIN_RC_DIV, "clk_xin_rc_div", "xin_rc_src", CLK_SET_RATE_PARENT,
+ RV1126B_PMUCLKSEL_CON(8), 0,
+ &rv1126b_rcdiv_pmu_fracmux),
+ GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "busclk_pmu_root", 0,
+ RV1126B_PMUCLKGATE_CON(0), 7, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", mux_24m_32k_p, 0,
+ RV1126B_PMUCLKSEL_CON(2), 4, 1, MFLAGS,
+ RV1126B_PMUCLKGATE_CON(0), 8, GFLAGS),
+ GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "busclk_pmu_root", CLK_IS_CRITICAL,
+ RV1126B_PMUCLKGATE_CON(0), 10, GFLAGS),
+ COMPOSITE(CLK_PMU_HP_TIMER, "clk_pmu_hp_timer", mux_cpll_24m_p, CLK_IS_CRITICAL,
+ RV1126B_PMUCLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126B_PMUCLKGATE_CON(0), 11, GFLAGS),
+ GATE(CLK_PMU_32K_HP_TIMER, "clk_pmu_32k_hp_timer", "clk_32k", CLK_IS_CRITICAL,
+ RV1126B_PMUCLKGATE_CON(0), 13, GFLAGS),
+ GATE(PCLK_PWM1, "pclk_pwm1", "busclk_pmu_root", 0,
+ RV1126B_PMUCLKGATE_CON(1), 0, GFLAGS),
+ COMPOSITE(CLK_PWM1, "clk_pwm1", mux_24m_rcosc_buspmu_p, 0,
+ RV1126B_PMUCLKSEL_CON(2), 8, 2, MFLAGS, 6, 2, DFLAGS,
+ RV1126B_PMUCLKGATE_CON(1), 1, GFLAGS),
+ GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
+ RV1126B_PMUCLKGATE_CON(1), 2, GFLAGS),
+ GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_32k", 0,
+ RV1126B_PMUCLKGATE_CON(1), 3, GFLAGS),
+ GATE(PCLK_I2C2, "pclk_i2c2", "busclk_pmu_root", 0,
+ RV1126B_PMUCLKGATE_CON(1), 6, GFLAGS),
+ COMPOSITE(CLK_I2C2, "clk_i2c2", mux_24m_rcosc_buspmu_p, 0,
+ RV1126B_PMUCLKSEL_CON(2), 14, 2, MFLAGS, 12, 2, DFLAGS,
+ RV1126B_PMUCLKGATE_CON(1), 7, GFLAGS),
+ GATE(PCLK_UART0, "pclk_uart0", "busclk_pmu_root", 0,
+ RV1126B_PMUCLKGATE_CON(1), 8, GFLAGS),
+ COMPOSITE_NODIV(SCLK_UART0, "sclk_uart0", sclk_uart0_p, CLK_SET_RATE_PARENT,
+ RV1126B_PMUCLKSEL_CON(3), 0, 2, MFLAGS,
+ RV1126B_PMUCLKGATE_CON(1), 11, GFLAGS),
+ GATE(PCLK_RCOSC_CTRL, "pclk_rcosc_ctrl", "busclk_pmu_root", CLK_IS_CRITICAL,
+ RV1126B_PMUCLKGATE_CON(2), 0, GFLAGS),
+ COMPOSITE_NODIV(CLK_OSC_RCOSC_CTRL, "clk_osc_rcosc_ctrl", clk_osc_rcosc_ctrl_p, CLK_IS_CRITICAL,
+ RV1126B_PMUCLKSEL_CON(3), 2, 1, MFLAGS,
+ RV1126B_PMUCLKGATE_CON(2), 1, GFLAGS),
+ GATE(CLK_REF_RCOSC_CTRL, "clk_ref_rcosc_ctrl", "xin24m", CLK_IS_CRITICAL,
+ RV1126B_PMUCLKGATE_CON(2), 2, GFLAGS),
+ GATE(PCLK_IOC_PMUIO0, "pclk_ioc_pmuio0", "busclk_pmu_root", CLK_IS_CRITICAL,
+ RV1126B_PMUCLKGATE_CON(2), 3, GFLAGS),
+ GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
+ RV1126B_PMUCLKGATE_CON(2), 6, GFLAGS),
+ GATE(CLK_PREROLL, "clk_preroll", "busclk_pmu_root", 0,
+ RV1126B_PMUCLKGATE_CON(2), 7, GFLAGS),
+ GATE(CLK_PREROLL_32K, "clk_preroll_32k", "clk_32k", 0,
+ RV1126B_PMUCLKGATE_CON(2), 8, GFLAGS),
+ GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "busclk_pmu_root", CLK_IS_CRITICAL,
+ RV1126B_PMUCLKGATE_CON(2), 9, GFLAGS),
+ GATE(PCLK_WDT_LPMCU, "pclk_wdt_lpmcu", "busclk_pmu_root", 0,
+ RV1126B_PMUCLKGATE_CON(3), 0, GFLAGS),
+ COMPOSITE_NODIV(TCLK_WDT_LPMCU, "tclk_wdt_lpmcu", mux_24m_rcosc_buspmu_32k_p, 0,
+ RV1126B_PMUCLKSEL_CON(3), 6, 2, MFLAGS,
+ RV1126B_PMUCLKGATE_CON(3), 1, GFLAGS),
+ GATE(CLK_LPMCU, "clk_lpmcu", "busclk_pmu_root", 0,
+ RV1126B_PMUCLKGATE_CON(3), 2, GFLAGS),
+ GATE(CLK_LPMCU_RTC, "clk_lpmcu_rtc", "xin24m", 0,
+ RV1126B_PMUCLKGATE_CON(3), 3, GFLAGS),
+ GATE(PCLK_LPMCU_MAILBOX, "pclk_lpmcu_mailbox", "busclk_pmu_root", 0,
+ RV1126B_PMUCLKGATE_CON(3), 4, GFLAGS),
+
+ /* pd_pmu1 */
+ GATE(PCLK_SPI2AHB, "pclk_spi2ahb", "busclk_pmu_root", 0,
+ RV1126B_PMU1CLKGATE_CON(0), 0, GFLAGS),
+ GATE(HCLK_SPI2AHB, "hclk_spi2ahb", "busclk_pmu_root", 0,
+ RV1126B_PMU1CLKGATE_CON(0), 1, GFLAGS),
+ GATE(HCLK_FSPI1, "hclk_fspi1", "busclk_pmu_root", 0,
+ RV1126B_PMU1CLKGATE_CON(0), 2, GFLAGS),
+ GATE(HCLK_XIP_FSPI1, "hclk_xip_fspi1", "busclk_pmu_root", 0,
+ RV1126B_PMU1CLKGATE_CON(0), 3, GFLAGS),
+ COMPOSITE(SCLK_1X_FSPI1, "sclk_1x_fspi1", mux_24m_rcosc_buspmu_p, 0,
+ RV1126B_PMU1CLKSEL_CON(0), 0, 2, MFLAGS, 2, 3, DFLAGS,
+ RV1126B_PMU1CLKGATE_CON(0), 4, GFLAGS),
+ GATE(PCLK_IOC_PMUIO1, "pclk_ioc_pmuio1", "busclk_pmu_root", CLK_IS_CRITICAL,
+ RV1126B_PMU1CLKGATE_CON(0), 5, GFLAGS),
+ GATE(PCLK_AUDIO_ADC_PMU, "pclk_audio_adc_pmu", "busclk_pmu_root", 0,
+ RV1126B_PMU1CLKGATE_CON(0), 8, GFLAGS),
+
+ COMPOSITE(MCLK_LPSAI, "mclk_lpsai", mux_24m_rcosc_buspmu_p, 0,
+ RV1126B_PMU1CLKSEL_CON(0), 6, 2, MFLAGS, 8, 5, DFLAGS,
+ RV1126B_PMU1CLKGATE_CON(1), 3, GFLAGS),
+ GATE(MCLK_AUDIO_ADC_PMU, "mclk_audio_adc_pmu", "mclk_lpsai", CLK_IS_CRITICAL,
+ RV1126B_PMU1CLKGATE_CON(0), 9, GFLAGS),
+ FACTOR(MCLK_AUDIO_ADC_DIV4_PMU, "mclk_audio_adc_div4_pmu", "mclk_audio_adc_pmu", 0, 1, 4),
+
+ /* pd_bus */
+ GATE(ACLK_GIC400, "aclk_gic400", "hclk_bus_root", CLK_IS_CRITICAL,
+ RV1126B_BUSCLKGATE_CON(0), 8, GFLAGS),
+ GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(0), 10, GFLAGS),
+ GATE(TCLK_WDT_NS, "tclk_wdt_ns", "tclk_wdt_ns_src", 0,
+ RV1126B_BUSCLKGATE_CON(0), 11, GFLAGS),
+ GATE(PCLK_WDT_HPMCU, "pclk_wdt_hpmcu", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(1), 0, GFLAGS),
+ GATE(HCLK_CACHE, "hclk_cache", "aclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(1), 2, GFLAGS),
+ GATE(PCLK_HPMCU_MAILBOX, "pclk_hpmcu_mailbox", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(1), 3, GFLAGS),
+ GATE(PCLK_HPMCU_INTMUX, "pclk_hpmcu_intmux", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(1), 4, GFLAGS),
+ GATE(CLK_HPMCU, "clk_hpmcu", "aclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(1), 5, GFLAGS),
+ GATE(CLK_HPMCU_RTC, "clk_hpmcu_rtc", "xin24m", 0,
+ RV1126B_BUSCLKGATE_CON(1), 10, GFLAGS),
+ GATE(PCLK_RKDMA, "pclk_rkdma", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(1), 11, GFLAGS),
+ GATE(ACLK_RKDMA, "aclk_rkdma", "aclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(1), 12, GFLAGS),
+ GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(2), 0, GFLAGS),
+ GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(2), 1, GFLAGS),
+ GATE(HCLK_RGA, "hclk_rga", "hclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(2), 2, GFLAGS),
+ GATE(ACLK_RGA, "aclk_rga", "aclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(2), 3, GFLAGS),
+ GATE(CLK_CORE_RGA, "clk_core_rga", "clk_core_rga_src", 0,
+ RV1126B_BUSCLKGATE_CON(2), 4, GFLAGS),
+ GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(2), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER0, "clk_timer0", clk_timer0_parents_p, 0,
+ RV1126B_BUSCLKSEL_CON(2), 0, 2, MFLAGS,
+ RV1126B_BUSCLKGATE_CON(2), 6, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER1, "clk_timer1", clk_timer1_parents_p, 0,
+ RV1126B_BUSCLKSEL_CON(2), 2, 2, MFLAGS,
+ RV1126B_BUSCLKGATE_CON(2), 7, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER2, "clk_timer2", clk_timer2_parents_p, 0,
+ RV1126B_BUSCLKSEL_CON(2), 4, 2, MFLAGS,
+ RV1126B_BUSCLKGATE_CON(2), 8, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER3, "clk_timer3", clk_timer3_parents_p, 0,
+ RV1126B_BUSCLKSEL_CON(2), 6, 2, MFLAGS,
+ RV1126B_BUSCLKGATE_CON(2), 9, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER4, "clk_timer4", clk_timer4_parents_p, 0,
+ RV1126B_BUSCLKSEL_CON(2), 8, 2, MFLAGS,
+ RV1126B_BUSCLKGATE_CON(2), 10, GFLAGS),
+ GATE(HCLK_RKRNG_S_NS, "hclk_rkrng_s_ns", "hclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(2), 14, GFLAGS),
+ GATE(HCLK_RKRNG_NS, "hclk_rkrng_ns", "hclk_rkrng_s_ns", 0,
+ RV1126B_BUSCLKGATE_CON(2), 15, GFLAGS),
+ GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", CLK_IS_CRITICAL,
+ RV1126B_BUSCLKGATE_CON(2), 11, GFLAGS),
+ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(3), 0, GFLAGS),
+ GATE(CLK_I2C0, "clk_i2c0", "clk_i2c_bus_src", 0,
+ RV1126B_BUSCLKGATE_CON(3), 1, GFLAGS),
+ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(3), 2, GFLAGS),
+ GATE(CLK_I2C1, "clk_i2c1", "clk_i2c_bus_src", 0,
+ RV1126B_BUSCLKGATE_CON(3), 3, GFLAGS),
+ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(3), 4, GFLAGS),
+ GATE(CLK_I2C3, "clk_i2c3", "clk_i2c_bus_src", 0,
+ RV1126B_BUSCLKGATE_CON(3), 5, GFLAGS),
+ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(3), 6, GFLAGS),
+ GATE(CLK_I2C4, "clk_i2c4", "clk_i2c_bus_src", 0,
+ RV1126B_BUSCLKGATE_CON(3), 7, GFLAGS),
+ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(3), 8, GFLAGS),
+ GATE(CLK_I2C5, "clk_i2c5", "clk_i2c_bus_src", 0,
+ RV1126B_BUSCLKGATE_CON(3), 9, GFLAGS),
+ GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(3), 10, GFLAGS),
+ GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(3), 12, GFLAGS),
+ GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(4), 0, GFLAGS),
+ GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0,
+ RV1126B_BUSCLKGATE_CON(4), 1, GFLAGS),
+ GATE(CLK_RC_PWM0, "clk_rc_pwm0", "xin24m", 0,
+ RV1126B_BUSCLKGATE_CON(4), 2, GFLAGS),
+ GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(4), 3, GFLAGS),
+ GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0,
+ RV1126B_BUSCLKGATE_CON(4), 4, GFLAGS),
+ GATE(CLK_RC_PWM2, "clk_rc_pwm2", "xin24m", 0,
+ RV1126B_BUSCLKGATE_CON(4), 5, GFLAGS),
+ GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(4), 6, GFLAGS),
+ GATE(CLK_OSC_PWM3, "clk_osc_pwm3", "xin24m", 0,
+ RV1126B_BUSCLKGATE_CON(4), 7, GFLAGS),
+ GATE(CLK_RC_PWM3, "clk_rc_pwm3", "xin24m", 0,
+ RV1126B_BUSCLKGATE_CON(4), 8, GFLAGS),
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(4), 9, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(4), 10, GFLAGS),
+ GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(4), 11, GFLAGS),
+ GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(4), 12, GFLAGS),
+ GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(4), 13, GFLAGS),
+ GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(4), 14, GFLAGS),
+ GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(4), 15, GFLAGS),
+ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", CLK_IS_CRITICAL,
+ RV1126B_BUSCLKGATE_CON(5), 0, GFLAGS),
+ GATE(CLK_TSADC, "clk_tsadc", "xin24m", CLK_IS_CRITICAL,
+ RV1126B_BUSCLKGATE_CON(5), 1, GFLAGS),
+ GATE(HCLK_SAI0, "hclk_sai0", "hclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(5), 2, GFLAGS),
+ GATE(HCLK_SAI1, "hclk_sai1", "hclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(5), 4, GFLAGS),
+ GATE(HCLK_SAI2, "hclk_sai2", "hclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(5), 6, GFLAGS),
+ GATE(HCLK_RKDSM, "hclk_rkdsm", "hclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(5), 8, GFLAGS),
+ GATE(MCLK_RKDSM, "mclk_rkdsm", "mclk_sai2", 0,
+ RV1126B_BUSCLKGATE_CON(5), 9, GFLAGS),
+ GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(5), 10, GFLAGS),
+ GATE(HCLK_ASRC0, "hclk_asrc0", "hclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(5), 11, GFLAGS),
+ GATE(HCLK_ASRC1, "hclk_asrc1", "hclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(5), 12, GFLAGS),
+ GATE(PCLK_AUDIO_ADC_BUS, "pclk_audio_adc_bus", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(5), 13, GFLAGS),
+ GATE(MCLK_AUDIO_ADC_BUS, "mclk_audio_adc_bus", "mclk_sai2", 0,
+ RV1126B_BUSCLKGATE_CON(5), 14, GFLAGS),
+ FACTOR(MCLK_AUDIO_ADC_DIV4_BUS, "mclk_audio_adc_div4_bus", "mclk_audio_adc_bus", 0, 1, 4),
+ GATE(PCLK_RKCE, "pclk_rkce", "pclk_bus_root", CLK_IS_CRITICAL,
+ RV1126B_BUSCLKGATE_CON(6), 0, GFLAGS),
+ GATE(HCLK_NS_RKCE, "hclk_ns_rkce", "hclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(6), 1, GFLAGS),
+ GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(6), 2, GFLAGS),
+ GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
+ RV1126B_BUSCLKGATE_CON(6), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
+ RV1126B_BUSCLKSEL_CON(2), 12, 3, DFLAGS,
+ RV1126B_BUSCLKGATE_CON(6), 4, GFLAGS),
+ GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_bus_root", 0,
+ RV1126B_BUSCLKGATE_CON(6), 6, GFLAGS),
+ GATE(CLK_TSADC_PHYCTRL, "clk_tsadc_phyctrl", "xin24m", CLK_IS_CRITICAL,
+ RV1126B_BUSCLKGATE_CON(6), 8, GFLAGS),
+ MUX(LRCK_SRC_ASRC0, "lrck_src_asrc0", lrck_src_asrc_p, 0,
+ RV1126B_BUSCLKSEL_CON(3), 0, 3, MFLAGS),
+ MUX(LRCK_DST_ASRC0, "lrck_dst_asrc0", lrck_src_asrc_p, 0,
+ RV1126B_BUSCLKSEL_CON(3), 4, 3, MFLAGS),
+ MUX(LRCK_SRC_ASRC1, "lrck_src_asrc1", lrck_src_asrc_p, 0,
+ RV1126B_BUSCLKSEL_CON(3), 8, 3, MFLAGS),
+ MUX(LRCK_DST_ASRC1, "lrck_dst_asrc1", lrck_src_asrc_p, 0,
+ RV1126B_BUSCLKSEL_CON(3), 12, 3, MFLAGS),
+ GATE(ACLK_NSRKCE, "aclk_nsrkce", "aclk_rkce_src", 0,
+ RV1126B_BUSCLKGATE_CON(2), 12, GFLAGS),
+ GATE(CLK_PKA_NSRKCE, "clk_pka_nsrkce", "clk_pka_rkce_src", 0,
+ RV1126B_BUSCLKGATE_CON(2), 13, GFLAGS),
+
+ /* pd_peri */
+ DIV(PCLK_RTC_ROOT, "pclk_rtc_root", "pclk_peri_root", 0,
+ RV1126B_PERICLKSEL_CON(0), 0, 2, DFLAGS),
+ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri_root", 0,
+ RV1126B_PERICLKGATE_CON(0), 5, GFLAGS),
+ GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
+ RV1126B_PERICLKGATE_CON(0), 6, GFLAGS),
+ GATE(PCLK_IOC_VCCIO1, "pclk_ioc_vccio1", "pclk_peri_root", CLK_IS_CRITICAL,
+ RV1126B_PERICLKGATE_CON(0), 7, GFLAGS),
+ GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri_root", 0,
+ RV1126B_PERICLKGATE_CON(0), 8, GFLAGS),
+ GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0,
+ RV1126B_PERICLKGATE_CON(0), 9, GFLAGS),
+ GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0,
+ RV1126B_PERICLKGATE_CON(0), 10, GFLAGS),
+ GATE(HCLK_USB2HOST, "hclk_usb2host", "aclk_peri_root", 0,
+ RV1126B_PERICLKGATE_CON(0), 11, GFLAGS),
+ GATE(HCLK_ARB_USB2HOST, "hclk_arb_usb2host", "aclk_peri_root", 0,
+ RV1126B_PERICLKGATE_CON(0), 12, GFLAGS),
+ GATE(PCLK_RTC_TEST, "pclk_rtc_test", "pclk_rtc_root", 0,
+ RV1126B_PERICLKGATE_CON(0), 13, GFLAGS),
+ GATE(HCLK_EMMC, "hclk_emmc", "aclk_peri_root", 0,
+ RV1126B_PERICLKGATE_CON(1), 0, GFLAGS),
+ GATE(HCLK_FSPI0, "hclk_fspi0", "aclk_peri_root", 0,
+ RV1126B_PERICLKGATE_CON(1), 1, GFLAGS),
+ GATE(HCLK_XIP_FSPI0, "hclk_xip_fspi0", "aclk_peri_root", 0,
+ RV1126B_PERICLKGATE_CON(1), 2, GFLAGS),
+ GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri_root", 0,
+ RV1126B_PERICLKGATE_CON(1), 8, GFLAGS),
+ GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri_root", 0,
+ RV1126B_PERICLKGATE_CON(1), 10, GFLAGS),
+ COMPOSITE_NOMUX(CLK_REF_PIPEPHY_CPLL_SRC, "clk_ref_pipephy_cpll_src", "cpll", 0,
+ RV1126B_PERICLKSEL_CON(1), 0, 6, DFLAGS,
+ RV1126B_PERICLKGATE_CON(1), 14, GFLAGS),
+ MUX(CLK_REF_PIPEPHY, "clk_ref_pipephy", clk_ref_pipephy_p, 0,
+ RV1126B_PERICLKSEL_CON(1), 12, 1, MFLAGS),
+};
+
+static struct rockchip_clk_branch rv1126b_armclk __initdata =
+ MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ RV1126B_CORECLKSEL_CON(0), 1, 1, MFLAGS);
+
+static void __init rv1126b_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ void __iomem *reg_base;
+ unsigned long clk_nr_clks;
+
+ clk_nr_clks = rockchip_clk_find_max_clk_id(rv1126b_clk_branches,
+ ARRAY_SIZE(rv1126b_clk_branches)) + 1;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rv1126b_pll_clks,
+ ARRAY_SIZE(rv1126b_pll_clks),
+ 0);
+
+ rockchip_clk_register_branches(ctx, rv1126b_clk_branches,
+ ARRAY_SIZE(rv1126b_clk_branches));
+
+ rockchip_clk_register_armclk_multi_pll(ctx, &rv1126b_armclk,
+ rv1126b_cpuclk_rates,
+ ARRAY_SIZE(rv1126b_cpuclk_rates));
+
+ rv1126b_rst_init(np, reg_base);
+
+ rockchip_register_restart_notifier(ctx, RV1126B_GLB_SRST_FST, NULL);
+
+ rockchip_clk_of_add_provider(np, ctx);
+
+ /* pvtpll src init */
+ writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_CORECLKSEL_CON(0));
+ writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_NPUCLKSEL_CON(0));
+ writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VICLKSEL_CON(0));
+ writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VEPUCLKSEL_CON(0));
+ writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VCPCLKSEL_CON(0));
+}
+
+CLK_OF_DECLARE(rv1126b_cru, "rockchip,rv1126b-cru", rv1126b_clk_init);
+
+struct clk_rv1126b_inits {
+ void (*inits)(struct device_node *np);
+};
+
+static const struct clk_rv1126b_inits clk_rv1126b_init = {
+ .inits = rv1126b_clk_init,
+};
+
+static const struct of_device_id clk_rv1126b_match_table[] = {
+ {
+ .compatible = "rockchip,rv1126b-cru",
+ .data = &clk_rv1126b_init,
+ },
+ { }
+};
+
+static int clk_rv1126b_probe(struct platform_device *pdev)
+{
+ const struct clk_rv1126b_inits *init_data;
+ struct device *dev = &pdev->dev;
+
+ init_data = device_get_match_data(dev);
+ if (!init_data)
+ return -EINVAL;
+
+ if (init_data->inits)
+ init_data->inits(dev->of_node);
+
+ return 0;
+}
+
+static struct platform_driver clk_rv1126b_driver = {
+ .probe = clk_rv1126b_probe,
+ .driver = {
+ .name = "clk-rv1126b",
+ .of_match_table = clk_rv1126b_match_table,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(clk_rv1126b_driver, clk_rv1126b_probe);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 19caf26c991b..2601df3b1066 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -722,6 +722,30 @@ void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
}
EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
+void rockchip_clk_register_armclk_multi_pll(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ const struct rockchip_cpuclk_rate_table *rates,
+ int nrates)
+{
+ struct clk *clk;
+
+ clk = rockchip_clk_register_cpuclk_multi_pll(list->name, list->parent_names,
+ list->num_parents, ctx->reg_base,
+ list->muxdiv_offset, list->mux_shift,
+ list->mux_width, list->mux_flags,
+ list->div_offset, list->div_shift,
+ list->div_width, list->div_flags,
+ list->flags, &ctx->lock, rates, nrates);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register clock %s: %ld\n",
+ __func__, list->name, PTR_ERR(clk));
+ return;
+ }
+
+ rockchip_clk_set_lookup(ctx, clk, list->id);
+}
+EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk_multi_pll);
+
void rockchip_clk_protect_critical(const char *const clocks[],
int nclocks)
{
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 7c5e74c7a2e2..b2fff1d13a4a 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -99,6 +99,73 @@ struct clk;
#define RV1126_EMMC_CON0 0x450
#define RV1126_EMMC_CON1 0x454
+#define RV1126B_TOPCRU_BASE 0x0
+#define RV1126B_BUSCRU_BASE 0x10000
+#define RV1126B_PERICRU_BASE 0x20000
+#define RV1126B_CORECRU_BASE 0x30000
+#define RV1126B_PMUCRU_BASE 0x40000
+#define RV1126B_PMU1CRU_BASE 0x50000
+#define RV1126B_DDRCRU_BASE 0x60000
+#define RV1126B_SUBDDRCRU_BASE 0x68000
+#define RV1126B_VICRU_BASE 0x70000
+#define RV1126B_VEPUCRU_BASE 0x80000
+#define RV1126B_NPUCRU_BASE 0x90000
+#define RV1126B_VDOCRU_BASE 0xA0000
+#define RV1126B_VCPCRU_BASE 0xB0000
+
+#define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE)
+#define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE)
+#define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE)
+#define RV1126B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_TOPCRU_BASE)
+#define RV1126B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_TOPCRU_BASE)
+#define RV1126B_GLB_SRST_FST (0xc08 + RV1126B_TOPCRU_BASE)
+#define RV1126B_GLB_SRST_SND (0xc0c + RV1126B_TOPCRU_BASE)
+#define RV1126B_CLK_CM_FRAC0_DIV_H (0xcc0 + RV1126B_TOPCRU_BASE)
+#define RV1126B_CLK_CM_FRAC1_DIV_H (0xcc4 + RV1126B_TOPCRU_BASE)
+#define RV1126B_CLK_CM_FRAC2_DIV_H (0xcc8 + RV1126B_TOPCRU_BASE)
+#define RV1126B_CLK_UART_FRAC0_DIV_H (0xccc + RV1126B_TOPCRU_BASE)
+#define RV1126B_CLK_UART_FRAC1_DIV_H (0xcd0 + RV1126B_TOPCRU_BASE)
+#define RV1126B_CLK_AUDIO_FRAC0_DIV_H (0xcd4 + RV1126B_TOPCRU_BASE)
+#define RV1126B_CLK_AUDIO_FRAC1_DIV_H (0xcd8 + RV1126B_TOPCRU_BASE)
+#define RV1126B_BUSCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_BUSCRU_BASE)
+#define RV1126B_BUSCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_BUSCRU_BASE)
+#define RV1126B_BUSSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_BUSCRU_BASE)
+#define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE)
+#define RV1126B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PERICRU_BASE)
+#define RV1126B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PERICRU_BASE)
+#define RV1126B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PERICRU_BASE)
+#define RV1126B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_CORECRU_BASE)
+#define RV1126B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_CORECRU_BASE)
+#define RV1126B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_CORECRU_BASE)
+#define RV1126B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMUCRU_BASE)
+#define RV1126B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMUCRU_BASE)
+#define RV1126B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMUCRU_BASE)
+#define RV1126B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMU1CRU_BASE)
+#define RV1126B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMU1CRU_BASE)
+#define RV1126B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMU1CRU_BASE)
+#define RV1126B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_DDRCRU_BASE)
+#define RV1126B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_DDRCRU_BASE)
+#define RV1126B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_DDRCRU_BASE)
+#define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE)
+#define RV1126B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_SUBDDRCRU_BASE)
+#define RV1126B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_SUBDDRCRU_BASE)
+#define RV1126B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_SUBDDRCRU_BASE)
+#define RV1126B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VICRU_BASE)
+#define RV1126B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VICRU_BASE)
+#define RV1126B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VICRU_BASE)
+#define RV1126B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VEPUCRU_BASE)
+#define RV1126B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VEPUCRU_BASE)
+#define RV1126B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VEPUCRU_BASE)
+#define RV1126B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_NPUCRU_BASE)
+#define RV1126B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_NPUCRU_BASE)
+#define RV1126B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_NPUCRU_BASE)
+#define RV1126B_VDOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VDOCRU_BASE)
+#define RV1126B_VDOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VDOCRU_BASE)
+#define RV1126B_VDOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VDOCRU_BASE)
+#define RV1126B_VCPCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VCPCRU_BASE)
+#define RV1126B_VCPCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VCPCRU_BASE)
+#define RV1126B_VCPSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VCPCRU_BASE)
+
#define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
@@ -208,6 +275,18 @@ struct clk;
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
+#define RK3506_PMU_CRU_BASE 0x10000
+#define RK3506_PLL_CON(x) ((x) * 0x4 + RK3506_PMU_CRU_BASE)
+#define RK3506_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3506_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
+#define RK3506_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
+#define RK3506_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3506_PMU_CRU_BASE)
+#define RK3506_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3506_PMU_CRU_BASE)
+#define RK3506_MODE_CON 0x280
+#define RK3506_GLB_CNT_TH 0xc00
+#define RK3506_GLB_SRST_FST 0xc08
+#define RK3506_GLB_SRST_SND 0xc0c
+
#define RK3528_PMU_CRU_BASE 0x10000
#define RK3528_PCIE_CRU_BASE 0x20000
#define RK3528_DDRPHY_CRU_BASE 0x28000
@@ -622,6 +701,17 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
const struct rockchip_cpuclk_rate_table *rates,
int nrates, void __iomem *reg_base, spinlock_t *lock);
+struct clk *rockchip_clk_register_cpuclk_multi_pll(const char *name,
+ const char *const *parent_names,
+ u8 num_parents, void __iomem *base,
+ int muxdiv_offset, u8 mux_shift,
+ u8 mux_width, u8 mux_flags,
+ int div_offset, u8 div_shift,
+ u8 div_width, u8 div_flags,
+ unsigned long flags, spinlock_t *lock,
+ const struct rockchip_cpuclk_rate_table *rates,
+ int nrates);
+
struct clk *rockchip_clk_register_mmc(const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *reg,
@@ -1208,6 +1298,10 @@ void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
const struct rockchip_cpuclk_reg_data *reg_data,
const struct rockchip_cpuclk_rate_table *rates,
int nrates);
+void rockchip_clk_register_armclk_multi_pll(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ const struct rockchip_cpuclk_rate_table *rates,
+ int nrates);
void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
unsigned int reg, void (*cb)(void));
@@ -1246,6 +1340,8 @@ static inline void rockchip_register_softrst(struct device_node *np,
return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
}
+void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base);
+void rk3506_rst_init(struct device_node *np, void __iomem *reg_base);
void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
void rk3562_rst_init(struct device_node *np, void __iomem *reg_base);
void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
diff --git a/drivers/clk/rockchip/rst-rk3506.c b/drivers/clk/rockchip/rst-rk3506.c
new file mode 100644
index 000000000000..c3abde60f3c6
--- /dev/null
+++ b/drivers/clk/rockchip/rst-rk3506.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <dt-bindings/reset/rockchip,rk3506-cru.h>
+#include "clk.h"
+
+/* 0xFF9A0000 + 0x0A00 */
+#define RK3506_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
+
+/* mapping table for reset ID to register offset */
+static const int rk3506_register_offset[] = {
+ /* CRU-->SOFTRST_CON00 */
+ RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET0_AC, 0, 0),
+ RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET1_AC, 0, 1),
+ RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET2_AC, 0, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_NCORESET0_AC, 0, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_NCORESET1_AC, 0, 5),
+ RK3506_CRU_RESET_OFFSET(SRST_NCORESET2_AC, 0, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_NL2RESET_AC, 0, 8),
+ RK3506_CRU_RESET_OFFSET(SRST_A_CORE_BIU_AC, 0, 9),
+ RK3506_CRU_RESET_OFFSET(SRST_H_M0_AC, 0, 10),
+
+ /* CRU-->SOFTRST_CON02 */
+ RK3506_CRU_RESET_OFFSET(SRST_NDBGRESET, 2, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 2, 14),
+ RK3506_CRU_RESET_OFFSET(SRST_PMU, 2, 15),
+
+ /* CRU-->SOFTRST_CON03 */
+ RK3506_CRU_RESET_OFFSET(SRST_P_DBG, 3, 1),
+ RK3506_CRU_RESET_OFFSET(SRST_POT_DBG, 3, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 3, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_CORE_EMA_DETECT, 3, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1, 3, 8),
+ RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO1, 3, 9),
+
+ /* CRU-->SOFTRST_CON04 */
+ RK3506_CRU_RESET_OFFSET(SRST_A_CORE_PERI_BIU, 4, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_A_DSMC, 4, 5),
+ RK3506_CRU_RESET_OFFSET(SRST_P_DSMC, 4, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_A_FLEXBUS, 4, 9),
+ RK3506_CRU_RESET_OFFSET(SRST_H_FLEXBUS, 4, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11),
+ RK3506_CRU_RESET_OFFSET(SRST_H_DSMC_SLV, 4, 12),
+ RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13),
+
+ /* CRU-->SOFTRST_CON05 */
+ RK3506_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 5, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 5, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 5, 5),
+ RK3506_CRU_RESET_OFFSET(SRST_A_SYSRAM, 5, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_A_DMAC0, 5, 8),
+ RK3506_CRU_RESET_OFFSET(SRST_A_DMAC1, 5, 9),
+ RK3506_CRU_RESET_OFFSET(SRST_H_M0, 5, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11),
+ RK3506_CRU_RESET_OFFSET(SRST_H_CRYPTO, 5, 15),
+
+ /* CRU-->SOFTRST_CON06 */
+ RK3506_CRU_RESET_OFFSET(SRST_H_RNG, 6, 0),
+ RK3506_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 6, 1),
+ RK3506_CRU_RESET_OFFSET(SRST_P_TIMER0, 6, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH0, 6, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH1, 6, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH2, 6, 5),
+ RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH3, 6, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH5, 6, 8),
+ RK3506_CRU_RESET_OFFSET(SRST_P_WDT0, 6, 9),
+ RK3506_CRU_RESET_OFFSET(SRST_T_WDT0, 6, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11),
+ RK3506_CRU_RESET_OFFSET(SRST_T_WDT1, 6, 12),
+ RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13),
+ RK3506_CRU_RESET_OFFSET(SRST_P_INTMUX, 6, 14),
+ RK3506_CRU_RESET_OFFSET(SRST_P_SPINLOCK, 6, 15),
+
+ /* CRU-->SOFTRST_CON07 */
+ RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0),
+ RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1),
+ RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5),
+ RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8),
+ RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11),
+ RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12),
+ RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13),
+ RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14),
+
+ /* CRU-->SOFTRST_CON08 */
+ RK3506_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 8, 0),
+ RK3506_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 8, 1),
+
+ /* CRU-->SOFTRST_CON09 */
+ RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_UTMI, 9, 0),
+ RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_UTMI, 9, 1),
+
+ /* CRU-->SOFTRST_CON10 */
+ RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_0, 10, 0),
+ RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_1, 10, 1),
+ RK3506_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 10, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_DDRC, 10, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_DDRMON, 10, 4),
+
+ /* CRU-->SOFTRST_CON11 */
+ RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5),
+ RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8),
+ RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9),
+ RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11),
+ RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12),
+ RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13),
+ RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14),
+ RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15),
+
+ /* CRU-->SOFTRST_CON12 */
+ RK3506_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
+ RK3506_CRU_RESET_OFFSET(SRST_I2C1, 12, 1),
+ RK3506_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_I2C2, 12, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_P_PWM1, 12, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_PWM1, 12, 5),
+ RK3506_CRU_RESET_OFFSET(SRST_P_SPI0, 12, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11),
+ RK3506_CRU_RESET_OFFSET(SRST_P_SPI1, 12, 12),
+ RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13),
+ RK3506_CRU_RESET_OFFSET(SRST_P_GPIO2, 12, 14),
+ RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO2, 12, 15),
+
+ /* CRU-->SOFTRST_CON13 */
+ RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0),
+ RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1),
+ RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_CAN0, 13, 5),
+ RK3506_CRU_RESET_OFFSET(SRST_H_CAN1, 13, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_H_PDM, 13, 8),
+ RK3506_CRU_RESET_OFFSET(SRST_M_PDM, 13, 9),
+ RK3506_CRU_RESET_OFFSET(SRST_PDM, 13, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11),
+ RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFTX, 13, 12),
+ RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFRX, 13, 13),
+ RK3506_CRU_RESET_OFFSET(SRST_SPDIFRX, 13, 14),
+ RK3506_CRU_RESET_OFFSET(SRST_M_SAI0, 13, 15),
+
+ /* CRU-->SOFTRST_CON14 */
+ RK3506_CRU_RESET_OFFSET(SRST_H_SAI0, 14, 0),
+ RK3506_CRU_RESET_OFFSET(SRST_M_SAI1, 14, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_H_SAI1, 14, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_H_ASRC0, 14, 5),
+ RK3506_CRU_RESET_OFFSET(SRST_ASRC0, 14, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_ASRC1, 14, 8),
+
+ /* CRU-->SOFTRST_CON17 */
+ RK3506_CRU_RESET_OFFSET(SRST_H_HSPERI_BIU, 17, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_H_FSPI, 17, 8),
+ RK3506_CRU_RESET_OFFSET(SRST_S_FSPI, 17, 9),
+ RK3506_CRU_RESET_OFFSET(SRST_P_SPI2, 17, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11),
+ RK3506_CRU_RESET_OFFSET(SRST_A_MAC1, 17, 12),
+
+ /* CRU-->SOFTRST_CON18 */
+ RK3506_CRU_RESET_OFFSET(SRST_M_SAI2, 18, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_H_SAI2, 18, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_H_SAI3, 18, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_H_SAI4, 18, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11),
+ RK3506_CRU_RESET_OFFSET(SRST_H_DSM, 18, 12),
+ RK3506_CRU_RESET_OFFSET(SRST_M_DSM, 18, 13),
+ RK3506_CRU_RESET_OFFSET(SRST_P_AUDIO_ADC, 18, 14),
+ RK3506_CRU_RESET_OFFSET(SRST_M_AUDIO_ADC, 18, 15),
+
+ /* CRU-->SOFTRST_CON19 */
+ RK3506_CRU_RESET_OFFSET(SRST_P_SARADC, 19, 0),
+ RK3506_CRU_RESET_OFFSET(SRST_SARADC, 19, 1),
+ RK3506_CRU_RESET_OFFSET(SRST_SARADC_PHY, 19, 2),
+ RK3506_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 19, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 19, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 19, 5),
+ RK3506_CRU_RESET_OFFSET(SRST_P_UART5, 19, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_P_GPIO234_IOC, 19, 8),
+
+ /* CRU-->SOFTRST_CON21 */
+ RK3506_CRU_RESET_OFFSET(SRST_A_VIO_BIU, 21, 3),
+ RK3506_CRU_RESET_OFFSET(SRST_H_VIO_BIU, 21, 4),
+ RK3506_CRU_RESET_OFFSET(SRST_H_RGA, 21, 6),
+ RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7),
+ RK3506_CRU_RESET_OFFSET(SRST_CORE_RGA, 21, 8),
+ RK3506_CRU_RESET_OFFSET(SRST_A_VOP, 21, 9),
+ RK3506_CRU_RESET_OFFSET(SRST_H_VOP, 21, 10),
+ RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11),
+ RK3506_CRU_RESET_OFFSET(SRST_P_DPHY, 21, 12),
+ RK3506_CRU_RESET_OFFSET(SRST_P_DSI_HOST, 21, 13),
+ RK3506_CRU_RESET_OFFSET(SRST_P_TSADC, 21, 14),
+ RK3506_CRU_RESET_OFFSET(SRST_TSADC, 21, 15),
+
+ /* CRU-->SOFTRST_CON22 */
+ RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1_IOC, 22, 1),
+};
+
+void rk3506_rst_init(struct device_node *np, void __iomem *reg_base)
+{
+ rockchip_register_softrst_lut(np,
+ rk3506_register_offset,
+ ARRAY_SIZE(rk3506_register_offset),
+ reg_base + RK3506_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+}
diff --git a/drivers/clk/rockchip/rst-rv1126b.c b/drivers/clk/rockchip/rst-rv1126b.c
new file mode 100644
index 000000000000..c75b0d885ca2
--- /dev/null
+++ b/drivers/clk/rockchip/rst-rv1126b.c
@@ -0,0 +1,443 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <dt-bindings/reset/rockchip,rv1126b-cru.h>
+#include "clk.h"
+
+/* 0x20000000 + 0x0A00 */
+#define TOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x0 * 4 + reg * 16 + bit)
+/* 0x20010000 + 0x0A00 */
+#define BUSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + reg * 16 + bit)
+/* 0x20020000 + 0x0A00 */
+#define PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + reg * 16 + bit)
+/* 0x20030000 + 0x0A00 */
+#define CORECRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000 * 4 + reg * 16 + bit)
+/* 0x20040000 + 0x0A00 */
+#define PMUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x40000 * 4 + reg * 16 + bit)
+/* 0x20050000 + 0x0A00 */
+#define PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x50000 * 4 + reg * 16 + bit)
+/* 0x20060000 + 0x0A00 */
+#define DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x60000 * 4 + reg * 16 + bit)
+/* 0x20068000 + 0x0A00 */
+#define SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x68000 * 4 + reg * 16 + bit)
+/* 0x20070000 + 0x0A00 */
+#define VICRU_RESET_OFFSET(id, reg, bit) [id] = (0x70000 * 4 + reg * 16 + bit)
+/* 0x20080000 + 0x0A00 */
+#define VEPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x80000 * 4 + reg * 16 + bit)
+/* 0x20090000 + 0x0A00 */
+#define NPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x90000 * 4 + reg * 16 + bit)
+/* 0x200A0000 + 0x0A00 */
+#define VDOCRU_RESET_OFFSET(id, reg, bit) [id] = (0xA0000 * 4 + reg * 16 + bit)
+/* 0x200B0000 + 0x0A00 */
+#define VCPCRU_RESET_OFFSET(id, reg, bit) [id] = (0xB0000 * 4 + reg * 16 + bit)
+
+/* =================mapping table for reset ID to register offset================== */
+static const int rv1126b_register_offset[] = {
+ /* TOPCRU-->SOFTRST_CON00 */
+
+ /* TOPCRU-->SOFTRST_CON15 */
+ TOPCRU_RESET_OFFSET(SRST_P_CRU, 15, 1),
+ TOPCRU_RESET_OFFSET(SRST_P_CRU_BIU, 15, 2),
+
+ /* BUSCRU-->SOFTRST_CON00 */
+ BUSCRU_RESET_OFFSET(SRST_A_TOP_BIU, 0, 0),
+ BUSCRU_RESET_OFFSET(SRST_A_RKCE_BIU, 0, 1),
+ BUSCRU_RESET_OFFSET(SRST_A_BUS_BIU, 0, 2),
+ BUSCRU_RESET_OFFSET(SRST_H_BUS_BIU, 0, 3),
+ BUSCRU_RESET_OFFSET(SRST_P_BUS_BIU, 0, 4),
+ BUSCRU_RESET_OFFSET(SRST_P_CRU_BUS, 0, 5),
+ BUSCRU_RESET_OFFSET(SRST_P_SYS_GRF, 0, 6),
+ BUSCRU_RESET_OFFSET(SRST_H_BOOTROM, 0, 7),
+ BUSCRU_RESET_OFFSET(SRST_A_GIC400, 0, 8),
+ BUSCRU_RESET_OFFSET(SRST_A_SPINLOCK, 0, 9),
+ BUSCRU_RESET_OFFSET(SRST_P_WDT_NS, 0, 10),
+ BUSCRU_RESET_OFFSET(SRST_T_WDT_NS, 0, 11),
+
+ /* BUSCRU-->SOFTRST_CON01 */
+ BUSCRU_RESET_OFFSET(SRST_P_WDT_HPMCU, 1, 0),
+ BUSCRU_RESET_OFFSET(SRST_T_WDT_HPMCU, 1, 1),
+ BUSCRU_RESET_OFFSET(SRST_H_CACHE, 1, 2),
+ BUSCRU_RESET_OFFSET(SRST_P_HPMCU_MAILBOX, 1, 3),
+ BUSCRU_RESET_OFFSET(SRST_P_HPMCU_INTMUX, 1, 4),
+ BUSCRU_RESET_OFFSET(SRST_HPMCU_FULL_CLUSTER, 1, 5),
+ BUSCRU_RESET_OFFSET(SRST_HPMCU_PWUP, 1, 6),
+ BUSCRU_RESET_OFFSET(SRST_HPMCU_ONLY_CORE, 1, 7),
+ BUSCRU_RESET_OFFSET(SRST_T_HPMCU_JTAG, 1, 8),
+ BUSCRU_RESET_OFFSET(SRST_P_RKDMA, 1, 11),
+ BUSCRU_RESET_OFFSET(SRST_A_RKDMA, 1, 12),
+
+ /* BUSCRU-->SOFTRST_CON02 */
+ BUSCRU_RESET_OFFSET(SRST_P_DCF, 2, 0),
+ BUSCRU_RESET_OFFSET(SRST_A_DCF, 2, 1),
+ BUSCRU_RESET_OFFSET(SRST_H_RGA, 2, 2),
+ BUSCRU_RESET_OFFSET(SRST_A_RGA, 2, 3),
+ BUSCRU_RESET_OFFSET(SRST_CORE_RGA, 2, 4),
+ BUSCRU_RESET_OFFSET(SRST_P_TIMER, 2, 5),
+ BUSCRU_RESET_OFFSET(SRST_TIMER0, 2, 6),
+ BUSCRU_RESET_OFFSET(SRST_TIMER1, 2, 7),
+ BUSCRU_RESET_OFFSET(SRST_TIMER2, 2, 8),
+ BUSCRU_RESET_OFFSET(SRST_TIMER3, 2, 9),
+ BUSCRU_RESET_OFFSET(SRST_TIMER4, 2, 10),
+ BUSCRU_RESET_OFFSET(SRST_TIMER5, 2, 11),
+ BUSCRU_RESET_OFFSET(SRST_A_RKCE, 2, 12),
+ BUSCRU_RESET_OFFSET(SRST_PKA_RKCE, 2, 13),
+ BUSCRU_RESET_OFFSET(SRST_H_RKRNG_S, 2, 14),
+ BUSCRU_RESET_OFFSET(SRST_H_RKRNG_NS, 2, 15),
+
+ /* BUSCRU-->SOFTRST_CON03 */
+ BUSCRU_RESET_OFFSET(SRST_P_I2C0, 3, 0),
+ BUSCRU_RESET_OFFSET(SRST_I2C0, 3, 1),
+ BUSCRU_RESET_OFFSET(SRST_P_I2C1, 3, 2),
+ BUSCRU_RESET_OFFSET(SRST_I2C1, 3, 3),
+ BUSCRU_RESET_OFFSET(SRST_P_I2C3, 3, 4),
+ BUSCRU_RESET_OFFSET(SRST_I2C3, 3, 5),
+ BUSCRU_RESET_OFFSET(SRST_P_I2C4, 3, 6),
+ BUSCRU_RESET_OFFSET(SRST_I2C4, 3, 7),
+ BUSCRU_RESET_OFFSET(SRST_P_I2C5, 3, 8),
+ BUSCRU_RESET_OFFSET(SRST_I2C5, 3, 9),
+ BUSCRU_RESET_OFFSET(SRST_P_SPI0, 3, 10),
+ BUSCRU_RESET_OFFSET(SRST_SPI0, 3, 11),
+ BUSCRU_RESET_OFFSET(SRST_P_SPI1, 3, 12),
+ BUSCRU_RESET_OFFSET(SRST_SPI1, 3, 13),
+
+ /* BUSCRU-->SOFTRST_CON04 */
+ BUSCRU_RESET_OFFSET(SRST_P_PWM0, 4, 0),
+ BUSCRU_RESET_OFFSET(SRST_PWM0, 4, 1),
+ BUSCRU_RESET_OFFSET(SRST_P_PWM2, 4, 4),
+ BUSCRU_RESET_OFFSET(SRST_PWM2, 4, 5),
+ BUSCRU_RESET_OFFSET(SRST_P_PWM3, 4, 8),
+ BUSCRU_RESET_OFFSET(SRST_PWM3, 4, 9),
+
+ /* BUSCRU-->SOFTRST_CON05 */
+ BUSCRU_RESET_OFFSET(SRST_P_UART1, 5, 0),
+ BUSCRU_RESET_OFFSET(SRST_S_UART1, 5, 1),
+ BUSCRU_RESET_OFFSET(SRST_P_UART2, 5, 2),
+ BUSCRU_RESET_OFFSET(SRST_S_UART2, 5, 3),
+ BUSCRU_RESET_OFFSET(SRST_P_UART3, 5, 4),
+ BUSCRU_RESET_OFFSET(SRST_S_UART3, 5, 5),
+ BUSCRU_RESET_OFFSET(SRST_P_UART4, 5, 6),
+ BUSCRU_RESET_OFFSET(SRST_S_UART4, 5, 7),
+ BUSCRU_RESET_OFFSET(SRST_P_UART5, 5, 8),
+ BUSCRU_RESET_OFFSET(SRST_S_UART5, 5, 9),
+ BUSCRU_RESET_OFFSET(SRST_P_UART6, 5, 10),
+ BUSCRU_RESET_OFFSET(SRST_S_UART6, 5, 11),
+ BUSCRU_RESET_OFFSET(SRST_P_UART7, 5, 12),
+ BUSCRU_RESET_OFFSET(SRST_S_UART7, 5, 13),
+
+ /* BUSCRU-->SOFTRST_CON06 */
+ BUSCRU_RESET_OFFSET(SRST_P_TSADC, 6, 0),
+ BUSCRU_RESET_OFFSET(SRST_TSADC, 6, 1),
+ BUSCRU_RESET_OFFSET(SRST_H_SAI0, 6, 2),
+ BUSCRU_RESET_OFFSET(SRST_M_SAI0, 6, 3),
+ BUSCRU_RESET_OFFSET(SRST_H_SAI1, 6, 4),
+ BUSCRU_RESET_OFFSET(SRST_M_SAI1, 6, 5),
+ BUSCRU_RESET_OFFSET(SRST_H_SAI2, 6, 6),
+ BUSCRU_RESET_OFFSET(SRST_M_SAI2, 6, 7),
+ BUSCRU_RESET_OFFSET(SRST_H_RKDSM, 6, 8),
+ BUSCRU_RESET_OFFSET(SRST_M_RKDSM, 6, 9),
+ BUSCRU_RESET_OFFSET(SRST_H_PDM, 6, 10),
+ BUSCRU_RESET_OFFSET(SRST_M_PDM, 6, 11),
+ BUSCRU_RESET_OFFSET(SRST_PDM, 6, 12),
+
+ /* BUSCRU-->SOFTRST_CON07 */
+ BUSCRU_RESET_OFFSET(SRST_H_ASRC0, 7, 0),
+ BUSCRU_RESET_OFFSET(SRST_ASRC0, 7, 1),
+ BUSCRU_RESET_OFFSET(SRST_H_ASRC1, 7, 2),
+ BUSCRU_RESET_OFFSET(SRST_ASRC1, 7, 3),
+ BUSCRU_RESET_OFFSET(SRST_P_AUDIO_ADC_BUS, 7, 4),
+ BUSCRU_RESET_OFFSET(SRST_M_AUDIO_ADC_BUS, 7, 5),
+ BUSCRU_RESET_OFFSET(SRST_P_RKCE, 7, 6),
+ BUSCRU_RESET_OFFSET(SRST_H_NS_RKCE, 7, 7),
+ BUSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 7, 8),
+ BUSCRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 7, 9),
+ BUSCRU_RESET_OFFSET(SRST_USER_OTPC_NS, 7, 10),
+ BUSCRU_RESET_OFFSET(SRST_OTPC_ARB, 7, 11),
+ BUSCRU_RESET_OFFSET(SRST_P_OTP_MASK, 7, 12),
+
+ /* PERICRU-->SOFTRST_CON00 */
+ PERICRU_RESET_OFFSET(SRST_A_PERI_BIU, 0, 0),
+ PERICRU_RESET_OFFSET(SRST_P_PERI_BIU, 0, 1),
+ PERICRU_RESET_OFFSET(SRST_P_RTC_BIU, 0, 2),
+ PERICRU_RESET_OFFSET(SRST_P_CRU_PERI, 0, 3),
+ PERICRU_RESET_OFFSET(SRST_P_PERI_GRF, 0, 4),
+ PERICRU_RESET_OFFSET(SRST_P_GPIO1, 0, 5),
+ PERICRU_RESET_OFFSET(SRST_DB_GPIO1, 0, 6),
+ PERICRU_RESET_OFFSET(SRST_P_IOC_VCCIO1, 0, 7),
+ PERICRU_RESET_OFFSET(SRST_A_USB3OTG, 0, 8),
+ PERICRU_RESET_OFFSET(SRST_H_USB2HOST, 0, 11),
+ PERICRU_RESET_OFFSET(SRST_H_ARB_USB2HOST, 0, 12),
+ PERICRU_RESET_OFFSET(SRST_P_RTC_TEST, 0, 13),
+
+ /* PERICRU-->SOFTRST_CON01 */
+ PERICRU_RESET_OFFSET(SRST_H_EMMC, 1, 0),
+ PERICRU_RESET_OFFSET(SRST_H_FSPI0, 1, 1),
+ PERICRU_RESET_OFFSET(SRST_H_XIP_FSPI0, 1, 2),
+ PERICRU_RESET_OFFSET(SRST_S_2X_FSPI0, 1, 3),
+ PERICRU_RESET_OFFSET(SRST_UTMI_USB2HOST, 1, 5),
+ PERICRU_RESET_OFFSET(SRST_REF_PIPEPHY, 1, 7),
+ PERICRU_RESET_OFFSET(SRST_P_PIPEPHY, 1, 8),
+ PERICRU_RESET_OFFSET(SRST_P_PIPEPHY_GRF, 1, 9),
+ PERICRU_RESET_OFFSET(SRST_P_USB2PHY, 1, 10),
+ PERICRU_RESET_OFFSET(SRST_POR_USB2PHY, 1, 11),
+ PERICRU_RESET_OFFSET(SRST_OTG_USB2PHY, 1, 12),
+ PERICRU_RESET_OFFSET(SRST_HOST_USB2PHY, 1, 13),
+
+ /* CORECRU-->SOFTRST_CON00 */
+ CORECRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 0, 0),
+ CORECRU_RESET_OFFSET(SRST_NCOREPORESET0, 0, 1),
+ CORECRU_RESET_OFFSET(SRST_NCORESET0, 0, 2),
+ CORECRU_RESET_OFFSET(SRST_NCOREPORESET1, 0, 3),
+ CORECRU_RESET_OFFSET(SRST_NCORESET1, 0, 4),
+ CORECRU_RESET_OFFSET(SRST_NCOREPORESET2, 0, 5),
+ CORECRU_RESET_OFFSET(SRST_NCORESET2, 0, 6),
+ CORECRU_RESET_OFFSET(SRST_NCOREPORESET3, 0, 7),
+ CORECRU_RESET_OFFSET(SRST_NCORESET3, 0, 8),
+ CORECRU_RESET_OFFSET(SRST_NDBGRESET, 0, 9),
+ CORECRU_RESET_OFFSET(SRST_NL2RESET, 0, 10),
+
+ /* CORECRU-->SOFTRST_CON01 */
+ CORECRU_RESET_OFFSET(SRST_A_CORE_BIU, 1, 0),
+ CORECRU_RESET_OFFSET(SRST_P_CORE_BIU, 1, 1),
+ CORECRU_RESET_OFFSET(SRST_H_CORE_BIU, 1, 2),
+ CORECRU_RESET_OFFSET(SRST_P_DBG, 1, 3),
+ CORECRU_RESET_OFFSET(SRST_POT_DBG, 1, 4),
+ CORECRU_RESET_OFFSET(SRST_NT_DBG, 1, 5),
+ CORECRU_RESET_OFFSET(SRST_P_CORE_PVTPLL, 1, 6),
+ CORECRU_RESET_OFFSET(SRST_P_CRU_CORE, 1, 7),
+ CORECRU_RESET_OFFSET(SRST_P_CORE_GRF, 1, 8),
+ CORECRU_RESET_OFFSET(SRST_P_DFT2APB, 1, 10),
+
+ /* PMUCRU-->SOFTRST_CON00 */
+ PMUCRU_RESET_OFFSET(SRST_H_PMU_BIU, 0, 0),
+ PMUCRU_RESET_OFFSET(SRST_P_PMU_GPIO0, 0, 7),
+ PMUCRU_RESET_OFFSET(SRST_DB_PMU_GPIO0, 0, 8),
+ PMUCRU_RESET_OFFSET(SRST_P_PMU_HP_TIMER, 0, 10),
+ PMUCRU_RESET_OFFSET(SRST_PMU_HP_TIMER, 0, 11),
+ PMUCRU_RESET_OFFSET(SRST_PMU_32K_HP_TIMER, 0, 12),
+
+ /* PMUCRU-->SOFTRST_CON01 */
+ PMUCRU_RESET_OFFSET(SRST_P_PWM1, 1, 0),
+ PMUCRU_RESET_OFFSET(SRST_PWM1, 1, 1),
+ PMUCRU_RESET_OFFSET(SRST_P_I2C2, 1, 2),
+ PMUCRU_RESET_OFFSET(SRST_I2C2, 1, 3),
+ PMUCRU_RESET_OFFSET(SRST_P_UART0, 1, 4),
+ PMUCRU_RESET_OFFSET(SRST_S_UART0, 1, 5),
+
+ /* PMUCRU-->SOFTRST_CON02 */
+ PMUCRU_RESET_OFFSET(SRST_P_RCOSC_CTRL, 2, 0),
+ PMUCRU_RESET_OFFSET(SRST_REF_RCOSC_CTRL, 2, 2),
+ PMUCRU_RESET_OFFSET(SRST_P_IOC_PMUIO0, 2, 3),
+ PMUCRU_RESET_OFFSET(SRST_P_CRU_PMU, 2, 4),
+ PMUCRU_RESET_OFFSET(SRST_P_PMU_GRF, 2, 5),
+ PMUCRU_RESET_OFFSET(SRST_PREROLL, 2, 7),
+ PMUCRU_RESET_OFFSET(SRST_PREROLL_32K, 2, 8),
+ PMUCRU_RESET_OFFSET(SRST_H_PMU_SRAM, 2, 9),
+
+ /* PMUCRU-->SOFTRST_CON03 */
+ PMUCRU_RESET_OFFSET(SRST_P_WDT_LPMCU, 3, 0),
+ PMUCRU_RESET_OFFSET(SRST_T_WDT_LPMCU, 3, 1),
+ PMUCRU_RESET_OFFSET(SRST_LPMCU_FULL_CLUSTER, 3, 2),
+ PMUCRU_RESET_OFFSET(SRST_LPMCU_PWUP, 3, 3),
+ PMUCRU_RESET_OFFSET(SRST_LPMCU_ONLY_CORE, 3, 4),
+ PMUCRU_RESET_OFFSET(SRST_T_LPMCU_JTAG, 3, 5),
+ PMUCRU_RESET_OFFSET(SRST_P_LPMCU_MAILBOX, 3, 6),
+
+ /* PMU1CRU-->SOFTRST_CON00 */
+ PMU1CRU_RESET_OFFSET(SRST_P_SPI2AHB, 0, 0),
+ PMU1CRU_RESET_OFFSET(SRST_H_SPI2AHB, 0, 1),
+ PMU1CRU_RESET_OFFSET(SRST_H_FSPI1, 0, 2),
+ PMU1CRU_RESET_OFFSET(SRST_H_XIP_FSPI1, 0, 3),
+ PMU1CRU_RESET_OFFSET(SRST_S_1X_FSPI1, 0, 4),
+ PMU1CRU_RESET_OFFSET(SRST_P_IOC_PMUIO1, 0, 5),
+ PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 0, 6),
+ PMU1CRU_RESET_OFFSET(SRST_P_AUDIO_ADC_PMU, 0, 7),
+ PMU1CRU_RESET_OFFSET(SRST_M_AUDIO_ADC_PMU, 0, 8),
+ PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 9),
+
+ /* PMU1CRU-->SOFTRST_CON01 */
+ PMU1CRU_RESET_OFFSET(SRST_P_LPDMA, 1, 0),
+ PMU1CRU_RESET_OFFSET(SRST_A_LPDMA, 1, 1),
+ PMU1CRU_RESET_OFFSET(SRST_H_LPSAI, 1, 2),
+ PMU1CRU_RESET_OFFSET(SRST_M_LPSAI, 1, 3),
+ PMU1CRU_RESET_OFFSET(SRST_P_AOA_TDD, 1, 4),
+ PMU1CRU_RESET_OFFSET(SRST_P_AOA_FE, 1, 5),
+ PMU1CRU_RESET_OFFSET(SRST_P_AOA_AAD, 1, 6),
+ PMU1CRU_RESET_OFFSET(SRST_P_AOA_APB, 1, 7),
+ PMU1CRU_RESET_OFFSET(SRST_P_AOA_SRAM, 1, 8),
+
+ /* DDRCRU-->SOFTRST_CON00 */
+ DDRCRU_RESET_OFFSET(SRST_P_DDR_BIU, 0, 1),
+ DDRCRU_RESET_OFFSET(SRST_P_DDRC, 0, 2),
+ DDRCRU_RESET_OFFSET(SRST_P_DDRMON, 0, 3),
+ DDRCRU_RESET_OFFSET(SRST_TIMER_DDRMON, 0, 4),
+ DDRCRU_RESET_OFFSET(SRST_P_DFICTRL, 0, 5),
+ DDRCRU_RESET_OFFSET(SRST_P_DDR_GRF, 0, 6),
+ DDRCRU_RESET_OFFSET(SRST_P_CRU_DDR, 0, 7),
+ DDRCRU_RESET_OFFSET(SRST_P_DDRPHY, 0, 8),
+ DDRCRU_RESET_OFFSET(SRST_P_DMA2DDR, 0, 9),
+
+ /* SUBDDRCRU-->SOFTRST_CON00 */
+ SUBDDRCRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 0, 0),
+ SUBDDRCRU_RESET_OFFSET(SRST_A_SYSMEM, 0, 1),
+ SUBDDRCRU_RESET_OFFSET(SRST_A_DDR_BIU, 0, 2),
+ SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH0_CPU, 0, 3),
+ SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH1_NPU, 0, 4),
+ SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH2_POE, 0, 5),
+ SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH3_VI, 0, 6),
+ SUBDDRCRU_RESET_OFFSET(SRST_CORE_DDRC, 0, 7),
+ SUBDDRCRU_RESET_OFFSET(SRST_DDRMON, 0, 8),
+ SUBDDRCRU_RESET_OFFSET(SRST_DFICTRL, 0, 9),
+ SUBDDRCRU_RESET_OFFSET(SRST_RS, 0, 11),
+ SUBDDRCRU_RESET_OFFSET(SRST_A_DMA2DDR, 0, 12),
+ SUBDDRCRU_RESET_OFFSET(SRST_DDRPHY, 0, 13),
+
+ /* VICRU-->SOFTRST_CON00 */
+ VICRU_RESET_OFFSET(SRST_REF_PVTPLL_ISP, 0, 0),
+ VICRU_RESET_OFFSET(SRST_A_GMAC_BIU, 0, 1),
+ VICRU_RESET_OFFSET(SRST_A_VI_BIU, 0, 2),
+ VICRU_RESET_OFFSET(SRST_H_VI_BIU, 0, 3),
+ VICRU_RESET_OFFSET(SRST_P_VI_BIU, 0, 4),
+ VICRU_RESET_OFFSET(SRST_P_CRU_VI, 0, 5),
+ VICRU_RESET_OFFSET(SRST_P_VI_GRF, 0, 6),
+ VICRU_RESET_OFFSET(SRST_P_VI_PVTPLL, 0, 7),
+ VICRU_RESET_OFFSET(SRST_P_DSMC, 0, 8),
+ VICRU_RESET_OFFSET(SRST_A_DSMC, 0, 9),
+ VICRU_RESET_OFFSET(SRST_H_CAN0, 0, 10),
+ VICRU_RESET_OFFSET(SRST_CAN0, 0, 11),
+ VICRU_RESET_OFFSET(SRST_H_CAN1, 0, 12),
+ VICRU_RESET_OFFSET(SRST_CAN1, 0, 13),
+
+ /* VICRU-->SOFTRST_CON01 */
+ VICRU_RESET_OFFSET(SRST_P_GPIO2, 1, 0),
+ VICRU_RESET_OFFSET(SRST_DB_GPIO2, 1, 1),
+ VICRU_RESET_OFFSET(SRST_P_GPIO4, 1, 2),
+ VICRU_RESET_OFFSET(SRST_DB_GPIO4, 1, 3),
+ VICRU_RESET_OFFSET(SRST_P_GPIO5, 1, 4),
+ VICRU_RESET_OFFSET(SRST_DB_GPIO5, 1, 5),
+ VICRU_RESET_OFFSET(SRST_P_GPIO6, 1, 6),
+ VICRU_RESET_OFFSET(SRST_DB_GPIO6, 1, 7),
+ VICRU_RESET_OFFSET(SRST_P_GPIO7, 1, 8),
+ VICRU_RESET_OFFSET(SRST_DB_GPIO7, 1, 9),
+ VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO2, 1, 10),
+ VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO4, 1, 11),
+ VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO5, 1, 12),
+ VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO6, 1, 13),
+ VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO7, 1, 14),
+
+ /* VICRU-->SOFTRST_CON02 */
+ VICRU_RESET_OFFSET(SRST_CORE_ISP, 2, 0),
+ VICRU_RESET_OFFSET(SRST_H_VICAP, 2, 1),
+ VICRU_RESET_OFFSET(SRST_A_VICAP, 2, 2),
+ VICRU_RESET_OFFSET(SRST_D_VICAP, 2, 3),
+ VICRU_RESET_OFFSET(SRST_ISP0_VICAP, 2, 4),
+ VICRU_RESET_OFFSET(SRST_CORE_VPSS, 2, 5),
+ VICRU_RESET_OFFSET(SRST_CORE_VPSL, 2, 6),
+ VICRU_RESET_OFFSET(SRST_P_CSI2HOST0, 2, 7),
+ VICRU_RESET_OFFSET(SRST_P_CSI2HOST1, 2, 8),
+ VICRU_RESET_OFFSET(SRST_P_CSI2HOST2, 2, 9),
+ VICRU_RESET_OFFSET(SRST_P_CSI2HOST3, 2, 10),
+ VICRU_RESET_OFFSET(SRST_H_SDMMC0, 2, 11),
+ VICRU_RESET_OFFSET(SRST_A_GMAC, 2, 12),
+ VICRU_RESET_OFFSET(SRST_P_CSIPHY0, 2, 13),
+ VICRU_RESET_OFFSET(SRST_P_CSIPHY1, 2, 14),
+
+ /* VICRU-->SOFTRST_CON03 */
+ VICRU_RESET_OFFSET(SRST_P_MACPHY, 3, 0),
+ VICRU_RESET_OFFSET(SRST_MACPHY, 3, 1),
+ VICRU_RESET_OFFSET(SRST_P_SARADC1, 3, 2),
+ VICRU_RESET_OFFSET(SRST_SARADC1, 3, 3),
+ VICRU_RESET_OFFSET(SRST_P_SARADC2, 3, 5),
+ VICRU_RESET_OFFSET(SRST_SARADC2, 3, 6),
+
+ /* VEPUCRU-->SOFTRST_CON00 */
+ VEPUCRU_RESET_OFFSET(SRST_REF_PVTPLL_VEPU, 0, 0),
+ VEPUCRU_RESET_OFFSET(SRST_A_VEPU_BIU, 0, 1),
+ VEPUCRU_RESET_OFFSET(SRST_H_VEPU_BIU, 0, 2),
+ VEPUCRU_RESET_OFFSET(SRST_P_VEPU_BIU, 0, 3),
+ VEPUCRU_RESET_OFFSET(SRST_P_CRU_VEPU, 0, 4),
+ VEPUCRU_RESET_OFFSET(SRST_P_VEPU_GRF, 0, 5),
+ VEPUCRU_RESET_OFFSET(SRST_P_GPIO3, 0, 7),
+ VEPUCRU_RESET_OFFSET(SRST_DB_GPIO3, 0, 8),
+ VEPUCRU_RESET_OFFSET(SRST_P_IOC_VCCIO3, 0, 9),
+ VEPUCRU_RESET_OFFSET(SRST_P_SARADC0, 0, 10),
+ VEPUCRU_RESET_OFFSET(SRST_SARADC0, 0, 11),
+ VEPUCRU_RESET_OFFSET(SRST_H_SDMMC1, 0, 13),
+
+ /* VEPUCRU-->SOFTRST_CON01 */
+ VEPUCRU_RESET_OFFSET(SRST_P_VEPU_PVTPLL, 1, 0),
+ VEPUCRU_RESET_OFFSET(SRST_H_VEPU, 1, 1),
+ VEPUCRU_RESET_OFFSET(SRST_A_VEPU, 1, 2),
+ VEPUCRU_RESET_OFFSET(SRST_CORE_VEPU, 1, 3),
+
+ /* NPUCRU-->SOFTRST_CON00 */
+ NPUCRU_RESET_OFFSET(SRST_REF_PVTPLL_NPU, 0, 0),
+ NPUCRU_RESET_OFFSET(SRST_A_NPU_BIU, 0, 2),
+ NPUCRU_RESET_OFFSET(SRST_H_NPU_BIU, 0, 3),
+ NPUCRU_RESET_OFFSET(SRST_P_NPU_BIU, 0, 4),
+ NPUCRU_RESET_OFFSET(SRST_P_CRU_NPU, 0, 5),
+ NPUCRU_RESET_OFFSET(SRST_P_NPU_GRF, 0, 6),
+ NPUCRU_RESET_OFFSET(SRST_P_NPU_PVTPLL, 0, 8),
+ NPUCRU_RESET_OFFSET(SRST_H_RKNN, 0, 9),
+ NPUCRU_RESET_OFFSET(SRST_A_RKNN, 0, 10),
+
+ /* VDOCRU-->SOFTRST_CON00 */
+ VDOCRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 0, 0),
+ VDOCRU_RESET_OFFSET(SRST_A_VDO_BIU, 0, 1),
+ VDOCRU_RESET_OFFSET(SRST_H_VDO_BIU, 0, 3),
+ VDOCRU_RESET_OFFSET(SRST_P_VDO_BIU, 0, 4),
+ VDOCRU_RESET_OFFSET(SRST_P_CRU_VDO, 0, 5),
+ VDOCRU_RESET_OFFSET(SRST_P_VDO_GRF, 0, 6),
+ VDOCRU_RESET_OFFSET(SRST_A_RKVDEC, 0, 7),
+ VDOCRU_RESET_OFFSET(SRST_H_RKVDEC, 0, 8),
+ VDOCRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 0, 9),
+ VDOCRU_RESET_OFFSET(SRST_A_VOP, 0, 10),
+ VDOCRU_RESET_OFFSET(SRST_H_VOP, 0, 11),
+ VDOCRU_RESET_OFFSET(SRST_D_VOP, 0, 12),
+ VDOCRU_RESET_OFFSET(SRST_A_OOC, 0, 13),
+ VDOCRU_RESET_OFFSET(SRST_H_OOC, 0, 14),
+ VDOCRU_RESET_OFFSET(SRST_D_OOC, 0, 15),
+
+ /* VDOCRU-->SOFTRST_CON01 */
+ VDOCRU_RESET_OFFSET(SRST_H_RKJPEG, 1, 3),
+ VDOCRU_RESET_OFFSET(SRST_A_RKJPEG, 1, 4),
+ VDOCRU_RESET_OFFSET(SRST_A_RKMMU_DECOM, 1, 5),
+ VDOCRU_RESET_OFFSET(SRST_H_RKMMU_DECOM, 1, 6),
+ VDOCRU_RESET_OFFSET(SRST_D_DECOM, 1, 8),
+ VDOCRU_RESET_OFFSET(SRST_A_DECOM, 1, 9),
+ VDOCRU_RESET_OFFSET(SRST_P_DECOM, 1, 10),
+ VDOCRU_RESET_OFFSET(SRST_P_MIPI_DSI, 1, 12),
+ VDOCRU_RESET_OFFSET(SRST_P_DSIPHY, 1, 13),
+
+ /* VCPCRU-->SOFTRST_CON00 */
+ VCPCRU_RESET_OFFSET(SRST_REF_PVTPLL_VCP, 0, 0),
+ VCPCRU_RESET_OFFSET(SRST_A_VCP_BIU, 0, 1),
+ VCPCRU_RESET_OFFSET(SRST_H_VCP_BIU, 0, 2),
+ VCPCRU_RESET_OFFSET(SRST_P_VCP_BIU, 0, 3),
+ VCPCRU_RESET_OFFSET(SRST_P_CRU_VCP, 0, 4),
+ VCPCRU_RESET_OFFSET(SRST_P_VCP_GRF, 0, 5),
+ VCPCRU_RESET_OFFSET(SRST_P_VCP_PVTPLL, 0, 7),
+ VCPCRU_RESET_OFFSET(SRST_A_AISP_BIU, 0, 8),
+ VCPCRU_RESET_OFFSET(SRST_H_AISP_BIU, 0, 9),
+ VCPCRU_RESET_OFFSET(SRST_CORE_AISP, 0, 13),
+
+ /* VCPCRU-->SOFTRST_CON01 */
+ VCPCRU_RESET_OFFSET(SRST_H_FEC, 1, 0),
+ VCPCRU_RESET_OFFSET(SRST_A_FEC, 1, 1),
+ VCPCRU_RESET_OFFSET(SRST_CORE_FEC, 1, 2),
+ VCPCRU_RESET_OFFSET(SRST_H_AVSP, 1, 3),
+ VCPCRU_RESET_OFFSET(SRST_A_AVSP, 1, 4),
+};
+
+void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base)
+{
+ rockchip_register_softrst_lut(np,
+ rv1126b_register_offset,
+ ARRAY_SIZE(rv1126b_register_offset),
+ reg_base + RV1126B_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+}
diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h
index 5263085c5b23..1e0aef8a645d 100644
--- a/include/dt-bindings/clock/rk3568-cru.h
+++ b/include/dt-bindings/clock/rk3568-cru.h
@@ -483,7 +483,11 @@
#define PCLK_CORE_PVTM 450
-#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)
+/* scmi-clocks indices */
+
+#define SCMI_CLK_CPU 0
+#define SCMI_CLK_GPU 1
+#define SCMI_CLK_NPU 2
/* pmu soft-reset indices */
/* pmucru_softrst_con0 */
diff --git a/include/dt-bindings/clock/rockchip,rk3506-cru.h b/include/dt-bindings/clock/rockchip,rk3506-cru.h
new file mode 100644
index 000000000000..71d7dda23cc9
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk3506-cru.h
@@ -0,0 +1,285 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
+
+/* cru plls */
+#define PLL_GPLL 0
+#define PLL_V0PLL 1
+#define PLL_V1PLL 2
+
+/* cru-clocks indices */
+#define ARMCLK 3
+#define CLK_DDR 4
+#define XIN24M_GATE 5
+#define CLK_GPLL_GATE 6
+#define CLK_V0PLL_GATE 7
+#define CLK_V1PLL_GATE 8
+#define CLK_GPLL_DIV 9
+#define CLK_GPLL_DIV_100M 10
+#define CLK_V0PLL_DIV 11
+#define CLK_V1PLL_DIV 12
+#define CLK_INT_VOICE_MATRIX0 13
+#define CLK_INT_VOICE_MATRIX1 14
+#define CLK_INT_VOICE_MATRIX2 15
+#define CLK_FRAC_UART_MATRIX0_MUX 16
+#define CLK_FRAC_UART_MATRIX1_MUX 17
+#define CLK_FRAC_VOICE_MATRIX0_MUX 18
+#define CLK_FRAC_VOICE_MATRIX1_MUX 19
+#define CLK_FRAC_COMMON_MATRIX0_MUX 20
+#define CLK_FRAC_COMMON_MATRIX1_MUX 21
+#define CLK_FRAC_COMMON_MATRIX2_MUX 22
+#define CLK_FRAC_UART_MATRIX0 23
+#define CLK_FRAC_UART_MATRIX1 24
+#define CLK_FRAC_VOICE_MATRIX0 25
+#define CLK_FRAC_VOICE_MATRIX1 26
+#define CLK_FRAC_COMMON_MATRIX0 27
+#define CLK_FRAC_COMMON_MATRIX1 28
+#define CLK_FRAC_COMMON_MATRIX2 29
+#define CLK_REF_USBPHY_TOP 30
+#define CLK_REF_DPHY_TOP 31
+#define ACLK_CORE_ROOT 32
+#define PCLK_CORE_ROOT 33
+#define PCLK_DBG 34
+#define PCLK_CORE_GRF 35
+#define PCLK_CORE_CRU 36
+#define CLK_CORE_EMA_DETECT 37
+#define CLK_REF_PVTPLL_CORE 38
+#define PCLK_GPIO1 39
+#define DBCLK_GPIO1 40
+#define ACLK_CORE_PERI_ROOT 41
+#define HCLK_CORE_PERI_ROOT 42
+#define PCLK_CORE_PERI_ROOT 43
+#define CLK_DSMC 44
+#define ACLK_DSMC 45
+#define PCLK_DSMC 46
+#define CLK_FLEXBUS_TX 47
+#define CLK_FLEXBUS_RX 48
+#define ACLK_FLEXBUS 49
+#define HCLK_FLEXBUS 50
+#define ACLK_DSMC_SLV 51
+#define HCLK_DSMC_SLV 52
+#define ACLK_BUS_ROOT 53
+#define HCLK_BUS_ROOT 54
+#define PCLK_BUS_ROOT 55
+#define ACLK_SYSRAM 56
+#define HCLK_SYSRAM 57
+#define ACLK_DMAC0 58
+#define ACLK_DMAC1 59
+#define HCLK_M0 60
+#define PCLK_BUS_GRF 61
+#define PCLK_TIMER 62
+#define CLK_TIMER0_CH0 63
+#define CLK_TIMER0_CH1 64
+#define CLK_TIMER0_CH2 65
+#define CLK_TIMER0_CH3 66
+#define CLK_TIMER0_CH4 67
+#define CLK_TIMER0_CH5 68
+#define PCLK_WDT0 69
+#define TCLK_WDT0 70
+#define PCLK_WDT1 71
+#define TCLK_WDT1 72
+#define PCLK_MAILBOX 73
+#define PCLK_INTMUX 74
+#define PCLK_SPINLOCK 75
+#define PCLK_DDRC 76
+#define HCLK_DDRPHY 77
+#define PCLK_DDRMON 78
+#define CLK_DDRMON_OSC 79
+#define PCLK_STDBY 80
+#define HCLK_USBOTG0 81
+#define HCLK_USBOTG0_PMU 82
+#define CLK_USBOTG0_ADP 83
+#define HCLK_USBOTG1 84
+#define HCLK_USBOTG1_PMU 85
+#define CLK_USBOTG1_ADP 86
+#define PCLK_USBPHY 87
+#define ACLK_DMA2DDR 88
+#define PCLK_DMA2DDR 89
+#define STCLK_M0 90
+#define CLK_DDRPHY 91
+#define CLK_DDRC_SRC 92
+#define ACLK_DDRC_0 93
+#define ACLK_DDRC_1 94
+#define CLK_DDRC 95
+#define CLK_DDRMON 96
+#define HCLK_LSPERI_ROOT 97
+#define PCLK_LSPERI_ROOT 98
+#define PCLK_UART0 99
+#define PCLK_UART1 100
+#define PCLK_UART2 101
+#define PCLK_UART3 102
+#define PCLK_UART4 103
+#define SCLK_UART0 104
+#define SCLK_UART1 105
+#define SCLK_UART2 106
+#define SCLK_UART3 107
+#define SCLK_UART4 108
+#define PCLK_I2C0 109
+#define CLK_I2C0 110
+#define PCLK_I2C1 111
+#define CLK_I2C1 112
+#define PCLK_I2C2 113
+#define CLK_I2C2 114
+#define PCLK_PWM1 115
+#define CLK_PWM1 116
+#define CLK_OSC_PWM1 117
+#define CLK_RC_PWM1 118
+#define CLK_FREQ_PWM1 119
+#define CLK_COUNTER_PWM1 120
+#define PCLK_SPI0 121
+#define CLK_SPI0 122
+#define PCLK_SPI1 123
+#define CLK_SPI1 124
+#define PCLK_GPIO2 125
+#define DBCLK_GPIO2 126
+#define PCLK_GPIO3 127
+#define DBCLK_GPIO3 128
+#define PCLK_GPIO4 129
+#define DBCLK_GPIO4 130
+#define HCLK_CAN0 131
+#define CLK_CAN0 132
+#define HCLK_CAN1 133
+#define CLK_CAN1 134
+#define HCLK_PDM 135
+#define MCLK_PDM 136
+#define CLKOUT_PDM 137
+#define MCLK_SPDIFTX 138
+#define HCLK_SPDIFTX 139
+#define HCLK_SPDIFRX 140
+#define MCLK_SPDIFRX 141
+#define MCLK_SAI0 142
+#define HCLK_SAI0 143
+#define MCLK_OUT_SAI0 144
+#define MCLK_SAI1 145
+#define HCLK_SAI1 146
+#define MCLK_OUT_SAI1 147
+#define HCLK_ASRC0 148
+#define CLK_ASRC0 149
+#define HCLK_ASRC1 150
+#define CLK_ASRC1 151
+#define PCLK_CRU 152
+#define PCLK_PMU_ROOT 153
+#define MCLK_ASRC0 154
+#define MCLK_ASRC1 155
+#define MCLK_ASRC2 156
+#define MCLK_ASRC3 157
+#define LRCK_ASRC0_SRC 158
+#define LRCK_ASRC0_DST 159
+#define LRCK_ASRC1_SRC 160
+#define LRCK_ASRC1_DST 161
+#define ACLK_HSPERI_ROOT 162
+#define HCLK_HSPERI_ROOT 163
+#define PCLK_HSPERI_ROOT 164
+#define CCLK_SRC_SDMMC 165
+#define HCLK_SDMMC 166
+#define HCLK_FSPI 167
+#define SCLK_FSPI 168
+#define PCLK_SPI2 169
+#define ACLK_MAC0 170
+#define ACLK_MAC1 171
+#define PCLK_MAC0 172
+#define PCLK_MAC1 173
+#define CLK_MAC_ROOT 174
+#define CLK_MAC0 175
+#define CLK_MAC1 176
+#define MCLK_SAI2 177
+#define HCLK_SAI2 178
+#define MCLK_OUT_SAI2 179
+#define MCLK_SAI3_SRC 180
+#define HCLK_SAI3 181
+#define MCLK_SAI3 182
+#define MCLK_OUT_SAI3 183
+#define MCLK_SAI4_SRC 184
+#define HCLK_SAI4 185
+#define MCLK_SAI4 186
+#define HCLK_DSM 187
+#define MCLK_DSM 188
+#define PCLK_AUDIO_ADC 189
+#define MCLK_AUDIO_ADC 190
+#define MCLK_AUDIO_ADC_DIV4 191
+#define PCLK_SARADC 192
+#define CLK_SARADC 193
+#define PCLK_OTPC_NS 194
+#define CLK_SBPI_OTPC_NS 195
+#define CLK_USER_OTPC_NS 196
+#define PCLK_UART5 197
+#define SCLK_UART5 198
+#define PCLK_GPIO234_IOC 199
+#define CLK_MAC_PTP_ROOT 200
+#define CLK_MAC0_PTP 201
+#define CLK_MAC1_PTP 202
+#define CLK_SPI2 203
+#define ACLK_VIO_ROOT 204
+#define HCLK_VIO_ROOT 205
+#define PCLK_VIO_ROOT 206
+#define HCLK_RGA 207
+#define ACLK_RGA 208
+#define CLK_CORE_RGA 209
+#define ACLK_VOP 210
+#define HCLK_VOP 211
+#define DCLK_VOP 212
+#define PCLK_DPHY 213
+#define PCLK_DSI_HOST 214
+#define PCLK_TSADC 215
+#define CLK_TSADC 216
+#define CLK_TSADC_TSEN 217
+#define PCLK_GPIO1_IOC 218
+#define PCLK_OTPC_S 219
+#define CLK_SBPI_OTPC_S 220
+#define CLK_USER_OTPC_S 221
+#define PCLK_OTP_MASK 222
+#define PCLK_KEYREADER 223
+#define HCLK_BOOTROM 224
+#define PCLK_DDR_SERVICE 225
+#define HCLK_CRYPTO_S 226
+#define HCLK_KEYLAD 227
+#define CLK_CORE_CRYPTO 228
+#define CLK_PKA_CRYPTO 229
+#define CLK_CORE_CRYPTO_S 230
+#define CLK_PKA_CRYPTO_S 231
+#define ACLK_CRYPTO_S 232
+#define HCLK_RNG_S 233
+#define CLK_CORE_CRYPTO_NS 234
+#define CLK_PKA_CRYPTO_NS 235
+#define ACLK_CRYPTO_NS 236
+#define HCLK_CRYPTO_NS 237
+#define HCLK_RNG 238
+#define CLK_PMU 239
+#define PCLK_PMU 240
+#define CLK_PMU_32K 241
+#define PCLK_PMU_CRU 242
+#define PCLK_PMU_GRF 243
+#define PCLK_GPIO0_IOC 244
+#define PCLK_GPIO0 245
+#define DBCLK_GPIO0 246
+#define PCLK_GPIO1_SHADOW 247
+#define DBCLK_GPIO1_SHADOW 248
+#define PCLK_PMU_HP_TIMER 249
+#define CLK_PMU_HP_TIMER 250
+#define CLK_PMU_HP_TIMER_32K 251
+#define PCLK_PWM0 252
+#define CLK_PWM0 253
+#define CLK_OSC_PWM0 254
+#define CLK_RC_PWM0 255
+#define CLK_MAC_OUT 256
+#define CLK_REF_OUT0 257
+#define CLK_REF_OUT1 258
+#define CLK_32K_FRAC 259
+#define CLK_32K_RC 260
+#define CLK_32K 261
+#define CLK_32K_PMU 262
+#define PCLK_TOUCH_KEY 263
+#define CLK_TOUCH_KEY 264
+#define CLK_REF_PHY_PLL 265
+#define CLK_REF_PHY_PMU_MUX 266
+#define CLK_WIFI_OUT 267
+#define CLK_V0PLL_REF 268
+#define CLK_V1PLL_REF 269
+#define CLK_32K_FRAC_MUX 270
+
+#endif
diff --git a/include/dt-bindings/clock/rockchip,rv1126b-cru.h b/include/dt-bindings/clock/rockchip,rv1126b-cru.h
new file mode 100644
index 000000000000..721d50a1419f
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rv1126b-cru.h
@@ -0,0 +1,392 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
+
+/* pll clocks */
+#define PLL_GPLL 0
+#define PLL_CPLL 1
+#define PLL_AUPLL 2
+#define ARMCLK 3
+#define SCLK_DDR 4
+
+/* clk (clocks) */
+#define CLK_CPLL_DIV20 5
+#define CLK_CPLL_DIV10 6
+#define CLK_CPLL_DIV8 7
+#define CLK_GPLL_DIV8 8
+#define CLK_GPLL_DIV6 9
+#define CLK_GPLL_DIV4 10
+#define CLK_CPLL_DIV3 11
+#define CLK_GPLL_DIV3 12
+#define CLK_CPLL_DIV2 13
+#define CLK_GPLL_DIV2 14
+#define CLK_CM_FRAC0 15
+#define CLK_CM_FRAC1 16
+#define CLK_CM_FRAC2 17
+#define CLK_UART_FRAC0 18
+#define CLK_UART_FRAC1 19
+#define CLK_AUDIO_FRAC0 20
+#define CLK_AUDIO_FRAC1 21
+#define CLK_AUDIO_INT0 22
+#define CLK_AUDIO_INT1 23
+#define SCLK_UART0_SRC 24
+#define SCLK_UART1 25
+#define SCLK_UART2 26
+#define SCLK_UART3 27
+#define SCLK_UART4 28
+#define SCLK_UART5 29
+#define SCLK_UART6 30
+#define SCLK_UART7 31
+#define MCLK_SAI0 32
+#define MCLK_SAI1 33
+#define MCLK_SAI2 34
+#define MCLK_PDM 35
+#define CLKOUT_PDM 36
+#define MCLK_ASRC0 37
+#define MCLK_ASRC1 38
+#define MCLK_ASRC2 39
+#define MCLK_ASRC3 40
+#define CLK_ASRC0 41
+#define CLK_ASRC1 42
+#define CLK_CORE_PLL 43
+#define CLK_NPU_PLL 44
+#define CLK_VEPU_PLL 45
+#define CLK_ISP_PLL 46
+#define CLK_AISP_PLL 47
+#define CLK_SARADC0_SRC 48
+#define CLK_SARADC1_SRC 49
+#define CLK_SARADC2_SRC 50
+#define HCLK_NPU_ROOT 51
+#define PCLK_NPU_ROOT 52
+#define ACLK_VEPU_ROOT 53
+#define HCLK_VEPU_ROOT 54
+#define PCLK_VEPU_ROOT 55
+#define CLK_CORE_RGA_SRC 56
+#define ACLK_GMAC_ROOT 57
+#define ACLK_VI_ROOT 58
+#define HCLK_VI_ROOT 59
+#define PCLK_VI_ROOT 60
+#define DCLK_VICAP_ROOT 61
+#define CLK_SYS_DSMC_ROOT 62
+#define ACLK_VDO_ROOT 63
+#define ACLK_RKVDEC_ROOT 64
+#define HCLK_VDO_ROOT 65
+#define PCLK_VDO_ROOT 66
+#define DCLK_OOC_SRC 67
+#define DCLK_VOP 68
+#define DCLK_DECOM_SRC 69
+#define PCLK_DDR_ROOT 70
+#define ACLK_SYSMEM_SRC 71
+#define ACLK_TOP_ROOT 72
+#define ACLK_BUS_ROOT 73
+#define HCLK_BUS_ROOT 74
+#define PCLK_BUS_ROOT 75
+#define CCLK_SDMMC0 76
+#define CCLK_SDMMC1 77
+#define CCLK_EMMC 78
+#define SCLK_2X_FSPI0 79
+#define CLK_GMAC_PTP_REF_SRC 80
+#define CLK_GMAC_125M 81
+#define CLK_TIMER_ROOT 82
+#define TCLK_WDT_NS_SRC 83
+#define TCLK_WDT_S_SRC 84
+#define TCLK_WDT_HPMCU 85
+#define CLK_CAN0 86
+#define CLK_CAN1 87
+#define PCLK_PERI_ROOT 88
+#define ACLK_PERI_ROOT 89
+#define CLK_I2C_BUS_SRC 90
+#define CLK_SPI0 91
+#define CLK_SPI1 92
+#define BUSCLK_PMU_SRC 93
+#define CLK_PWM0 94
+#define CLK_PWM2 95
+#define CLK_PWM3 96
+#define CLK_PKA_RKCE_SRC 97
+#define ACLK_RKCE_SRC 98
+#define ACLK_VCP_ROOT 99
+#define HCLK_VCP_ROOT 100
+#define PCLK_VCP_ROOT 101
+#define CLK_CORE_FEC_SRC 102
+#define CLK_CORE_AVSP_SRC 103
+#define CLK_50M_GMAC_IOBUF_VI 104
+#define PCLK_TOP_ROOT 105
+#define CLK_MIPI0_OUT2IO 106
+#define CLK_MIPI1_OUT2IO 107
+#define CLK_MIPI2_OUT2IO 108
+#define CLK_MIPI3_OUT2IO 109
+#define CLK_CIF_OUT2IO 110
+#define CLK_MAC_OUT2IO 111
+#define MCLK_SAI0_OUT2IO 112
+#define MCLK_SAI1_OUT2IO 113
+#define MCLK_SAI2_OUT2IO 114
+#define CLK_CM_FRAC0_SRC 115
+#define CLK_CM_FRAC1_SRC 116
+#define CLK_CM_FRAC2_SRC 117
+#define CLK_UART_FRAC0_SRC 118
+#define CLK_UART_FRAC1_SRC 119
+#define CLK_AUDIO_FRAC0_SRC 120
+#define CLK_AUDIO_FRAC1_SRC 121
+#define ACLK_NPU_ROOT 122
+#define HCLK_RKNN 123
+#define ACLK_RKNN 124
+#define PCLK_GPIO3 125
+#define DBCLK_GPIO3 126
+#define PCLK_IOC_VCCIO3 127
+#define PCLK_SARADC0 128
+#define CLK_SARADC0 129
+#define HCLK_SDMMC1 130
+#define HCLK_VEPU 131
+#define ACLK_VEPU 132
+#define CLK_CORE_VEPU 133
+#define HCLK_FEC 134
+#define ACLK_FEC 135
+#define CLK_CORE_FEC 136
+#define HCLK_AVSP 137
+#define ACLK_AVSP 138
+#define BUSCLK_PMU1_ROOT 139
+#define HCLK_AISP 140
+#define ACLK_AISP 141
+#define CLK_CORE_AISP 142
+#define CLK_CORE_ISP_ROOT 143
+#define PCLK_DSMC 144
+#define ACLK_DSMC 145
+#define HCLK_CAN0 146
+#define HCLK_CAN1 147
+#define PCLK_GPIO2 148
+#define DBCLK_GPIO2 149
+#define PCLK_GPIO4 150
+#define DBCLK_GPIO4 151
+#define PCLK_GPIO5 152
+#define DBCLK_GPIO5 153
+#define PCLK_GPIO6 154
+#define DBCLK_GPIO6 155
+#define PCLK_GPIO7 156
+#define DBCLK_GPIO7 157
+#define PCLK_IOC_VCCIO2 158
+#define PCLK_IOC_VCCIO4 159
+#define PCLK_IOC_VCCIO5 160
+#define PCLK_IOC_VCCIO6 161
+#define PCLK_IOC_VCCIO7 162
+#define HCLK_ISP 163
+#define ACLK_ISP 164
+#define CLK_CORE_ISP 165
+#define HCLK_VICAP 166
+#define ACLK_VICAP 167
+#define DCLK_VICAP 168
+#define ISP0CLK_VICAP 169
+#define HCLK_VPSS 170
+#define ACLK_VPSS 171
+#define CLK_CORE_VPSS 172
+#define PCLK_CSI2HOST0 173
+#define DCLK_CSI2HOST0 174
+#define PCLK_CSI2HOST1 175
+#define DCLK_CSI2HOST1 176
+#define PCLK_CSI2HOST2 177
+#define DCLK_CSI2HOST2 178
+#define PCLK_CSI2HOST3 179
+#define DCLK_CSI2HOST3 180
+#define HCLK_SDMMC0 181
+#define ACLK_GMAC 182
+#define PCLK_GMAC 183
+#define CLK_GMAC_PTP_REF 184
+#define PCLK_CSIPHY0 185
+#define PCLK_CSIPHY1 186
+#define PCLK_MACPHY 187
+#define PCLK_SARADC1 188
+#define CLK_SARADC1 189
+#define PCLK_SARADC2 190
+#define CLK_SARADC2 191
+#define ACLK_RKVDEC 192
+#define HCLK_RKVDEC 193
+#define CLK_HEVC_CA_RKVDEC 194
+#define ACLK_VOP 195
+#define HCLK_VOP 196
+#define HCLK_RKJPEG 197
+#define ACLK_RKJPEG 198
+#define ACLK_RKMMU_DECOM 199
+#define HCLK_RKMMU_DECOM 200
+#define DCLK_DECOM 201
+#define ACLK_DECOM 202
+#define PCLK_DECOM 203
+#define PCLK_MIPI_DSI 204
+#define PCLK_DSIPHY 205
+#define ACLK_OOC 206
+#define ACLK_SYSMEM 207
+#define PCLK_DDRC 208
+#define PCLK_DDRMON 209
+#define CLK_TIMER_DDRMON 210
+#define PCLK_DFICTRL 211
+#define PCLK_DDRPHY 212
+#define PCLK_DMA2DDR 213
+#define CLK_RCOSC_SRC 214
+#define BUSCLK_PMU_MUX 215
+#define BUSCLK_PMU_ROOT 216
+#define PCLK_PMU 217
+#define CLK_XIN_RC_DIV 218
+#define CLK_32K 219
+#define PCLK_PMU_GPIO0 220
+#define DBCLK_PMU_GPIO0 221
+#define PCLK_PMU_HP_TIMER 222
+#define CLK_PMU_HP_TIMER 223
+#define CLK_PMU_32K_HP_TIMER 224
+#define PCLK_PWM1 225
+#define CLK_PWM1 226
+#define CLK_OSC_PWM1 227
+#define CLK_RC_PWM1 228
+#define CLK_FREQ_PWM1 229
+#define CLK_COUNTER_PWM1 230
+#define PCLK_I2C2 231
+#define CLK_I2C2 232
+#define PCLK_UART0 233
+#define SCLK_UART0 234
+#define PCLK_RCOSC_CTRL 235
+#define CLK_OSC_RCOSC_CTRL 236
+#define CLK_REF_RCOSC_CTRL 237
+#define PCLK_IOC_PMUIO0 238
+#define CLK_REFOUT 239
+#define CLK_PREROLL 240
+#define CLK_PREROLL_32K 241
+#define HCLK_PMU_SRAM 242
+#define PCLK_WDT_LPMCU 243
+#define TCLK_WDT_LPMCU 244
+#define CLK_LPMCU 245
+#define CLK_LPMCU_RTC 246
+#define PCLK_LPMCU_MAILBOX 247
+#define HCLK_OOC 248
+#define PCLK_SPI2AHB 249
+#define HCLK_SPI2AHB 250
+#define HCLK_FSPI1 251
+#define HCLK_XIP_FSPI1 252
+#define SCLK_1X_FSPI1 253
+#define PCLK_IOC_PMUIO1 254
+#define PCLK_AUDIO_ADC_PMU 255
+#define MCLK_AUDIO_ADC_PMU 256
+#define MCLK_AUDIO_ADC_DIV4_PMU 257
+#define MCLK_LPSAI 258
+#define ACLK_GIC400 259
+#define PCLK_WDT_NS 260
+#define TCLK_WDT_NS 261
+#define PCLK_WDT_HPMCU 262
+#define HCLK_CACHE 263
+#define PCLK_HPMCU_MAILBOX 264
+#define PCLK_HPMCU_INTMUX 265
+#define CLK_HPMCU 266
+#define CLK_HPMCU_RTC 267
+#define PCLK_RKDMA 268
+#define ACLK_RKDMA 269
+#define PCLK_DCF 270
+#define ACLK_DCF 271
+#define HCLK_RGA 272
+#define ACLK_RGA 273
+#define CLK_CORE_RGA 274
+#define PCLK_TIMER 275
+#define CLK_TIMER0 276
+#define CLK_TIMER1 277
+#define CLK_TIMER2 278
+#define CLK_TIMER3 279
+#define CLK_TIMER4 280
+#define CLK_TIMER5 281
+#define PCLK_I2C0 282
+#define CLK_I2C0 283
+#define PCLK_I2C1 284
+#define CLK_I2C1 285
+#define PCLK_I2C3 286
+#define CLK_I2C3 287
+#define PCLK_I2C4 288
+#define CLK_I2C4 289
+#define PCLK_I2C5 290
+#define CLK_I2C5 291
+#define PCLK_SPI0 292
+#define PCLK_SPI1 293
+#define PCLK_PWM0 294
+#define CLK_OSC_PWM0 295
+#define CLK_RC_PWM0 296
+#define PCLK_PWM2 297
+#define CLK_OSC_PWM2 298
+#define CLK_RC_PWM2 299
+#define PCLK_PWM3 300
+#define CLK_OSC_PWM3 301
+#define CLK_RC_PWM3 302
+#define PCLK_UART1 303
+#define PCLK_UART2 304
+#define PCLK_UART3 305
+#define PCLK_UART4 306
+#define PCLK_UART5 307
+#define PCLK_UART6 308
+#define PCLK_UART7 309
+#define PCLK_TSADC 310
+#define CLK_TSADC 311
+#define HCLK_SAI0 312
+#define HCLK_SAI1 313
+#define HCLK_SAI2 314
+#define HCLK_RKDSM 315
+#define MCLK_RKDSM 316
+#define HCLK_PDM 317
+#define HCLK_ASRC0 318
+#define HCLK_ASRC1 319
+#define PCLK_AUDIO_ADC_BUS 320
+#define MCLK_AUDIO_ADC_BUS 321
+#define MCLK_AUDIO_ADC_DIV4_BUS 322
+#define PCLK_RKCE 323
+#define HCLK_NS_RKCE 324
+#define PCLK_OTPC_NS 325
+#define CLK_SBPI_OTPC_NS 326
+#define CLK_USER_OTPC_NS 327
+#define CLK_OTPC_ARB 328
+#define PCLK_OTP_MASK 329
+#define CLK_TSADC_PHYCTRL 330
+#define LRCK_SRC_ASRC0 331
+#define LRCK_DST_ASRC0 332
+#define LRCK_SRC_ASRC1 333
+#define LRCK_DST_ASRC1 334
+#define PCLK_KEY_READER 335
+#define ACLK_NSRKCE 336
+#define CLK_PKA_NSRKCE 337
+#define PCLK_RTC_ROOT 338
+#define PCLK_GPIO1 339
+#define DBCLK_GPIO1 340
+#define PCLK_IOC_VCCIO1 341
+#define ACLK_USB3OTG 342
+#define CLK_REF_USB3OTG 343
+#define CLK_SUSPEND_USB3OTG 344
+#define HCLK_USB2HOST 345
+#define HCLK_ARB_USB2HOST 346
+#define PCLK_RTC_TEST 347
+#define HCLK_EMMC 348
+#define HCLK_FSPI0 349
+#define HCLK_XIP_FSPI0 350
+#define PCLK_PIPEPHY 351
+#define PCLK_USB2PHY 352
+#define CLK_REF_PIPEPHY_CPLL_SRC 353
+#define CLK_REF_PIPEPHY 354
+#define HCLK_VPSL 355
+#define ACLK_VPSL 356
+#define CLK_CORE_VPSL 357
+#define CLK_MACPHY 358
+#define HCLK_RKRNG_NS 359
+#define HCLK_RKRNG_S_NS 360
+#define CLK_AISP_PLL_SRC 361
+
+/* secure clks */
+#define CLK_USER_OTPC_S 362
+#define CLK_SBPI_OTPC_S 363
+#define PCLK_OTPC_S 364
+#define PCLK_KEY_READER_S 365
+#define HCLK_KL_RKCE_S 366
+#define HCLK_RKCE_S 367
+#define PCLK_WDT_S 368
+#define TCLK_WDT_S 369
+#define CLK_STIMER0 370
+#define CLK_STIMER1 371
+#define PLK_STIMER 372
+#define HCLK_RKRNG_S 373
+#define CLK_PKA_RKCE_S 374
+#define ACLK_RKCE_S 375
+
+#endif
diff --git a/include/dt-bindings/reset/rockchip,rk3506-cru.h b/include/dt-bindings/reset/rockchip,rk3506-cru.h
new file mode 100644
index 000000000000..31c0d4aa410f
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rk3506-cru.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_REST_ROCKCHIP_RK3506_H
+#define _DT_BINDINGS_REST_ROCKCHIP_RK3506_H
+
+/* CRU-->SOFTRST_CON00 */
+#define SRST_NCOREPORESET0_AC 0
+#define SRST_NCOREPORESET1_AC 1
+#define SRST_NCOREPORESET2_AC 2
+#define SRST_NCORESET0_AC 3
+#define SRST_NCORESET1_AC 4
+#define SRST_NCORESET2_AC 5
+#define SRST_NL2RESET_AC 6
+#define SRST_A_CORE_BIU_AC 7
+#define SRST_H_M0_AC 8
+
+/* CRU-->SOFTRST_CON02 */
+#define SRST_NDBGRESET 9
+#define SRST_P_CORE_BIU 10
+#define SRST_PMU 11
+
+/* CRU-->SOFTRST_CON03 */
+#define SRST_P_DBG 12
+#define SRST_POT_DBG 13
+#define SRST_P_CORE_GRF 14
+#define SRST_CORE_EMA_DETECT 15
+#define SRST_REF_PVTPLL_CORE 16
+#define SRST_P_GPIO1 17
+#define SRST_DB_GPIO1 18
+
+/* CRU-->SOFTRST_CON04 */
+#define SRST_A_CORE_PERI_BIU 19
+#define SRST_A_DSMC 20
+#define SRST_P_DSMC 21
+#define SRST_FLEXBUS 22
+#define SRST_A_FLEXBUS 23
+#define SRST_H_FLEXBUS 24
+#define SRST_A_DSMC_SLV 25
+#define SRST_H_DSMC_SLV 26
+#define SRST_DSMC_SLV 27
+
+/* CRU-->SOFTRST_CON05 */
+#define SRST_A_BUS_BIU 28
+#define SRST_H_BUS_BIU 29
+#define SRST_P_BUS_BIU 30
+#define SRST_A_SYSRAM 31
+#define SRST_H_SYSRAM 32
+#define SRST_A_DMAC0 33
+#define SRST_A_DMAC1 34
+#define SRST_H_M0 35
+#define SRST_M0_JTAG 36
+#define SRST_H_CRYPTO 37
+
+/* CRU-->SOFTRST_CON06 */
+#define SRST_H_RNG 38
+#define SRST_P_BUS_GRF 39
+#define SRST_P_TIMER0 40
+#define SRST_TIMER0_CH0 41
+#define SRST_TIMER0_CH1 42
+#define SRST_TIMER0_CH2 43
+#define SRST_TIMER0_CH3 44
+#define SRST_TIMER0_CH4 45
+#define SRST_TIMER0_CH5 46
+#define SRST_P_WDT0 47
+#define SRST_T_WDT0 48
+#define SRST_P_WDT1 49
+#define SRST_T_WDT1 50
+#define SRST_P_MAILBOX 51
+#define SRST_P_INTMUX 52
+#define SRST_P_SPINLOCK 53
+
+/* CRU-->SOFTRST_CON07 */
+#define SRST_P_DDRC 54
+#define SRST_H_DDRPHY 55
+#define SRST_P_DDRMON 56
+#define SRST_DDRMON_OSC 57
+#define SRST_P_DDR_LPC 58
+#define SRST_H_USBOTG0 59
+#define SRST_USBOTG0_ADP 60
+#define SRST_H_USBOTG1 61
+#define SRST_USBOTG1_ADP 62
+#define SRST_P_USBPHY 63
+#define SRST_USBPHY_POR 64
+#define SRST_USBPHY_OTG0 65
+#define SRST_USBPHY_OTG1 66
+
+/* CRU-->SOFTRST_CON08 */
+#define SRST_A_DMA2DDR 67
+#define SRST_P_DMA2DDR 68
+
+/* CRU-->SOFTRST_CON09 */
+#define SRST_USBOTG0_UTMI 69
+#define SRST_USBOTG1_UTMI 70
+
+/* CRU-->SOFTRST_CON10 */
+#define SRST_A_DDRC_0 71
+#define SRST_A_DDRC_1 72
+#define SRST_A_DDR_BIU 73
+#define SRST_DDRC 74
+#define SRST_DDRMON 75
+
+/* CRU-->SOFTRST_CON11 */
+#define SRST_H_LSPERI_BIU 76
+#define SRST_P_UART0 77
+#define SRST_P_UART1 78
+#define SRST_P_UART2 79
+#define SRST_P_UART3 80
+#define SRST_P_UART4 81
+#define SRST_UART0 82
+#define SRST_UART1 83
+#define SRST_UART2 84
+#define SRST_UART3 85
+#define SRST_UART4 86
+#define SRST_P_I2C0 87
+#define SRST_I2C0 88
+
+/* CRU-->SOFTRST_CON12 */
+#define SRST_P_I2C1 89
+#define SRST_I2C1 90
+#define SRST_P_I2C2 91
+#define SRST_I2C2 92
+#define SRST_P_PWM1 93
+#define SRST_PWM1 94
+#define SRST_P_SPI0 95
+#define SRST_SPI0 96
+#define SRST_P_SPI1 97
+#define SRST_SPI1 98
+#define SRST_P_GPIO2 99
+#define SRST_DB_GPIO2 100
+
+/* CRU-->SOFTRST_CON13 */
+#define SRST_P_GPIO3 101
+#define SRST_DB_GPIO3 102
+#define SRST_P_GPIO4 103
+#define SRST_DB_GPIO4 104
+#define SRST_H_CAN0 105
+#define SRST_CAN0 106
+#define SRST_H_CAN1 107
+#define SRST_CAN1 108
+#define SRST_H_PDM 109
+#define SRST_M_PDM 110
+#define SRST_PDM 111
+#define SRST_SPDIFTX 112
+#define SRST_H_SPDIFTX 113
+#define SRST_H_SPDIFRX 114
+#define SRST_SPDIFRX 115
+#define SRST_M_SAI0 116
+
+/* CRU-->SOFTRST_CON14 */
+#define SRST_H_SAI0 117
+#define SRST_M_SAI1 118
+#define SRST_H_SAI1 119
+#define SRST_H_ASRC0 120
+#define SRST_ASRC0 121
+#define SRST_H_ASRC1 122
+#define SRST_ASRC1 123
+
+/* CRU-->SOFTRST_CON17 */
+#define SRST_H_HSPERI_BIU 124
+#define SRST_H_SDMMC 125
+#define SRST_H_FSPI 126
+#define SRST_S_FSPI 127
+#define SRST_P_SPI2 128
+#define SRST_A_MAC0 129
+#define SRST_A_MAC1 130
+
+/* CRU-->SOFTRST_CON18 */
+#define SRST_M_SAI2 131
+#define SRST_H_SAI2 132
+#define SRST_H_SAI3 133
+#define SRST_M_SAI3 134
+#define SRST_H_SAI4 135
+#define SRST_M_SAI4 136
+#define SRST_H_DSM 137
+#define SRST_M_DSM 138
+#define SRST_P_AUDIO_ADC 139
+#define SRST_M_AUDIO_ADC 140
+
+/* CRU-->SOFTRST_CON19 */
+#define SRST_P_SARADC 141
+#define SRST_SARADC 142
+#define SRST_SARADC_PHY 143
+#define SRST_P_OTPC_NS 144
+#define SRST_SBPI_OTPC_NS 145
+#define SRST_USER_OTPC_NS 146
+#define SRST_P_UART5 147
+#define SRST_UART5 148
+#define SRST_P_GPIO234_IOC 149
+
+/* CRU-->SOFTRST_CON21 */
+#define SRST_A_VIO_BIU 150
+#define SRST_H_VIO_BIU 151
+#define SRST_H_RGA 152
+#define SRST_A_RGA 153
+#define SRST_CORE_RGA 154
+#define SRST_A_VOP 155
+#define SRST_H_VOP 156
+#define SRST_VOP 157
+#define SRST_P_DPHY 158
+#define SRST_P_DSI_HOST 159
+#define SRST_P_TSADC 160
+#define SRST_TSADC 161
+
+/* CRU-->SOFTRST_CON22 */
+#define SRST_P_GPIO1_IOC 162
+
+#endif
diff --git a/include/dt-bindings/reset/rockchip,rv1126b-cru.h b/include/dt-bindings/reset/rockchip,rv1126b-cru.h
new file mode 100644
index 000000000000..a7712db319d0
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rv1126b-cru.h
@@ -0,0 +1,405 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RV1126B_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RV1126B_H
+
+/* ==========================list all of reset fields id=========================== */
+/* TOPCRU-->SOFTRST_CON00 */
+
+/* TOPCRU-->SOFTRST_CON15 */
+#define SRST_P_CRU 0
+#define SRST_P_CRU_BIU 1
+
+/* BUSCRU-->SOFTRST_CON00 */
+#define SRST_A_TOP_BIU 2
+#define SRST_A_RKCE_BIU 3
+#define SRST_A_BUS_BIU 4
+#define SRST_H_BUS_BIU 5
+#define SRST_P_BUS_BIU 6
+#define SRST_P_CRU_BUS 7
+#define SRST_P_SYS_GRF 8
+#define SRST_H_BOOTROM 9
+#define SRST_A_GIC400 10
+#define SRST_A_SPINLOCK 11
+#define SRST_P_WDT_NS 12
+#define SRST_T_WDT_NS 13
+
+/* BUSCRU-->SOFTRST_CON01 */
+#define SRST_P_WDT_HPMCU 14
+#define SRST_T_WDT_HPMCU 15
+#define SRST_H_CACHE 16
+#define SRST_P_HPMCU_MAILBOX 17
+#define SRST_P_HPMCU_INTMUX 18
+#define SRST_HPMCU_FULL_CLUSTER 19
+#define SRST_HPMCU_PWUP 20
+#define SRST_HPMCU_ONLY_CORE 21
+#define SRST_T_HPMCU_JTAG 22
+#define SRST_P_RKDMA 23
+#define SRST_A_RKDMA 24
+
+/* BUSCRU-->SOFTRST_CON02 */
+#define SRST_P_DCF 25
+#define SRST_A_DCF 26
+#define SRST_H_RGA 27
+#define SRST_A_RGA 28
+#define SRST_CORE_RGA 29
+#define SRST_P_TIMER 30
+#define SRST_TIMER0 31
+#define SRST_TIMER1 32
+#define SRST_TIMER2 33
+#define SRST_TIMER3 34
+#define SRST_TIMER4 35
+#define SRST_TIMER5 36
+#define SRST_A_RKCE 37
+#define SRST_PKA_RKCE 38
+#define SRST_H_RKRNG_S 39
+#define SRST_H_RKRNG_NS 40
+
+/* BUSCRU-->SOFTRST_CON03 */
+#define SRST_P_I2C0 41
+#define SRST_I2C0 42
+#define SRST_P_I2C1 43
+#define SRST_I2C1 44
+#define SRST_P_I2C3 45
+#define SRST_I2C3 46
+#define SRST_P_I2C4 47
+#define SRST_I2C4 48
+#define SRST_P_I2C5 49
+#define SRST_I2C5 50
+#define SRST_P_SPI0 51
+#define SRST_SPI0 52
+#define SRST_P_SPI1 53
+#define SRST_SPI1 54
+
+/* BUSCRU-->SOFTRST_CON04 */
+#define SRST_P_PWM0 55
+#define SRST_PWM0 56
+#define SRST_P_PWM2 57
+#define SRST_PWM2 58
+#define SRST_P_PWM3 59
+#define SRST_PWM3 60
+
+/* BUSCRU-->SOFTRST_CON05 */
+#define SRST_P_UART1 61
+#define SRST_S_UART1 62
+#define SRST_P_UART2 63
+#define SRST_S_UART2 64
+#define SRST_P_UART3 65
+#define SRST_S_UART3 66
+#define SRST_P_UART4 67
+#define SRST_S_UART4 68
+#define SRST_P_UART5 69
+#define SRST_S_UART5 70
+#define SRST_P_UART6 71
+#define SRST_S_UART6 72
+#define SRST_P_UART7 73
+#define SRST_S_UART7 74
+
+/* BUSCRU-->SOFTRST_CON06 */
+#define SRST_P_TSADC 75
+#define SRST_TSADC 76
+#define SRST_H_SAI0 77
+#define SRST_M_SAI0 78
+#define SRST_H_SAI1 79
+#define SRST_M_SAI1 80
+#define SRST_H_SAI2 81
+#define SRST_M_SAI2 82
+#define SRST_H_RKDSM 83
+#define SRST_M_RKDSM 84
+#define SRST_H_PDM 85
+#define SRST_M_PDM 86
+#define SRST_PDM 87
+
+/* BUSCRU-->SOFTRST_CON07 */
+#define SRST_H_ASRC0 88
+#define SRST_ASRC0 89
+#define SRST_H_ASRC1 90
+#define SRST_ASRC1 91
+#define SRST_P_AUDIO_ADC_BUS 92
+#define SRST_M_AUDIO_ADC_BUS 93
+#define SRST_P_RKCE 94
+#define SRST_H_NS_RKCE 95
+#define SRST_P_OTPC_NS 96
+#define SRST_SBPI_OTPC_NS 97
+#define SRST_USER_OTPC_NS 98
+#define SRST_OTPC_ARB 99
+#define SRST_P_OTP_MASK 100
+
+/* PERICRU-->SOFTRST_CON00 */
+#define SRST_A_PERI_BIU 101
+#define SRST_P_PERI_BIU 102
+#define SRST_P_RTC_BIU 103
+#define SRST_P_CRU_PERI 104
+#define SRST_P_PERI_GRF 105
+#define SRST_P_GPIO1 106
+#define SRST_DB_GPIO1 107
+#define SRST_P_IOC_VCCIO1 108
+#define SRST_A_USB3OTG 109
+#define SRST_H_USB2HOST 110
+#define SRST_H_ARB_USB2HOST 111
+#define SRST_P_RTC_TEST 112
+
+/* PERICRU-->SOFTRST_CON01 */
+#define SRST_H_EMMC 113
+#define SRST_H_FSPI0 114
+#define SRST_H_XIP_FSPI0 115
+#define SRST_S_2X_FSPI0 116
+#define SRST_UTMI_USB2HOST 117
+#define SRST_REF_PIPEPHY 118
+#define SRST_P_PIPEPHY 119
+#define SRST_P_PIPEPHY_GRF 120
+#define SRST_P_USB2PHY 121
+#define SRST_POR_USB2PHY 122
+#define SRST_OTG_USB2PHY 123
+#define SRST_HOST_USB2PHY 124
+
+/* CORECRU-->SOFTRST_CON00 */
+#define SRST_REF_PVTPLL_CORE 125
+#define SRST_NCOREPORESET0 126
+#define SRST_NCORESET0 127
+#define SRST_NCOREPORESET1 128
+#define SRST_NCORESET1 129
+#define SRST_NCOREPORESET2 130
+#define SRST_NCORESET2 131
+#define SRST_NCOREPORESET3 132
+#define SRST_NCORESET3 133
+#define SRST_NDBGRESET 134
+#define SRST_NL2RESET 135
+
+/* CORECRU-->SOFTRST_CON01 */
+#define SRST_A_CORE_BIU 136
+#define SRST_P_CORE_BIU 137
+#define SRST_H_CORE_BIU 138
+#define SRST_P_DBG 139
+#define SRST_POT_DBG 140
+#define SRST_NT_DBG 141
+#define SRST_P_CORE_PVTPLL 142
+#define SRST_P_CRU_CORE 143
+#define SRST_P_CORE_GRF 144
+#define SRST_P_DFT2APB 145
+
+/* PMUCRU-->SOFTRST_CON00 */
+#define SRST_H_PMU_BIU 146
+#define SRST_P_PMU_GPIO0 147
+#define SRST_DB_PMU_GPIO0 148
+#define SRST_P_PMU_HP_TIMER 149
+#define SRST_PMU_HP_TIMER 150
+#define SRST_PMU_32K_HP_TIMER 151
+
+/* PMUCRU-->SOFTRST_CON01 */
+#define SRST_P_PWM1 152
+#define SRST_PWM1 153
+#define SRST_P_I2C2 154
+#define SRST_I2C2 155
+#define SRST_P_UART0 156
+#define SRST_S_UART0 157
+
+/* PMUCRU-->SOFTRST_CON02 */
+#define SRST_P_RCOSC_CTRL 158
+#define SRST_REF_RCOSC_CTRL 159
+#define SRST_P_IOC_PMUIO0 160
+#define SRST_P_CRU_PMU 161
+#define SRST_P_PMU_GRF 162
+#define SRST_PREROLL 163
+#define SRST_PREROLL_32K 164
+#define SRST_H_PMU_SRAM 165
+
+/* PMUCRU-->SOFTRST_CON03 */
+#define SRST_P_WDT_LPMCU 166
+#define SRST_T_WDT_LPMCU 167
+#define SRST_LPMCU_FULL_CLUSTER 168
+#define SRST_LPMCU_PWUP 169
+#define SRST_LPMCU_ONLY_CORE 170
+#define SRST_T_LPMCU_JTAG 171
+#define SRST_P_LPMCU_MAILBOX 172
+
+/* PMU1CRU-->SOFTRST_CON00 */
+#define SRST_P_SPI2AHB 173
+#define SRST_H_SPI2AHB 174
+#define SRST_H_FSPI1 175
+#define SRST_H_XIP_FSPI1 176
+#define SRST_S_1X_FSPI1 177
+#define SRST_P_IOC_PMUIO1 178
+#define SRST_P_CRU_PMU1 179
+#define SRST_P_AUDIO_ADC_PMU 180
+#define SRST_M_AUDIO_ADC_PMU 181
+#define SRST_H_PMU1_BIU 182
+
+/* PMU1CRU-->SOFTRST_CON01 */
+#define SRST_P_LPDMA 183
+#define SRST_A_LPDMA 184
+#define SRST_H_LPSAI 185
+#define SRST_M_LPSAI 186
+#define SRST_P_AOA_TDD 187
+#define SRST_P_AOA_FE 188
+#define SRST_P_AOA_AAD 189
+#define SRST_P_AOA_APB 190
+#define SRST_P_AOA_SRAM 191
+
+/* DDRCRU-->SOFTRST_CON00 */
+#define SRST_P_DDR_BIU 192
+#define SRST_P_DDRC 193
+#define SRST_P_DDRMON 194
+#define SRST_TIMER_DDRMON 195
+#define SRST_P_DFICTRL 196
+#define SRST_P_DDR_GRF 197
+#define SRST_P_CRU_DDR 198
+#define SRST_P_DDRPHY 199
+#define SRST_P_DMA2DDR 200
+
+/* SUBDDRCRU-->SOFTRST_CON00 */
+#define SRST_A_SYSMEM_BIU 201
+#define SRST_A_SYSMEM 202
+#define SRST_A_DDR_BIU 203
+#define SRST_A_DDRSCH0_CPU 204
+#define SRST_A_DDRSCH1_NPU 205
+#define SRST_A_DDRSCH2_POE 206
+#define SRST_A_DDRSCH3_VI 207
+#define SRST_CORE_DDRC 208
+#define SRST_DDRMON 209
+#define SRST_DFICTRL 210
+#define SRST_RS 211
+#define SRST_A_DMA2DDR 212
+#define SRST_DDRPHY 213
+
+/* VICRU-->SOFTRST_CON00 */
+#define SRST_REF_PVTPLL_ISP 214
+#define SRST_A_GMAC_BIU 215
+#define SRST_A_VI_BIU 216
+#define SRST_H_VI_BIU 217
+#define SRST_P_VI_BIU 218
+#define SRST_P_CRU_VI 219
+#define SRST_P_VI_GRF 220
+#define SRST_P_VI_PVTPLL 221
+#define SRST_P_DSMC 222
+#define SRST_A_DSMC 223
+#define SRST_H_CAN0 224
+#define SRST_CAN0 225
+#define SRST_H_CAN1 226
+#define SRST_CAN1 227
+
+/* VICRU-->SOFTRST_CON01 */
+#define SRST_P_GPIO2 228
+#define SRST_DB_GPIO2 229
+#define SRST_P_GPIO4 230
+#define SRST_DB_GPIO4 231
+#define SRST_P_GPIO5 232
+#define SRST_DB_GPIO5 233
+#define SRST_P_GPIO6 234
+#define SRST_DB_GPIO6 235
+#define SRST_P_GPIO7 236
+#define SRST_DB_GPIO7 237
+#define SRST_P_IOC_VCCIO2 238
+#define SRST_P_IOC_VCCIO4 239
+#define SRST_P_IOC_VCCIO5 240
+#define SRST_P_IOC_VCCIO6 241
+#define SRST_P_IOC_VCCIO7 242
+
+/* VICRU-->SOFTRST_CON02 */
+#define SRST_CORE_ISP 243
+#define SRST_H_VICAP 244
+#define SRST_A_VICAP 245
+#define SRST_D_VICAP 246
+#define SRST_ISP0_VICAP 247
+#define SRST_CORE_VPSS 248
+#define SRST_CORE_VPSL 249
+#define SRST_P_CSI2HOST0 250
+#define SRST_P_CSI2HOST1 251
+#define SRST_P_CSI2HOST2 252
+#define SRST_P_CSI2HOST3 253
+#define SRST_H_SDMMC0 254
+#define SRST_A_GMAC 255
+#define SRST_P_CSIPHY0 256
+#define SRST_P_CSIPHY1 257
+
+/* VICRU-->SOFTRST_CON03 */
+#define SRST_P_MACPHY 258
+#define SRST_MACPHY 259
+#define SRST_P_SARADC1 260
+#define SRST_SARADC1 261
+#define SRST_P_SARADC2 262
+#define SRST_SARADC2 263
+
+/* VEPUCRU-->SOFTRST_CON00 */
+#define SRST_REF_PVTPLL_VEPU 264
+#define SRST_A_VEPU_BIU 265
+#define SRST_H_VEPU_BIU 266
+#define SRST_P_VEPU_BIU 267
+#define SRST_P_CRU_VEPU 268
+#define SRST_P_VEPU_GRF 269
+#define SRST_P_GPIO3 270
+#define SRST_DB_GPIO3 271
+#define SRST_P_IOC_VCCIO3 272
+#define SRST_P_SARADC0 273
+#define SRST_SARADC0 274
+#define SRST_H_SDMMC1 275
+
+/* VEPUCRU-->SOFTRST_CON01 */
+#define SRST_P_VEPU_PVTPLL 276
+#define SRST_H_VEPU 277
+#define SRST_A_VEPU 278
+#define SRST_CORE_VEPU 279
+
+/* NPUCRU-->SOFTRST_CON00 */
+#define SRST_REF_PVTPLL_NPU 280
+#define SRST_A_NPU_BIU 281
+#define SRST_H_NPU_BIU 282
+#define SRST_P_NPU_BIU 283
+#define SRST_P_CRU_NPU 284
+#define SRST_P_NPU_GRF 285
+#define SRST_P_NPU_PVTPLL 286
+#define SRST_H_RKNN 287
+#define SRST_A_RKNN 288
+
+/* VDOCRU-->SOFTRST_CON00 */
+#define SRST_A_RKVDEC_BIU 289
+#define SRST_A_VDO_BIU 290
+#define SRST_H_VDO_BIU 291
+#define SRST_P_VDO_BIU 292
+#define SRST_P_CRU_VDO 293
+#define SRST_P_VDO_GRF 294
+#define SRST_A_RKVDEC 295
+#define SRST_H_RKVDEC 296
+#define SRST_HEVC_CA_RKVDEC 297
+#define SRST_A_VOP 298
+#define SRST_H_VOP 299
+#define SRST_D_VOP 300
+#define SRST_A_OOC 301
+#define SRST_H_OOC 302
+#define SRST_D_OOC 303
+
+/* VDOCRU-->SOFTRST_CON01 */
+#define SRST_H_RKJPEG 304
+#define SRST_A_RKJPEG 305
+#define SRST_A_RKMMU_DECOM 306
+#define SRST_H_RKMMU_DECOM 307
+#define SRST_D_DECOM 308
+#define SRST_A_DECOM 309
+#define SRST_P_DECOM 310
+#define SRST_P_MIPI_DSI 311
+#define SRST_P_DSIPHY 312
+
+/* VCPCRU-->SOFTRST_CON00 */
+#define SRST_REF_PVTPLL_VCP 313
+#define SRST_A_VCP_BIU 314
+#define SRST_H_VCP_BIU 315
+#define SRST_P_VCP_BIU 316
+#define SRST_P_CRU_VCP 317
+#define SRST_P_VCP_GRF 318
+#define SRST_P_VCP_PVTPLL 319
+#define SRST_A_AISP_BIU 320
+#define SRST_H_AISP_BIU 321
+#define SRST_CORE_AISP 322
+
+/* VCPCRU-->SOFTRST_CON01 */
+#define SRST_H_FEC 323
+#define SRST_A_FEC 324
+#define SRST_CORE_FEC 325
+#define SRST_H_AVSP 326
+#define SRST_A_AVSP 327
+
+#endif
generated by cgit (git 2.34.1) at 2025-12-27 18:42:28 +0000