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2025-06-20dt-bindings: clock: mediatek: Add #reset-cells property for MT8188Julien Massot
The '#reset-cells' property is permitted for some of the MT8188 clock controllers, but not listed as a valid property. Fixes: 9a5cd59640ac ("dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188") Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Julien Massot <julien.massot@collabora.com> Link: https://lore.kernel.org/r/20250516-dtb-check-mt8188-v2-1-fb60bef1b8e1@collabora.com Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-05-31Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "There are 11 newly supported SoCs, but these are all either new variants of existing designs, or straight reuses of the existing chip in a new package: - RK3562 is a new chip based on the old Cortex-A53 core, apparently a low-cost version of the Cortex-A55 based RK3568/RK3566. - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different set of on-chip peripherals. - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family - Amlogic S6/S7/S7D - Samsung Exynos7870 is an older chip similar to Exynos7885 - WonderMedia wm8950 is a minor variation on the wm8850 chip - Amlogic s805y is almost idential to s805x - Allwinner A523 is similar to A527 and T527 - Qualcomm MSM8926 is a variant of MSM8226 - Qualcomm Snapdragon X1P42100 is related to R1E80100 There are also 65 boards, including reference designs for the chips above, this includes - 12 new boards based on TI K3 series chips, most of them from Toradex - 10 devices using Rockchips RK35xx and PX30 chips - 2 phones and 2 laptops based on Qualcomm Snapdragon designs - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses - 3 Samsung Galaxy phones based on Exynos7870 - 5 Allwinner based boards using a variety of ARMv8 chips - 9 32-bit machines, each based on a different SoC family Aside from the new hardware, there is the usual set of cleanups and newly added hardware support on existing machines, for a total of 965 devicetree changesets" * tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits) MAINTAINERS, mailmap: update Sven Peter's email address arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency arm64: dts: nuvoton: Add pinctrl ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings arm64: dts: blaize-blzp1600: Enable GPIO support dt-bindings: clock: socfpga: convert to yaml arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3562 pcie unit addresses arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3576 pcie unit addresses arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588 arm64: dts: rockchip: Add missing SFC power-domains to rk3576 Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0" arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes arm64: dts: mt6359: Rename RTC node to match binding expectations arm64: dts: mt8365-evk: Add goodix touchscreen support arm64: dts: mediatek: mt8188: Add missing #reset-cells property arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board ...
2025-05-29Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' ↵Stephen Boyd
into clk-next * clk-amlogic: clk: meson: Do not enable by default during compile testing clk: meson-g12a: add missing fclk_div2 to spicc * clk-allwinner: clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support dt-bindings: allwinner: add H616 DE33 clock binding clk: sunxi-ng: h616: Add LVDS reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset clk: sunxi: Do not enable by default during compile testing clk: sunxi-ng: Do not enable by default during compile testing * clk-rockchip: clk: rockchip: rk3528: add slab.h header include clk: rockchip: rk3576: add missing slab.h include clk: rockchip: rename gate-grf clk file clk: rockchip: rename branch_muxgrf to branch_grf_mux clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks clk: rockchip: rk3036: mark ddrphy as critical clk: rockchip: rk3036: fix implementation of usb480m clock mux dt-bindings: clock: rk3036: add SCLK_USB480M clock-id clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region clk: rockchip: Support MMC clocks in GRF region dt-bindings: clock: Add GRF clock definition for RK3528 clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576 clk: rockchip: introduce GRF gates clk: rockchip: introduce auxiliary GRFs dt-bindings: clock: rk3576: add IOC gated clocks clk: rockchip: rk3568: Add PLL rate for 33.3MHz clk: rockchip: Drop empty init callback for rk3588 PLL type clk: rockchip: rk3588: Add PLL rate for 1500 MHz * clk-qcom: clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750 clk: qcom: rpmh: make clkaN optional clk: qcom: Add support for Camera Clock Controller on QCS8300 clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz dt-bindings: clock: add SM6350 QCOM video clock bindings clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs clk: qcom: Fix missing error check for dev_pm_domain_attach()
2025-05-29Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' ↵Stephen Boyd
into clk-next * clk-socfpga: clk: socfpga: stratix10: Optimize local variables clk: socfpga: clk-pll: Optimize local variables * clk-sophgo: clk: sophgo: Add clock controller support for SG2044 SoC clk: sophgo: Add PLL clock controller support for SG2044 SoC dt-bindings: clock: sophgo: add clock controller for SG2044 dt-bindings: soc: sophgo: Add SG2044 top syscon device clk: sophgo: Add support for newly added precise compatible dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC * clk-thead: clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC dt-bindings: clock: thead: Add TH1520 VO clock controller * clk-samsung: clk: samsung: correct clock summary for hsi1 block clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition clk: samsung: exynosautov920: add cpucl1/2 clock support dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions clk: samsung: exynosautov920: add cpucl0 clock support dt-bindings: clock: exynosautov920: add cpucl0 clock definitions clk: samsung: Use samsung CCF common function
2025-05-29Merge branches 'clk-bindings', 'clk-renesas', 'clk-spacemit' and ↵Stephen Boyd
'clk-cleanup' into clk-next * clk-bindings: dt-bindings: clock: Drop st,stm32h7-rcc.txt dt-bindings: clock: convert bcm2835-aux-clock to yaml dt-bindings: clock: Drop maxim,max77686.txt dt-bindings: clock: convert vf610-clock.txt to yaml format * clk-renesas: (26 commits) clk: renesas: r9a09g047: Add XSPI clock/reset clk: renesas: r9a09g047: Add support for xspi mux and divider dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks clk: renesas: Use str_on_off() helper clk: renesas: r9a09g057: Add clock and reset entries for USB2 dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable() clk: renesas: rzv2h: Support static dividers without RMW clk: renesas: rzv2h: Add macro for defining static dividers clk: renesas: rzv2h: Add support for static mux clocks clk: renesas: r9a09g047: Add clock and reset entries for GE3D clk: renesas: rzv2h: Fix a typo clk: renesas: rzv2h: Add support for RZ/V2N SoC clk: renesas: rzv2h: Sort compatible list based on SoC part number dt-bindings: pinctrl: renesas: Document RZ/V2N SoC dt-bindings: clock: renesas: Document RZ/V2N SoC CPG dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert() ... * clk-spacemit: clk: spacemit: k1: Add TWSI8 bus and function clocks clk: spacemit: Add clock support for SpacemiT K1 SoC dt-bindings: clock: spacemit: Add spacemit,k1-pll dt-bindings: soc: spacemit: Add spacemit,k1-syscon * clk-cleanup: clk: test: Forward-declare struct of_phandle_args in kunit/clk.h clk: davinci: Use of_get_available_child_by_name() clk: bcm: rpi: Add NULL check in raspberrypi_clk_register() clk: bcm: rpi: Drop module alias clk: bcm: kona: Remove unused scaled_div_build
2025-05-21Merge tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux ↵Arnd Bergmann
into soc/dt RISC-V SpacemiT DT changes for 6.16 - Add clock driver, fix for pinctrl/uart - Add gpio support, enable LED heartbeat * tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: add gpio LED for system heartbeat riscv: dts: spacemit: add gpio support for K1 SoC riscv: dts: spacemit: Acquire clocks for UART riscv: dts: spacemit: Acquire clocks for pinctrl riscv: dts: spacemit: Add clock tree for SpacemiT K1 dt-bindings: clock: spacemit: Add spacemit,k1-pll dt-bindings: soc: spacemit: Add spacemit,k1-syscon Link: https://lore.kernel.org/r/20250514044841-GYA524674@gentoo Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-21dt-bindings: clock: socfpga: convert to yamlMatthew Gerlach
Convert the clock device tree bindings to yaml for the Altera SoCFPGA Cyclone5, Arria5, and Arria10 chip families. Since the clock nodes are subnodes to Altera SOCFPGA Clock Manager, the yaml was added to socfpga-clk-manager.yaml. Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2025-05-12dt-bindings: allwinner: add H616 DE33 clock bindingRyan Walklin
The Allwinner H616 and variants have a new display engine revision (DE33). Add a clock binding for the DE33. Signed-off-by: Ryan Walklin <ryan@testtoast.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://patch.msgid.link/20250511104042.24249-7-ryan@testtoast.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-05-10dt-bindings: clock: add SM6350 QCOM video clock bindingsKonrad Dybcio
Add device tree bindings for video clock controller for SM6350 SoCs. Signed-off-by: Konrad Dybcio <konradybcio@kernel.org> Co-developed-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250324-sm6350-videocc-v2-2-cc22386433f4@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-07dt-bindings: clock: thead: Add TH1520 VO clock controllerMichal Wilczynski
Add device tree bindings for the TH1520 Video Output (VO) subsystem clock controller. The VO sub-system manages clock gates for multimedia components including HDMI, MIPI, and GPU. Document the VIDEO_PLL requirements for the VO clock controller, which receives its input from the AP clock controller. The VIDEO_PLL is a Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz with maximum FOUTVCO of 2376 MHz. This binding complements the existing AP sub-system clock controller which manages CPU, DPU, GMAC and TEE PLLs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Reviewed-by: Drew Fustini <drew@pdp7.com> Signed-off-by: Drew Fustini <drew@pdp7.com>
2025-05-07dt-bindings: clock: sophgo: add clock controller for SG2044Inochi Amaoto
The clock controller on the SG2044 provides common clock function for all IPs on the SoC. This device requires PLL clock to function normally. Add definition for the clock controller of the SG2044 SoC. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250418020325.421257-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-07dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoCInochi Amaoto
As previous binding uses a wildcard compatible for existed clock device of CV1800 series SoC, it is not suitable for existed requirement. The only exception is sophgo,sg2000-clk, it does match a real device, so keep it as is. Add new precise compatible for existed clock devices of CV1800 series SoCs and make old wildcard compatible deprecated. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250504104553.1447819-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-06dt-bindings: clock: Drop st,stm32h7-rcc.txtRob Herring (Arm)
The binding is already covered by st,stm32-rcc.yaml. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250505161933.1432791-1-robh@kernel.org Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-05-06dt-bindings: clock: convert bcm2835-aux-clock to yamlStefan Wahren
Convert the DT binding document for BCM2835 auxiliary peripheral clock from .txt to YAML. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20250503080949.3945-1-wahrenst@gmx.net Acked-by: Conor Dooley <conor.dooley@microchip.com> [sboyd@kernel.org: Drop aux label] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-05-06dt-bindings: clock: Drop maxim,max77686.txtRob Herring (Arm)
The clock binding for Maxim MAX77686/MAX77802/MAX77620 is already covered by mfd/maxim,max77686.yaml. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250505161943.1433081-1-robh@kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-04-30dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitionsShin Son
Add cpucl1 and cpucl2 clock definitions. CPUCL1/2 refer to CPU Cluster 1 and CPU Cluster 2, which provide clock support for the CPUs on Exynosauto V920 SoC. Signed-off-by: Shin Son <shin.son@samsung.com> Link: https://lore.kernel.org/r/20250428113517.426987-2-shin.son@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-29dt-bindings: clock: convert vf610-clock.txt to yaml formatFrank Li
Convert vf610-clock.txt to yaml format. Additional changes: - swap audio_ext and enet_ext to match existed dts order - remove clock consumer in example Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250411212339.3273202-1-Frank.Li@nxp.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-04-27dt-bindings: clock: exynosautov920: add cpucl0 clock definitionsShin Son
Add cpucl0 clock definitions. CPUCL0 refers to CPU Cluster 0, which provide clock support for the CPUs on Exynosauto V920 SoC. Signed-off-by: Shin Son <shin.son@samsung.com> Link: https://lore.kernel.org/r/20250423044153.1288077-2-shin.son@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-04-17dt-bindings: clock: spacemit: Add spacemit,k1-pllHaylen Chu
Add definition for the PLL found on SpacemiT K1 SoC, which takes the external 24MHz oscillator as input and generates clocks in various frequencies for the system. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250416135406.16284-3-heylenay@4d2.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-04-14dt-bindings: clock: renesas: Document RZ/V2N SoC CPGLad Prabhakar
Document the device tree bindings for the Renesas RZ/V2N (R9A09G056) SoC Clock Pulse Generator (CPG). Update `renesas,rzv2h-cpg.yaml` to include the compatible string for RZ/V2N SoC and adjust the title and description accordingly. Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific clock driver will be reused for this SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-29Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Here's the pile of clk driver patches. The usual suspects^Wsilicon vendors are all here, adding new SoC support and fixing existing code. There are a few patches to the clk framework here as well. They've been baking in linux-next for weeks so I'm hoping we don't have to revert them. The disable OF node patch is probably the scariest one although it seems unlikely that a system would be relying on a driver _not_ probing because the clk never appeared, but you never know. Nothing looks out of the ordinary on the driver side but that's because it's mostly a bunch of data. Core: - Use dev_err_probe() in the clk registration path (Peering into the crystal ball shows many patches that remove printks) - Check for disabled OF nodes in of_clk_get_hw_from_clkspec() New Drivers: - Allwinner A523/T527 clk driver - Qualcomm IPQ9574 NSS clk driver - Qualcomm QCS8300 GPU and video clk drivers - Qualcomm SDM429 RPM clks - Qualcomm QCM6490 LPASS (low power audio) resets - Samsung Exynos2200: driver for several clock controllers (Alive, CMGP, HSI, PERIC/PERIS, TOP, UFS and VFS) - Samsung Exynos7870: Driver for several clock controllers (Alive, MIF, DISP AUD, FSYS, G3D, ISP, MFC and PERI) - Rockchip rk3528 and rk3562 clk driver Updates: - Various fixes to SoC clk drivers for incorrect data, avoid touching protected registers, etc. - Additions for some missing clks in existing SoC clk drivers - DT schema conversions from text to YAML - Kconfig cleanups to allow drivers to be compiled on moar architectures" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits) clk: qcom: Add NSS clock Controller driver for IPQ9574 clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps clk: amlogic: a1: fix a typo clk: amlogic: gxbb: drop non existing 32k clock parent clk: amlogic: gxbb: drop incorrect flag on 32k clock clk: amlogic: g12b: fix cluster A parent data clk: amlogic: g12a: fix mmc A peripheral clock dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles dt-bindings: reset: fix double id on rk3562-cru reset ids drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 dt-bindings: clock: qcom: Add compatible for QCM6490 boards clk: qcom: gdsc: Update the status poll timeout for GDSC clk: qcom: gdsc: Set retain_ff before moving to HW CTRL clk: davinci: remove support for da830 ...
2025-03-29Merge tag 'mips_6.15' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - Add support for multi-cluster configuration - Add quirks for enabling multi-cluster mode on EyeQ6 - Add DTS clocks for ralink - Cleanup realtek DTS - Other cleanups and fixes * tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (35 commits) MIPS: config: omega2+, vocore2: enable CLK_MTMIPS arch: mips: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX MIPS: cm: Fix warning if MIPS_CM is disabled MIPS: Fix Macro name MIPS: ds1287: Match ds1287_set_base_clock() function types MIPS: cevt-ds1287: Add missing ds1287.h include MIPS: dec: Declare which_prom() as static MIPS: Loongson2ef: Replace deprecated strncpy() with strscpy() mips: dts: ralink: mt7628a: update system controller node and its consumers mips: dts: ralink: mt7620a: update system controller node and its consumers mips: dts: ralink: rt3883: update system controller node and its consumers mips: dts: ralink: rt3050: update system controller node and its consumers mips: dts: ralink: rt2880: update system controller node and its consumers dt-bindings: clock: add clock definitions for Ralink SoCs MIPS: Use arch specific syscall name match function mips: dts: realtek: Add restart to Cisco SG220-26P mips: dts: realtek: Add RTL838x SoC peripherals mips: dts: realtek: Replace uart clock property mips: dts: realtek: Correct uart interrupt-parent mips: dts: realtek: Add SoC IRQ node for RTL838x ...
2025-03-26Merge branches 'clk-allwinner', 'clk-amlogic' and 'clk-qcom' into clk-nextStephen Boyd
* clk-allwinner: clk: sunxi-ng: add support for the A523/T527 PRCM CCU clk: sunxi-ng: a523: add reset lines clk: sunxi-ng: a523: add bus clock gates clk: sunxi-ng: a523: remaining mod clocks clk: sunxi-ng: a523: add USB mod clocks clk: sunxi-ng: a523: add interface mod clocks clk: sunxi-ng: a523: add system mod clocks clk: sunxi-ng: a523: add video mod clocks clk: sunxi-ng: a523: Add support for bus clocks clk: sunxi-ng: Add support for the A523/T527 CCU PLLs dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs clk: sunxi-ng: Add support for update bit clk: sunxi-ng: mp: provide wrappers for setting feature flags clk: sunxi-ng: mp: introduce dual-divider clock clk: sunxi-ng: h616: Reparent GPU clock during frequency changes clk: sunxi-ng: h616: Add clock/reset for LCD TCON dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset * clk-amlogic: clk: amlogic: a1: fix a typo clk: amlogic: gxbb: drop non existing 32k clock parent clk: amlogic: gxbb: drop incorrect flag on 32k clock clk: amlogic: g12b: fix cluster A parent data clk: amlogic: g12a: fix mmc A peripheral clock * clk-qcom: (41 commits) clk: qcom: Add NSS clock Controller driver for IPQ9574 clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 dt-bindings: clock: qcom: Add compatible for QCM6490 boards clk: qcom: gdsc: Update the status poll timeout for GDSC clk: qcom: gdsc: Set retain_ff before moving to HW CTRL clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable() clk: qcom: videocc: Constify 'struct qcom_cc_desc' clk: qcom: gpucc: Constify 'struct qcom_cc_desc' clk: qcom: dispcc: Constify 'struct qcom_cc_desc' clk: qcom: camcc: Constify 'struct qcom_cc_desc' dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover clk: qcom: Add support for Video Clock Controller on QCS8300 clk: qcom: Add support for GPU Clock Controller on QCS8300 ...
2025-03-26Merge branches 'clk-rockchip', 'clk-samsung' and 'clk-imx' into clk-nextStephen Boyd
* clk-rockchip: dt-bindings: reset: fix double id on rk3562-cru reset ids clk: rockchip: Add clock controller for the RK3562 dt-bindings: clock: Add RK3562 cru clk: rockchip: rk3528: Add reset lookup table clk: rockchip: Add clock controller driver for RK3528 SoC clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE dt-bindings: clock: Document clock and reset unit of RK3528 clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parent clk: rockchip: rk3568: mark hclk_vi as critical clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066 dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1 * clk-samsung: clk: samsung: Drop unused clk.h and of.h headers clk: samsung: Add missing mod_devicetable.h header clk: samsung: add initial exynos7870 clock driver clk: samsung: introduce Exynos2200 clock driver clk: samsung: clk-pll: add support for pll_4311 dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU dt-bindings: clock: add Exynos2200 SoC clk: samsung: Fix UBSAN panic in samsung_clk_init() clk: samsung: Fix spelling mistake "stablization" -> "stabilization" clk: samsung: exynos990: Add CMU_PERIS block dt-bindings: clock: exynos990: Add CMU_PERIS block * clk-imx: clk: imx8mp: inform CCF of maximum frequency of clocks dt-bindings: clock: imx8m: document nominal/overdrive properties clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parents dt-bindings: clock: imx8mp: add axi clock
2025-03-26Merge branches 'clk-parent', 'clk-renesas', 'clk-mediatek' and 'clk-cleanup' ↵Stephen Boyd
into clk-next * clk-parent: clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec() * clk-renesas: (24 commits) clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1 clk: renesas: r7s9210: Distinguish clocks by clock type clk: renesas: rzg2l: Remove unneeded nullify checks clk: renesas: cpg-mssr: Remove obsolete nullify check clk: renesas: r9a09g057: Add entries for the DMACs clk: renesas: r9a09g047: Add CANFD clocks and resets clk: renesas: r9a09g047: Add CRU0 clocks and resets clk: renesas: rzv2h: Update error message clk: renesas: rzg2l: Update error message clk: renesas: r9a09g047: Add ICU clock/reset clk: renesas: r9a07g043: Fix HP clock source for RZ/Five clk: renesas: r9a09g047: Add SDHI clocks/resets clk: renesas: r8a779h0: Add VSPX clock clk: renesas: r8a779h0: Add FCPVX clock clk: renesas: r8a08g045: Check the source of the CPU PLL settings clk: renesas: r9a09g047: Add WDT clocks and resets clk: renesas: r8a779h0: Add ISP core clocks clk: renesas: r8a779g0: Add ISP core clocks clk: renesas: r8a779a0: Add ISP core clocks ... * clk-mediatek: clk: mediatek: Add SMI LARBs reset for MT8188 dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188 clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitx dt-bindings: clock: mediatek,mt8188: Add VDO1_DPI1_HDMI clock * clk-cleanup: dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles clk: davinci: remove support for da830 dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema clk: mmp: Fix NULL vs IS_ERR() check clk: Print an error when clk registration fails clk: Correct the data types of the variables in clk_calc_new_rates clk: imgtec: use %pe for better readability of errors while printing clk: stm32f4: fix an uninitialized variable clk: keystone: syscon-clk: Do not use syscon helper to build regmap
2025-03-17Merge branch '20250313110359.242491-1-quic_mmanikan@quicinc.com' into ↵Bjorn Andersson
clk-for-6.15 Merge the IPQ9574 NSSCC binding through a topic branch, to allow them to also be merged and used in the DeviceTree source tree.
2025-03-17dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitionsDevi Priya
Add NSSCC clock and reset definitions for ipq9574. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20250313110359.242491-4-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-03-16dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-oppsVladimir Zapolskiy
The switch to multiple power domains implies that the required-opps property shall be updated accordingly, a record in one property corresponds to a record in another one. Fixes: 7ec95ff9abf4 ("dt-bindings: clock: move qcom,x1e80100-camcc to its own file") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20250304143152.1799966-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-03-14Merge tag 'samsung-dt64-6.15' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt Samsung DTS ARM64 changes for v6.15 1. Google GS101: - Disable GSA core pinctrl because its registers are not available for normal world. - Add APM (Active Power Management) mailbox and the ACPM firmware nodes. - Add new boards: Google Pixel 6 Pro (Raven). - Enable framebuffer and reboot-mode. 2. Exynos990: - Add PERIS clock controller, MCT timer 3. Exynos8895: - Define all remaining serial engine (USI) and syscon nodes, add MMC. - Enable microSD and touchsreen on Samsung Galaxy S8 (dreamlte). 4. ExynosAutov920: Add UFS and CPU cache information. 5. Various cleanups. This includes two topic branches with DT bindings, which might be shared with other trees depending on needs: 1. for-v6.15/samsung-clk-dt-bindings with Exynos990 clock controller header constants. 2. for-v6.15/samsung-soc-dt-bindings with Exynos USI serial engines header constants rework. * tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (25 commits) arm64: dts: tesla: Change labels to lower-case arm64: dts: exynos: gs101: Change labels to lower-case arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC arm64: dts: exynosautov920: add CPU cache information arm64: dts: exynos: gs101: add ACPM protocol node arm64: dts: exynos: gs101: add AP to APM mailbox node arm64: dts: exynos: gs101: add SRAM node arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0) arm64: dts: exynos: gs101: align poweroff writes with downstream arm64: dts: exynos: gs101: drop explicit regmap from reboot nodes arm64: dts: exynos8895: Rename PMU nodes to fixup sorting arm64: dts: exynos8895-dreamlte: enable support for the touchscreen arm64: dts: exynos8895-dreamlte: enable support for microSD storage arm64: dts: exynos8895: add a node for mmc arm64: dts: exynos8895: define all usi nodes arm64: dts: exynos8895: add syscon nodes for peric0/1 and fsys0/1 arm64: dts: exynos990: Rename and sort PMU nodes arm64: dts: exynos990: Add CMU_PERIS and MCT nodes dt-bindings: soc: samsung: usi: add USIv1 and samsung,exynos8895-usi dt-bindings: clock: exynos990: Add CMU_PERIS block ... Link: https://lore.kernel.org/r/20250309185601.10616-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-03-14Merge tag 'v6.15-rockchip-dts64-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt New boards: MNT-Reform2 laptop (rk3588), OrangePi5-Ultra (rk3588), Radxa Rock 4D (rk3576), Firefly ROC-RK3576-PC, Photonicat (rk3568) New overlays: Video-adapters for Theobroma boards and one adapter used in hw test scenarios. Interesting bigger changes contain clock support for rk3528; support for the hdmi1 controller as well as hdmi-audio support on both controllers on rk3588; the hdmi-receiver of the rk3588 landed, and rk3576 got basic graphics support and can now do hdmi output. Another big block is that we're now doing overlays way better and are including build-testing for applied overlays to the base dtb - similar to how other arches already do this. Of cours a big list of more controllers for rk3576 (nvmem, sfc), rk3588 (rng, spdif, regulator for gpu power-domain) and rk3528 (saradc, pinctrl) And a huge number of board-level improvements and additions. * tag 'v6.15-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (89 commits) arm64: dts: rockchip: Add SPI NOR device on the ROCK 4D arm64: dts: rockchip: Add SFC nodes for rk3576 arm64: dts: rockchip: Add maskrom button to Radxa E20C arm64: dts: rockchip: Add SARADC node for RK3528 arm64: dts: rockchip: Add user button to Radxa E20C arm64: dts: rockchip: Add leds node to Radxa E20C arm64: dts: rockchip: Add HDMI support for rock-4d arm64: dts: rockchip: enable SCMI clk for RK3528 SoC arm64: dts: rockchip: Enable HDMI receiver on rock-5b arm64: dts: rockchip: Add device tree support for HDMI RX Controller arm64: dts: rockchip: Add rk3528 QoS register node dt-bindings: mfd: syscon: Add rk3528 QoS register compatible arm64: dts: rockchip: add MNT Reform 2 laptop dt-bindings: arm: rockchip: Add MNT Reform 2 (RCORE) dt-bindings: soc: rockchip: Add RK3528 VPU GRF syscon dt-bindings: soc: rockchip: Add RK3528 VO GRF syscon arm64: dts: rockchip: Enable hdmi out display for rk3576-evb-v10 arm64: dts: rockchip: Enable hdmi display on sige5 arm64: dts: rockchip: Add hdmi for rk3576 arm64: dts: rockchip: Add vop for rk3576 ... Link: https://lore.kernel.org/r/13791512.uLZWGnKmhe@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-03-13dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatiblesWolfram Sang
The driver support more SoCs. Add the missing ones. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20250213092728.11659-2-wsa+renesas@sang-engineering.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-03-13dt-bindings: clock: qcom: Add compatible for QCM6490 boardsTaniya Das
On the QCM6490 boards, the LPASS firmware controls the complete clock controller functionalities and associated power domains. However, only the LPASS resets required to be controlled by the high level OS. Thus, add the new QCM6490 compatible to support the reset functionality for Low Power Audio subsystem. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250221-lpass_qcm6490_resets-v5-1-6be0c0949a83@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-03-13dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schemaAndreas Kemnade
Convert the TI clkctrl clock device tree binding to json-schema. Specify the creator of the original binding as a maintainer. reg property is used mostly with one item, in am3xxx also with an arbitrary number of items, so divert from the original binding specifying two (probably meaning one address and one size). The consumer part of the example is left out because the full consumer node would be needed. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20250311180215.173634-1-andreas@kemnade.info Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-03-12dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUsAndre Przywara
The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for the main and the PRCM R-CCU. The source clock list differs in some annoying details, and folding this into the existing Allwinner CCU clock binding document gets quite unwieldy, so create a new document for these CCUs. Add the new compatible string, along with the required input clock lists. This conditionally describes the input clock lists, to make adding support for the other two CCUs easier. Also add the DT binding headers, listing all the clocks with their ID numbers. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250307002628.10684-5-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-03dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftoverVladimir Zapolskiy
Qualcomm x1e80100-camcc was moved to its own dt bindings description file, however a small leftover was left, remove it. Fixes: 7ec95ff9abf4 ("dt-bindings: clock: move qcom,x1e80100-camcc to its own file") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20250303223936.1780441-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-03-03dt-bindings: clock: imx8m: document nominal/overdrive propertiesAhmad Fatoum
The imx8m-clock.yaml binding covers the clock controller inside all of the i.MX8M Q/M/N/P SoCs. All of them have in common that they support two operating modes: nominal and overdrive mode. While the overdrive mode allows for higher frequencies for many IPs, the nominal mode needs a lower SoC voltage, thereby reducing heat generation and power usage. As increasing clock rates beyond the maximum permitted by the supplied SoC voltage can lead to difficult to debug issues, device tree consumers would benefit from knowing what mode is active to enforce the clock rate limits that come with it. To facilitate this, extend the clock controller bindings with an optional fsl,operating-mode property. This intentionally allows the absence of the property, because there is no default suitable for all boards: For i.MX8M Mini and Nano, the kernel SoC DTSIs has assigned-clock-rates that are all achievable in nominal mode. For i.MX8MP, there are some rates only validated for overdrive mode. But even for the i.MX8M Mini/Nano boards, we don't know what rates they may configure at runtime, so it has not been possible so far to infer from just the device tree what the mode is. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.kernel.org/r/20250218-imx8m-clk-v4-1-b7697dc2dcd0@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2025-03-03dt-bindings: clock: imx8mp: add axi clockLaurentiu Mihalcea
Some components of AUDIOMIX (i.e: DSP, OCRAM_A) are clocked by AUDIO_AXI_CLK_ROOT. Since the AUDIOMIX block control manages the clock gates for those components, include their root clock in the list of clocks consumed by the IP. Fixes: 95a0aa7bb10e ("dt-bindings: clock: imx8mp: Add audiomix block control") Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20250226164513.33822-2-laurentiumihalcea111@gmail.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2025-03-01dt-bindings: clock: add clock definitions and documentation for exynos7870 CMUKaustabh Chakraborty
Add unique identifiers for exynos7870 clocks for every bank. It adds all clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and CMU_PERI. Document the devicetree bindings as well. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250301-exynos7870-pmu-clocks-v5-1-715b646d5206@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-01dt-bindings: clock: add Exynos2200 SoCIvaylo Ivanov
Provide dt-schema documentation for Exynos2200 SoC clock controller. Add device tree clock binding definitions for the following CMU blocks: - CMU_ALIVE - CMU_CMGP - CMU_HSI0 - CMU_PERIC0/1/2 - CMU_PERIS - CMU_TOP - CMU_UFS - CMU_VTS Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250223115601.723886-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-28dt-bindings: clock: Add RK3562 cruKever Yang
Document the device tree bindings of the rockchip rk3562 SoC clock and reset unit. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250227105916.2340856-2-kever.yang@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-27dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188Friday Yang
On the MediaTek platform, some SMI LARBs are directly connected to the SMI Common, while others are connected to the SMI Sub-Common, which in turn is connected to the SMI Common. The hardware block diagram can be described as follows. SMI-Common(Smart Multimedia Interface Common) | +----------------+------------------+ | | | | | | | | | | | | | | | larb0 SMI-Sub-Common0 SMI-Sub-Common1 | | | | | larb1 larb2 larb3 larb7 larb9 For previous discussion on the direction of the code modifications, please refer to: https://lore.kernel.org/all/CAFGrd9qZhObQXvm2_abqaX83xMLqxjQETB2= wXpobDWU1CnvkA@mail.gmail.com/ https://lore.kernel.org/all/CAPDyKFpokXV2gJDgowbixTvOH_5VL3B5H8ey hP+KJ5Fasm2rFg@mail.gmail.com/ On the MediaTek MT8188 SoC platform, we encountered power-off failures and SMI bus hang issues during camera stress tests. The issue arises because bus glitches are sometimes produced when MTCMOS powers on or off. While this is fairly normal, the software must handle these glitches to avoid mistaking them for transaction signals. What's more, this issue emerged only after the initial upstreaming of this binding. Without these patches, the SMI becomes unstable during camera stress tests. The software solutions can be summarized as follows: 1. Use CLAMP to disable the SMI sub-common port after turning off the LARB CG and before turning off the LARB MTCMOS. 2. Use CLAMP to disable/enable the SMI sub-common port. 3. Implement an AXI reset for SMI LARBs. This patch add '#reset-cells' for the clock controller located in image, camera and IPE subsystems. Signed-off-by: Friday Yang <friday.yang@mediatek.com> Link: https://lore.kernel.org/r/20250221075058.14180-2-friday.yang@mediatek.com Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-02-26dt-bindings: clock: Document clock and reset unit of RK3528Yao Zi
There are two types of clocks in RK3528 SoC, CRU-managed and SCMI-managed. Independent IDs are assigned to them. For the reset part, differing from previous Rockchip SoCs and downstream bindings which embeds register offsets into the IDs, gapless numbers starting from zero are used. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-21dt-bindings: clock: add clock definitions for Ralink SoCsSergio Paracuellos
Add clock missing definitions for RT2880, RT305X, RT3352, RT3383, RT5350, MT7620 and MT76X8 Ralink SoCs. Update bindings to clarify clock depending on these new introduced constants so consumer nodes can easily use the correct one in DTS files matching properly what is being used in driver code (clock IDs are implicitly used there). Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2025-02-14Merge branch '20250109-qcs8300-mm-patches-new-v4-0-63e8ac268b02@quicinc.com' ↵Bjorn Andersson
into clk-for-6.15 Merge the QCS8300 multimedia clock controllers through a topic branch, to make binding constants available to DeviceTree source as well.
2025-02-14dt-bindings: clock: qcom: Add QCS8300 video clock controllerImran Shaik
The QCS8300 video clock controller is a derivative of SA8775P, but QCS8300 has minor difference. Hence, reuse the SA8775P videocc bindings for QCS8300 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-5-63e8ac268b02@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-14dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300Imran Shaik
The QCS8300 camera clock controller is a derivative of SA8775P, but has an additional clock and minor differences. Hence, reuse the SA8775P camera bindings and add additional clock required for QCS8300. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-3-63e8ac268b02@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-14dt-bindings: clock: qcom: Add GPU clocks for QCS8300Imran Shaik
The QCS8300 GPU clock controller is a derivative of SA8775P, but has few additional clocks and minor differences. Hence, reuse gpucc bindings of SA8775P and add additional clocks required for QCS8300. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-1-63e8ac268b02@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-14dt-bindings: clock: qcom,rpmcc: Add SDM429Daniil Titov
Document the qcom,rpmcc-sdm429 compatible and add BB_CLK3 clock definition. Signed-off-by: Daniil Titov <daniilt971@gmail.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250212-sdm429-rpm-v1-1-0a24ac19a478@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-02-04dt-bindings: clock: exynos990: Add CMU_PERIS blockIgor Belwon
Add CMU_PERIS block compatible, and clock definitions. CMU_PERIS requires one bus clock dependency, and it's used for i.e the MCT. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250104-exynos990-cmu-v1-1-9f54d69286d6@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-02dt-bindings: clock: qcom: Add QCS8300 video clock controllerImran Shaik
The QCS8300 video clock controller is a derivative of SA8775P, but QCS8300 has minor difference. Hence, reuse the SA8775P videocc bindings for QCS8300 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-5-63e8ac268b02@quicinc.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-30 21:21:16 +0000