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2025-04-08mtd: spi-nor: macronix: Add fixups for MX25L3255ECheng Ming Lin
SFDP of MX25L3255E is JESD216, which does not include the Quad Enable bit Requirement in BFPT. As a result, during BFPT parsing, the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable. Therefore, it is necessary to correct this setting by late_init. In addition, MX25L3255E also supports 1-4-4 page program in 3-byte address mode. However, since the 3-byte address 1-4-4 page program is not defined in SFDP, it needs to be configured in late_init. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> Acked-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> [pratyush@kernel.org: move params declaration to top, and use it everywhere] Link: https://lore.kernel.org/r/20250407075400.1113177-4-linchengming884@gmail.com
2025-04-08mtd: spi-nor: macronix: Remove duplicate flash info entriesCheng Ming Lin
To clean up the code and reduce duplication, this entry is removed. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20250407075400.1113177-3-linchengming884@gmail.com
2025-04-08mtd: spi-nor: macronix: Drop the redundant flash info fieldsCheng Ming Lin
Many flash devices share the same ID but have different part numbers. To avoid confusion, the part number field is removed. Additionally, since SFDP already provides size information and functionality covered by no_sfdp_flags, these fields are also removed. Furthermore, when 4-byte address instruction table is available, the SPI_NOR_4B_OPCODES flag is no longer needed and is removed. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20250407075400.1113177-2-linchengming884@gmail.com
2025-03-26Merge tag 'mtd/for-6.15' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd updates from Miquel Raynal: "MTD changes: - The atmel,dataflash binding has been converted to yaml and the physmap one constrained. Some logs are improved, error path are getting reworked a bit, few patches target the use of str_enabled_disabled(). Raw NAND changes: - i.MX8 and i.MX31 now have their own compatible, the Qcom driver got cleaned, the Broadcom driver got fixed. SPI NAND changes: - OTP support has been brought, and ESMT and Micron manufacturer drivers implement it. - Read retry, and Macronix manufacturer driver implement it. SPI NOR changes: - Adding support for few flashes. Few cleanup patches for the core driver, where we touched the headers inclusion list and we start using the scope based mutex cleanup helpers. There is also a bunch of minor improvements and fixes in drivers and bindings" * tag 'mtd/for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (34 commits) dt-bindings: mtd: atmel,dataflash: convert txt to yaml mtd: mchp48l640: Use str_enable_disable() in mchp48l640_write_prepare() mtd: rawnand: gpmi: Use str_enabled_disabled() in gpmi_nand_attach_chip() mtd: mtdpart: Do not supply NULL to printf() dt-bindings: mtd: gpmi-nand: Add compatible string for i.MX8 chips mtd: nand: Fix a kdoc comment mtd: spinand: Improve spinand_info macros style mtd: spi-nor: drop unused <linux/of_platform.h> mtd: spi-nor: explicitly include <linux/of.h> mtd: spi-nor: explicitly include <linux/math64.h> mtd: spi-nor: macronix: add support for mx66{l2, u1}g45g mtd: spi-nor: macronix: Add post_sfdp fixups for Quad Input Page Program mtd: Fix error handling in mtd_device_parse_register() error path mtd: capture device name setting failure when adding mtd mtd: Add check for devm_kcalloc() mtd: Replace kcalloc() with devm_kcalloc() dt-bindings: mtd: physmap: Ensure all properties are defined mtd: rawnand: brcmnand: fix PM resume warning dt-bindings: mtd: mxc-nand: Document fsl,imx31-nand mtd: spinand: macronix: Add support for read retry ...
2025-03-18mtd: spi-nor: drop unused <linux/of_platform.h>Tudor Ambarus
There's nothing used in the SPI NOR core from <linux/of_platform.h>, drop the header inclusion. Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20250307-spi-nor-headers-cleanup-v1-3-c186a9511c1e@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2025-03-18mtd: spi-nor: explicitly include <linux/of.h>Tudor Ambarus
The core driver is using of_property_read_bool() and relies on implicit inclusion of <linux/of.h>, which comes from <linux/mtd/mtd.h>. It is good practice to directly include all headers used, it avoids implicit dependencies and spurious breakage if someone rearranges headers and causes the implicit include to vanish. Include the missing header. Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20250307-spi-nor-headers-cleanup-v1-1-c186a9511c1e@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2025-03-07mtd: spi-nor: explicitly include <linux/math64.h>Tudor Ambarus
swp and otp drivers use div_u64 and div64_u64 and rely on implicit inclusion of <linux/math64.h>. It is good practice to directly include all headers used, it avoids implicit dependencies and spurious breakage if someone rearranges headers and causes the implicit include to vanish. Include the missing header. Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20250223-snor-math64-v2-1-6f0313eea331@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2025-03-07mtd: spi-nor: macronix: add support for mx66{l2, u1}g45gCheng Ming Lin
Due to incorrect values in the 4-BAIT table for these two flash IDs, it is necessary to add these two flash IDs with fixups. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> Link: https://lore.kernel.org/r/20250211063028.382169-3-linchengming884@gmail.com [ta: update commit subject] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2025-03-07mtd: spi-nor: macronix: Add post_sfdp fixups for Quad Input Page ProgramCheng Ming Lin
Although certain Macronix NOR flash support the Quad Input Page Program feature, the corresponding information in the 4-byte Address Instruction Table of these flash is not properly filled. As a result, this feature cannot be enabled as expected. To address this issue, a post_sfdp fixups implementation is required to correct the missing information. Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> Link: https://lore.kernel.org/r/20250211063028.382169-2-linchengming884@gmail.com [ta: fix alignment to match open parenthesis] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2025-02-18mtd: spi-nor: use scope-based mutex cleanup helpersTudor Ambarus
Use scope-based mutex clenup helpers, it reduces the code size. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20250211-spi-nor-guard-mutex-v1-2-05ed77a484d9@linaro.org
2025-02-18mtd: spi-nor: sort headers alphabeticallyTudor Ambarus
Sorting headers alphabetically helps locating duplicates, and makes it easier to figure out where to insert new headers. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20250211-spi-nor-guard-mutex-v1-1-05ed77a484d9@linaro.org
2025-02-17mtd: spi-nor: sst: Fix SST write failureAmit Kumar Mahapatra
'commit 18bcb4aa54ea ("mtd: spi-nor: sst: Factor out common write operation to `sst_nor_write_data()`")' introduced a bug where only one byte of data is written, regardless of the number of bytes passed to sst_nor_write_data(), causing a kernel crash during the write operation. Ensure the correct number of bytes are written as passed to sst_nor_write_data(). Call trace: [ 57.400180] ------------[ cut here ]------------ [ 57.404842] While writing 2 byte written 1 bytes [ 57.409493] WARNING: CPU: 0 PID: 737 at drivers/mtd/spi-nor/sst.c:187 sst_nor_write_data+0x6c/0x74 [ 57.418464] Modules linked in: [ 57.421517] CPU: 0 UID: 0 PID: 737 Comm: mtd_debug Not tainted 6.12.0-g5ad04afd91f9 #30 [ 57.429517] Hardware name: Xilinx Versal A2197 Processor board revA - x-prc-02 revA (DT) [ 57.437600] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 57.444557] pc : sst_nor_write_data+0x6c/0x74 [ 57.448911] lr : sst_nor_write_data+0x6c/0x74 [ 57.453264] sp : ffff80008232bb40 [ 57.456570] x29: ffff80008232bb40 x28: 0000000000010000 x27: 0000000000000001 [ 57.463708] x26: 000000000000ffff x25: 0000000000000000 x24: 0000000000000000 [ 57.470843] x23: 0000000000010000 x22: ffff80008232bbf0 x21: ffff000816230000 [ 57.477978] x20: ffff0008056c0080 x19: 0000000000000002 x18: 0000000000000006 [ 57.485112] x17: 0000000000000000 x16: 0000000000000000 x15: ffff80008232b580 [ 57.492246] x14: 0000000000000000 x13: ffff8000816d1530 x12: 00000000000004a4 [ 57.499380] x11: 000000000000018c x10: ffff8000816fd530 x9 : ffff8000816d1530 [ 57.506515] x8 : 00000000fffff7ff x7 : ffff8000816fd530 x6 : 0000000000000001 [ 57.513649] x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000 [ 57.520782] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0008049b0000 [ 57.527916] Call trace: [ 57.530354] sst_nor_write_data+0x6c/0x74 [ 57.534361] sst_nor_write+0xb4/0x18c [ 57.538019] mtd_write_oob_std+0x7c/0x88 [ 57.541941] mtd_write_oob+0x70/0xbc [ 57.545511] mtd_write+0x68/0xa8 [ 57.548733] mtdchar_write+0x10c/0x290 [ 57.552477] vfs_write+0xb4/0x3a8 [ 57.555791] ksys_write+0x74/0x10c [ 57.559189] __arm64_sys_write+0x1c/0x28 [ 57.563109] invoke_syscall+0x54/0x11c [ 57.566856] el0_svc_common.constprop.0+0xc0/0xe0 [ 57.571557] do_el0_svc+0x1c/0x28 [ 57.574868] el0_svc+0x30/0xcc [ 57.577921] el0t_64_sync_handler+0x120/0x12c [ 57.582276] el0t_64_sync+0x190/0x194 [ 57.585933] ---[ end trace 0000000000000000 ]--- Cc: stable@vger.kernel.org Fixes: 18bcb4aa54ea ("mtd: spi-nor: sst: Factor out common write operation to `sst_nor_write_data()`") Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Bence Csókás <csokas.bence@prolan.hu> [pratyush@kernel.org: add Cc stable tag] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20250213054546.2078121-1-amit.kumar-mahapatra@amd.com
2025-02-03mtd: spi-nor: winbond: Add support for w25q02jvMiquel Raynal
Add support for Winbond w25q02jv spi-nor chip which shares most of w25q01jv's specificities as, this time, the chip is made of 4 different dies. Link: https://www.winbond.com/resource-files/W25Q02JV_DTR%20RevD%2007092024%20Plus.pdf Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20250110-winbond-6-12-rc1-nor-volatile-bit-v3-2-735363f8cc7d@bootlin.com
2025-02-03mtd: spi-nor: winbond: Add support for w25q01jvMiquel Raynal
Add support for Winbond w25q01jv spi-nor chip. This chip is internally made of two dies with linear addressing capabilities to make it transparent to the user that two dies were used. There is one drawback however, the read status operation is racy as the status bit only gives the active die status and not the status of the other die. For commands affecting the two dies, it means if another command is sent too fast after the first die has returned a valid status (deviation can be up to 200us), the chip will get corrupted/in an unstable state. This chip hence requires a better status register read. There are three solutions here: 1- If we assume that the most common situation producing this problem is status register writes, maybe we could change the "non-volatile" status register write commands to become "volatile" status register writes. In practice, what takes time is the write operation of the bits themselves, and not the activation of the feature in the internal circuitry. Enabling "volatile" status register writes would make the writes nearly instant. This approach, besides probably being the less impacting one, could overlook other possible actions where both dies can be used at the same time like a chip erase (or any erase over die boundaries in general). 2- Wait about 200us after getting a first status ready feedback. This 200us is about the maximum possible deviation between dies and would cover all cases. 3- We iterate manually over all internal dies (which takes about 30us per die) until all are ready. This approach will always be faster than a blind delay which represents the maximum deviation, while also being totally safe. This third approach has been adopted. A flash-specific hook for the status register read had to be implemented. Testing with the flash_speed benchmark shown no difference with the existing performances (using the regular status read core function). In practice there are difference in the experimental results below, but they are part of the natural deviation of the benchmark: > Without the fixup $ flash_speed /dev/mtd0 -c100 -d eraseblock write speed is 442 KiB/s eraseblock read speed is 1606 KiB/s page write speed is 439 KiB/s page read speed is 1520 KiB/s 2 page write speed is 441 KiB/s 2 page read speed is 1562 KiB/s erase speed is 68 KiB/s > With the fixup $ flash_speed /dev/mtd0 -c100 -d eraseblock write speed is 428 KiB/s eraseblock read speed is 1626 KiB/s page write speed is 426 KiB/s page read speed is 1538 KiB/s 2 page write speed is 426 KiB/s 2 page read speed is 1574 KiB/s erase speed is 66 KiB/s However, the fixup, whatever which one we pick, must be applied on multi-die chips, which hence must be properly flagged. The SFDP tables implemented give a lot of information but the die details are part of an optional table that is not implemented, hence we use a post parsing fixup hook to set the params->n_dice value manually. Link: https://www.winbond.com/resource-files/W25Q01JV%20SPI%20RevE%2003042024%20Plus.pdf Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20250110-winbond-6-12-rc1-nor-volatile-bit-v3-1-735363f8cc7d@bootlin.com
2025-01-25Merge tag 'mtd/for-6.14' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "MTD changes: - There's been no major core change, just a bunch of driver related improvements. Amongst them the conversion to of_property_present() for non-boolean properties, the addition of the support for Fujitsu MB85RS128TY FRAM, a couple of improvements to the phram driver and the usual load of misc changes. Raw NAND changes: - A new controller driver, from Nuvoton, has been merged - Bastien Curutchet has contributed a series improving the Davinci controller driver, both on the organization of the code, but also on the performance side. The binding has also been converted to yaml, received a new OOB layout and now supports on-die ECC engines - The Qualcomm controller driver has been deeply cleaned to extract some parts of the code into a shared file with the Qualcomm SPI memory controller - Aside from these main changes, the Cadence binding has been converted to yaml, the brcmnand controller driver has received a small fix, otherwise some more minor changes have also made their way in SPI NAND changes: - The SPI NAND subsystem has seen a great improvement, with the advent of DTR operations (DDR operations, which may be extended to the address cycles). The first vendor driver to benefit from these improvements is the Winbond driver - A new manufacturer driver is added SkyHigh, with a new constraint for the core, it is impossible to disable the on-die ECC engine - A Foresee device is also now supported SPI NOR changes: - Several flash entries have been added: Atmel AT25SF321, Spansion S28HL256T and S28HL02GT - Support for vcc-supply regulators and their DT bindings has been added - The mx25u25635f entry has been dropped. The flash shares its ID with mx25u25645g and both parts have an SFDP table. Removing their entry lets them be driven by the generic SFDP-based driver" * tag 'mtd/for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (47 commits) mtd: spinand: skyhigh: Align with recent read from cache variant changes mtd: spinand: winbond: Add support for DTR operations mtd: spinand: winbond: Add comment about naming mtd: spinand: winbond: Update the *JW chip definitions mtd: spinand: Add support for read DTR operations mtd: spinand: Enhance the logic when picking a variant mtd: spinand: Add an optional frequency to read from cache macros mtd: spinand: Create distinct fast and slow read from cache variants mtd: hyperbus: Use of_property_present() for non-boolean properties mtd: st_spi_fsm: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr() mtd: rawnand: davinci: add ROM supported OOB layout mtd: spi-nor: sysfs: constify 'struct bin_attribute' mtd: spi-nor: spansion: Add support for S28HL02GT mtd: spi-nor: spansion: Add support for S28HL256T mtd: spi-nor: extend description of size member of struct flash_info mtd: rawnand: davinci: Reduce polling interval in NAND_OP_WAITRDY_INSTR mtd: rawnand: qcom: Fix build issue on x86 architecture mtd: rawnand: qcom: use FIELD_PREP and GENMASK mtd: nand: Add qpic_common API file mtd: rawnand: qcom: Add qcom prefix to common api ...
2025-01-15Revert "mtd: spi-nor: core: replace dummy buswidth from addr to data"Pratyush Yadav
This reverts commit 98d1fb94ce75f39febd456d6d3cbbe58b6678795. The commit uses data nbits instead of addr nbits for dummy phase. This causes a regression for all boards where spi-tx-bus-width is smaller than spi-rx-bus-width. It is a common pattern for boards to have spi-tx-bus-width == 1 and spi-rx-bus-width > 1. The regression causes all reads with a dummy phase to become unavailable for such boards, leading to a usually slower 0-dummy-cycle read being selected. Most controllers' supports_op hooks call spi_mem_default_supports_op(). In spi_mem_default_supports_op(), spi_mem_check_buswidth() is called to check if the buswidths for the op can actually be supported by the board's wiring. This wiring information comes from (among other things) the spi-{tx,rx}-bus-width DT properties. Based on these properties, SPI_TX_* or SPI_RX_* flags are set by of_spi_parse_dt(). spi_mem_check_buswidth() then uses these flags to make the decision whether an op can be supported by the board's wiring (in a way, indirectly checking against spi-{rx,tx}-bus-width). Now the tricky bit here is that spi_mem_check_buswidth() does: if (op->dummy.nbytes && spi_check_buswidth_req(mem, op->dummy.buswidth, true)) return false; The true argument to spi_check_buswidth_req() means the op is treated as a TX op. For a board that has say 1-bit TX and 4-bit RX, a 4-bit dummy TX is considered as unsupported, and the op gets rejected. The commit being reverted uses the data buswidth for dummy buswidth. So for reads, the RX buswidth gets used for the dummy phase, uncovering this issue. In reality, a dummy phase is neither RX nor TX. As the name suggests, these are just dummy cycles that send or receive no data, and thus don't really need to have any buswidth at all. Ideally, dummy phases should not be checked against the board's wiring capabilities at all, and should only be sanity-checked for having a sane buswidth value. Since we are now at rc7 and such a change might introduce many unexpected bugs, revert the commit for now. It can be sent out later along with the spi_mem_check_buswidth() fix. Fixes: 98d1fb94ce75 ("mtd: spi-nor: core: replace dummy buswidth from addr to data") Reported-by: Alexander Stein <alexander.stein@ew.tq-group.com> Closes: https://lore.kernel.org/linux-mtd/3342163.44csPzL39Z@steina-w/ Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-01-13mtd: spi-nor: sysfs: constify 'struct bin_attribute'Thomas Weißschuh
The sysfs core now allows instances of 'struct bin_attribute' to be moved into read-only memory. Make use of that to protect them against accidental or malicious modifications. Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Acked-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241222-sysfs-const-bin_attr-mtd-v1-1-ee13140a4e9b@weissschuh.net
2025-01-13mtd: spi-nor: spansion: Add support for S28HL02GTTakahiro Kuwano
Infineon S28HL02GT is 3.0V, 2Gb Flash device with Octal interface. It has the same functionalities with S28HS02GT. Link: https://www.infineon.com/dgdl/Infineon-S28HS02GT_S28HS04GT_S28HL02GT_S28HL04GT_2Gb_4Gb_SEMPER_Flash_Octal_interface_1.8V_3.0V-DataSheet-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017f0631e33714d9 Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> [pratyush@kernel.org: add comment with flash name] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/dc6aa706253a5200ff0c0d4523c2540312575c01.1734588106.git.Takahiro.Kuwano@infineon.com
2025-01-13mtd: spi-nor: spansion: Add support for S28HL256TTakahiro Kuwano
Infineon S28HL256T is 3.0V, 256Mb Flash device with Octal interface. It has the same functionalities with S28HS256T(1.8V). Link: https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HL256T_256Mb_SEMPER_Flash_Octal_interface_1_8V_3-DataSheet-v02_00-EN.pdf?fileId=8ac78c8c8fc2dd9c018fc66787aa0657 Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> [pratyush@kernel.org: add comment with flash name] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/f052b04693f1100e725e076fd8a0ae339f8002c4.1734588106.git.Takahiro.Kuwano@infineon.com
2025-01-13mtd: spi-nor: extend description of size member of struct flash_infoTudor Ambarus
We use the size as an indicator whether to parse SFDP or not. We don't introduce a dedicated member for SFDP parsing because we'd like to keep the struct size at a minimum, as it's used for every flash declaration. Ideally we won't have flash entries at all, but there are still flash parameters that aren't defined by SFDP, thus we need to statically specify them. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241219-spi-nor-flash-info-size-desc-v1-1-6b53cf011027@linaro.org
2024-12-06mtd: spi-nor: macronix: remove mx25u25635f from parts list to enable SFDPParth Pancholi
The Macronix mx25u25635f flash device supports SFDP initialization. This commit removes the specific mx25u25635f entry (NOR ID 0xc22539), along with its size and flags, from the NOR parts list. By removing this entry, both mx25u25635f and mx25u25645g (which share the same NOR ID) will utilize the generic flash driver configuration. This change allows both devices (mx25u25635f and mx25u25645g) to leverage SFDP-defined parameters, enabling dual and quad read operations without the need for manual adjustment of no_sfdp_flags. Link: https://www.macronix.com/Lists/Datasheet/Attachments/8663/MX25U25635F,%201.8V,%20256Mb,%20v1.5.pdf Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241105105844.257676-1-parth105105@gmail.com
2024-12-06mtd: spi-nor: support vcc-supply regulatorPeng Fan
SPI NOR flashes needs power supply to work properly. The power supply maybe software controllable per board design. So add the support for an vcc-supply regulator. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> [ta: move devm_regulator_get_enable() to spi_nor_probe().] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241111111946.9048-3-tudor.ambarus@linaro.org
2024-12-06mtd: spi-nor: use local variable for struct deviceTudor Ambarus
Use a local variable for the struct device pointers to avoid dereferencing. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241111111946.9048-2-tudor.ambarus@linaro.org
2024-12-06mtd: spi-nor: macronix: use nor->addr_nbytesTudor Ambarus
Use the nor->addr_nbytes set by the core, we shouldn't use magic numbers or states that are not tracked by the core. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Acked-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241111113609.12093-1-tudor.ambarus@linaro.org
2024-12-06mtd: spi-nor: atmel: add at25sf321 entryMarcus Folkesson
Add entry for the at25sf321 32Mbit SPI flash. This flash is populated on a custom board and was tested at 10MHz frequency using the "ti,da830-spi" SPI controller. Link: https://www.renesas.com/en/document/dst/at25sf321-datasheet?r=1608801 Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241116-spi-nor-v4-1-3de8ac6fd0be@gmail.com
2024-11-29Merge tag 'driver-core-6.13-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core updates from Greg KH: "Here is a small set of driver core changes for 6.13-rc1. Nothing major for this merge cycle, except for the two simple merge conflicts are here just to make life interesting. Included in here are: - sysfs core changes and preparations for more sysfs api cleanups that can come through all driver trees after -rc1 is out - fw_devlink fixes based on many reports and debugging sessions - list_for_each_reverse() removal, no one was using it! - last-minute seq_printf() format string bug found and fixed in many drivers all at once. - minor bugfixes and changes full details in the shortlog" * tag 'driver-core-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (35 commits) Fix a potential abuse of seq_printf() format string in drivers cpu: Remove spurious NULL in attribute_group definition s390/con3215: Remove spurious NULL in attribute_group definition perf: arm-ni: Remove spurious NULL in attribute_group definition driver core: Constify bin_attribute definitions sysfs: attribute_group: allow registration of const bin_attribute firmware_loader: Fix possible resource leak in fw_log_firmware_info() drivers: core: fw_devlink: Fix excess parameter description in docstring driver core: class: Correct WARN() message in APIs class_(for_each|find)_device() cacheinfo: Use of_property_present() for non-boolean properties cdx: Fix cdx_mmap_resource() after constifying attr in ->mmap() drivers: core: fw_devlink: Make the error message a bit more useful phy: tegra: xusb: Set fwnode for xusb port devices drm: display: Set fwnode for aux bus devices driver core: fw_devlink: Stop trying to optimize cycle detection logic driver core: Constify attribute arguments of binary attributes sysfs: bin_attribute: add const read/write callback variants sysfs: implement all BIN_ATTR_* macros in terms of __BIN_ATTR() sysfs: treewide: constify attribute callback of bin_attribute::llseek() sysfs: treewide: constify attribute callback of bin_attribute::mmap() ...
2024-11-19Merge tag 'spi-nor/for-6.13' of ↵Miquel Raynal
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next SPI NOR introduces byte swap support for 8D-8D-8D mode and a user for it: macronix. SPI NOR flashes may swap the bytes on a 16-bit boundary when configured in Octal DTR mode. For such cases the byte order is propagated through SPI MEM to the SPI controllers so that the controllers swap the bytes back at runtime. This avoids breaking the boot sequence because of the endianness problems that appear when the bootloaders use 1-1-1 and the kernel uses 8D-8D-8D with byte swap support. Along with the SPI MEM byte swap support we queue a patch for the SPI MXIC controller that swaps the bytes back at runtime. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEHUIqys8OyG1eHf7fS1VPR6WNFOkFAmczG/oACgkQS1VPR6WN # FOnTCAf/YjH9AimQAFJLRKoGqsf6boh1JppcRh1YTRS+D6+Ap9+s1gJoZZYs5VWA # vNfBzGqDXknBvpmOgoXnuDu2zFs9FUvdN5Kf7w6LiS5qtz7uOxHdVoDQyDgnN6w5 # 9ts7qF7LViBHg/HgTEzQT2Zj6qmvIwUbccIkmJeehWjEP/urzOML5nPnM9g4HZVB # W8B5KQ4TiOY1GxkXvIP6EQS6mDKznP3yl2Hnsmk0HPpSm6D807O2zvT+z1SCxpjy # C8+mYRKsRxHoFGL6UzWgqREGBn2wzF7Ral1CR9SpSZZLLtr6S0shqRzKiiH8eiZK # 1hFpXzMS3OWi4a/5724AWaqcR0Qgqw== # =jf3Q # -----END PGP SIGNATURE----- # gpg: Signature made Tue 12 Nov 2024 10:12:26 AM CET # gpg: using RSA key 1D422ACACF0EC86D5E1DFEDF4B554F47A58D14E9 # gpg: Good signature from "Tudor Ambarus (4096-bit rsa key) <tudor.ambarus@microchip.com>" [full] # gpg: aka "Tudor Ambarus <tudor.ambarus@gmail.com>" [full] # gpg: tudor.ambarus@microchip.com: Verified 15 signatures in the past 5 years. # Encrypted 0 messages. # gpg: tudor.ambarus@gmail.com: Verified 15 signatures in the past 5 years. # Encrypted 0 messages.
2024-11-12mtd: spi-nor: core: replace dummy buswidth from addr to dataCheng Ming Lin
The default dummy cycle for Macronix SPI NOR flash in Octal Output Read Mode(1-1-8) is 20. Currently, the dummy buswidth is set according to the address bus width. In the 1-1-8 mode, this means the dummy buswidth is 1. When converting dummy cycles to bytes, this results in 20 x 1 / 8 = 2 bytes, causing the host to read data 4 cycles too early. Since the protocol data buswidth is always greater than or equal to the address buswidth. Setting the dummy buswidth to match the data buswidth increases the likelihood that the dummy cycle-to-byte conversion will be divisible, preventing the host from reading data prematurely. Fixes: 0e30f47232ab ("mtd: spi-nor: add support for DTR protocol") Cc: stable@vger.kernel.org Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> Link: https://lore.kernel.org/r/20241112075242.174010-2-linchengming884@gmail.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-11-11mtd: spi-nor: winbond: add "w/ and w/o SFDP" commentTudor Ambarus
Commit d35df77707bf ("mtd: spi-nor: winbond: fix w25q128 regression") upstream fixed a regression for flavors of 0xef4018 flash that don't define SFDP tables. Add a comment on the flash definition highlighting that there are flavors of flashes with and without SFDP support. It spares developers searching the entire git log for when we'll better handle these cases. Acked-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20241029080049.96679-1-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-11-05sysfs: treewide: constify attribute callback of bin_is_visible()Thomas Weißschuh
The is_bin_visible() callbacks should not modify the struct bin_attribute passed as argument. Enforce this by marking the argument as const. As there are not many callback implementers perform this change throughout the tree at once. Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Acked-by: Martin K. Petersen <martin.petersen@oracle.com> Acked-by: Jason Gunthorpe <jgg@nvidia.com> Acked-by: Ira Weiny <ira.weiny@intel.com> Acked-by: Krzysztof Wilczyński <kw@linux.com> Link: https://lore.kernel.org/r/20241103-sysfs-const-bin_attr-v2-5-71110628844c@weissschuh.net Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-10-29mtd: spi-nor: spansion: Use nor->addr_nbytes in octal DTR mode in RD_ANY_REG_OPTakahiro Kuwano
In octal DTR mode, RD_ANY_REG_OP needs to use 4-byte address regardless of flash's internal address mode. Use nor->addr_nbytes which is set to 4 during setup. Fixes: eff9604390d6 ("mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OP") Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Link: https://lore.kernel.org/r/20241016000837.17951-1-Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-10-21mtd: Switch back to struct platform_driver::remove()Uwe Kleine-König
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/mtd to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20241007205803.444994-10-u.kleine-koenig@baylibre.com
2024-10-04mtd: spi-nor: add support for Macronix Octal flashAlvinZhou
Add manufacturer ID 0xc2 at the end of ID table to allow manufacturer fixups to be applied for any Macronix flash. This spares us of adding new flash entries for flashes that can be initialized solely based on the SFDP data, but still need the manufacturer hooks to set parameters that can't be discovered at SFDP parsing time. The ID is added in order to set the octal DTR methods. SFDP defines a "Command Sequences to Change to Octal DDR (8D-8D-8D) Mode" which can enable the octal DTR mode. Until that is parsed and used, use the local defined method. Suggested-by: Michael Walle <mwalle@kernel.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Link: https://lore.kernel.org/r/20240926141956.2386374-7-alvinzhou.tw@gmail.com [ta: update commit message and comment in the code] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-10-02mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPTTudor Ambarus
Parse BFPT in order to retrieve the byte order in 8D-8D-8D mode. This info flag will be used as a basis to determine whether there is byte swapping of data for SPI NOR flash in octal DTR mode. The controller driver will check whether byte swapping is supported to determine whether the corresponding operation are supported, thus avoiding the generation of unexpected data order. Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Link: https://lore.kernel.org/r/20240926141956.2386374-5-alvinzhou.tw@gmail.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-10-02mtd: spi-nor: core: Allow specifying the byte order in Octal DTR modeTudor Ambarus
Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. The byte order of 16-bit words is swapped when read or written in 8D-8D-8D mode compared to STR modes. Allow operations to specify the byte order in DTR mode, so that controllers can swap the bytes back at run-time to address the flash's endianness requirements, if they are capable. If the controller is not capable of swapping the bytes, the protocol is downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the bytes is always done regardless if it's a data or register access, so that it comply with the JESD216 requirements: "Byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1". Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Suggested-by: Michael Walle <mwalle@kernel.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Link: https://lore.kernel.org/r/20240926141956.2386374-4-alvinzhou.tw@gmail.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-10-02mtd: spi-nor: add Octal DTR support for Macronix flashAlvinZhou
Create Macronix specify method for enable Octal DTR mode and set 20 dummy cycles to allow running at the maximum supported frequency for Macronix Octal flash. Use number of dummy cycles which is parse by SFDP then convert it to bit pattern and set in CR2 register. Set CR2 register for enable octal DTR mode. Use Read ID to confirm that enabling/disabling octal DTR mode was successful. Macronix ID format is A-A-B-B-C-C in octal DTR mode. To ensure the successful enablement of octal DTR mode, confirm that the 6-byte data is entirely correct. Co-developed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Link: https://lore.kernel.org/r/20240926141956.2386374-2-alvinzhou.tw@gmail.com
2024-09-14mtd: spi-nor: fix flash probingMichael Walle
Fix flash probing by name. Flash entries without a name are allowed since commit 15eb8303bb42 ("mtd: spi-nor: mark the flash name as obsolete"). But it was just until recently that a flash entry without a name was actually introduced. This triggers a bug in the legacy probe by name path. Skip entries without a name to fix it. Fixes: 2095e7da8049 ("mtd: spi-nor: spansion: Add support for S28HS256T") Reported-by: Jon Hunter <jonathanh@nvidia.com> Closes: https://lore.kernel.org/r/66c8ebb0-1324-4ad9-9926-8d4eb7e1e63a@nvidia.com/ Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240909072854.812206-1-mwalle@kernel.org
2024-09-14mtd: spi-nor: spansion: Add support for S28HS256TTakahiro Kuwano
Infineon S28HS256T is 256Mb Octal SPI device which has same functionalities with 512Mb and 1Gb parts. Link: https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HL256T_256Mb_SEMPER_Flash_Octal_interface_1_8V_3-DataSheet-v02_00-EN.pdf?fileId=8ac78c8c8fc2dd9c018fc66787aa0657 Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240830080428.6994-1-Takahiro.Kuwano@infineon.com
2024-09-14mtd: spi-nor: winbond: add Zetta ZD25Q128C supportMichael Walle
Zetta normally uses BAh as its vendor ID. But for the ZD25Q128C they took the one from Winbond and messed up the size parameters in SFDP. Most functions seem compatible with the W25Q128, we just have to fix up the size. Link: http://www.zettadevice.com/upload/file/20150821/DS_Zetta_25Q128_RevA.pdf Link: https://www.lcsc.com/datasheet/lcsc_datasheet_2312081757_Zetta-ZD25Q128CSIGT_C19626875.pdf Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240804221535.291923-1-mwalle@kernel.org
2024-09-14mtd: spi-nor: micron-st: Add n25q064a WP supportBrian Norris
These flash chips are used on Google / TP-Link / ASUS OnHub devices, and OnHub devices are write-protected by default (same as any other ChromeOS/Chromebook system). I've referred to datasheets, and tested on OnHub devices. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240726185825.142733-1-computersforpeace@gmail.com
2024-09-14mtd: spi-nor: sst: Factor out common write operation to `sst_nor_write_data()`Csókás, Bence
Writing to the Flash in `sst_nor_write()` is a 3-step process: first an optional one-byte write to get 2-byte-aligned, then the bulk of the data is written out in vendor-specific 2-byte writes. Finally, if there's a byte left over, another one-byte write. This was implemented 3 times in the body of `sst_nor_write()`. To reduce code duplication, factor out these sub-steps to their own function. Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> [pratyush@kernel.org: fixup whitespace, use %zu instead of %i in WARN()] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240710091401.1282824-1-csokas.bence@prolan.hu
2024-06-21mtd: spi-nor: winbond: fix w25q128 regressionMichael Walle
Commit 83e824a4a595 ("mtd: spi-nor: Correct flags for Winbond w25q128") removed the flags for non-SFDP devices. It was assumed that it wasn't in use anymore. This wasn't true. Add the no_sfdp_flags as well as the size again. We add the additional flags for dual and quad read because they have been reported to work properly by Hartmut using both older and newer versions of this flash, the similar flashes with 64Mbit and 256Mbit already have these flags and because it will (luckily) trigger our legacy SFDP parsing, so newer versions with SFDP support will still get the parameters from the SFDP tables. Reported-by: Hartmut Birr <e9hack@gmail.com> Closes: https://lore.kernel.org/r/CALxbwRo_-9CaJmt7r7ELgu+vOcgk=xZcGHobnKf=oT2=u4d4aA@mail.gmail.com/ Fixes: 83e824a4a595 ("mtd: spi-nor: Correct flags for Winbond w25q128") Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Esben Haabendal <esben@geanix.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240621120929.2670185-1-mwalle@kernel.org
2024-06-18mtd: spi-nor: simplify spi_nor_get_flash_info()Michael Walle
Rework spi_nor_get_flash_info() to make it look more straight forward and esp. don't return early. The latter is a preparation to check for deprecated flashes. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240603134055.1859863-1-mwalle@kernel.org
2024-05-27mtd: spi-nor: get rid of SPI_NOR_NO_FRMichael Walle
The Everspin FRAM devices are the only user of the NO_FR flag. Drop the global flag and instead use a manufacturer fixup for the Everspin flashes to drop the fast read support. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> [pratyush@kernel.org: s/evervision/everspin/g in code and commit message] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240419141249.609534-5-mwalle@kernel.org
2024-05-27mtd: spi-nor: remove .setup() callbackMichael Walle
With the removal of the Xilinx flashes, there is no more flash driver using that hook. The original intention was to let the driver configure special requirements like page size an opcodes. This is already possible by other means and it is unlikely a flash will overwrite the (more or less complex) setup function. Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240419141249.609534-4-mwalle@kernel.org
2024-05-27mtd: spi-nor: get rid of non-power-of-2 page size handlingMichael Walle
The Xilinx flashes were the only users of page sizes that were not power of 2. Support for them has been dropped, thus we can also get rid of the special page size handling for it. Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> [pratyush@kernel.org: fixup minor typos and grammar in commit message] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240419141249.609534-3-mwalle@kernel.org
2024-05-27mtd: spi-nor: Remove support for Xilinx S3AN flashesMichael Walle
These flashes are kind of an oddball for the very old Xilinx Spartan 3 FPGAs to store their bitstream. More importantly, they reuse the Atmel JEDEC manufacturer ID and in fact the at45db081d already blocks the use of the 3S700AN flash chip. It's time to sunset support for these flashes. Signed-off-by: Michael Walle <mwalle@kernel.org> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Cc: Ricardo Ribalda <ribalda@kernel.org> Acked-by: Ricardo Ribalda <ribalda@chromium.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240419141249.609534-2-mwalle@kernel.org
2024-04-29mtd: spi-nor: replace unnecessary div64_u64() with div_u64()Michael Walle
Both occurrences of div64_u64() just have a u8 or u32 divisor. Use div_u64() instead. Many 32 bit architectures can optimize this variant better than a full 64 bit divide. Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/9ba7f4e6-2b8b-44a3-9cac-9ed6e50f1700@moroto.mountain/ Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> [pratyush@kernel.org: touched up commit message] Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Link: https://lore.kernel.org/r/20240429121113.803703-1-mwalle@kernel.org
2024-03-13mtd: spi-nor: core: correct type of iMuhammad Usama Anjum
The i should be signed to find out the end of the loop. Otherwise, i >= 0 is always true and loop becomes infinite. Make its type to be int. Fixes: 6a9eda34418f ("mtd: spi-nor: core: set mtd->eraseregions for non-uniform erase map") Signed-off-by: Muhammad Usama Anjum <usama.anjum@collabora.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20240304090103.818092-1-usama.anjum@collabora.com
2024-02-26mtd: spi-nor: core: set mtd->eraseregions for non-uniform erase mapTakahiro Kuwano
Some of Infineon SPI NOR flash devices support hybrid sector layout that overlays 4KB sectors on a 256KB sector and SPI NOR framework recognizes that by parsing SMPT and construct params->erase_map. The hybrid sector layout is similar to CFI flash devices that have small sectors on top and/or bottom address. In case of CFI flash devices, the erase map information is parsed through CFI table and populated into mtd->eraseregions so that users can create MTD partitions that aligned with small sector boundaries. This patch provides the same capability to SPI NOR flash devices that have non-uniform erase map. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/35d0962986e493b06c13bdf7ada8130a9966dc02.1708404584.git.Takahiro.Kuwano@infineon.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
generated by cgit (git 2.34.1) at 2025-07-30 08:24:46 +0000