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2025-07-31Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This is the usual collection of primarily clk driver updates. The big part of the diff is all the new Qualcomm clk drivers added for a few SoCs they're working on. The other two vendors with significant work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks to existing drivers and supports some new SoCs while Amlogic is starting a significant refactoring to simplify their code. The core framework gained a pair of helpers to get the 'struct device' or 'struct device_node' associated with a 'struct clk_hw'. Some associated KUnit tests were added for these simple helpers as well. Beyond that core change there are lots of little fixes throughout the clk drivers for the stuff we see every day, wrong clk driver data that affects tree topology or supported frequencies, etc. They're not found until the clks are actually used by some consumer device driver. New Drivers: - Global, display, gpu, video, camera, tcsr, and rpmh clock controller for the Qualcomm Milos SoC - Camera, display, GPU, and video clock controllers for Qualcomm QCS615 - Video clock controller driver for Qualcomm SM6350 - Camera clock controller driver for Qualcomm SC8180X - I3C clocks and resets on Renesas RZ/G3E - Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas RZ/V2H(P) and RZ/V2N - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P) - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H - Ethernet clocks and resets on Renesas RZ/G3E - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas RZ/V2N Updates: - Support atomic PWMs in the PWM clk driver - clk_hw_get_dev() and clk_hw_get_of_node() helpers - Replace round_rate() with determine_rate() in various clk drivers - Convert clk DT bindings to DT schema format for DT validation - Various clk driver cleanups and refactorings from static analysis tools and possibly real humans - A lot of little fixes here and there to things like clk tree topology, missing frequencies, flagging clks as critical, etc" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits) clk: clocking-wizard: Fix the round rate handling for versal clk: Fix typos clk: spacemit: ccu_pll: fix error return value in recalc_rate callback clk: tegra: periph: Make tegra_clk_periph_ops static clk: tegra: periph: Fix error handling and resolve unsigned compare warning clk: imx: scu: convert from round_rate() to determine_rate() clk: imx: pllv4: convert from round_rate() to determine_rate() clk: imx: pllv3: convert from round_rate() to determine_rate() clk: imx: pllv2: convert from round_rate() to determine_rate() clk: imx: pll14xx: convert from round_rate() to determine_rate() clk: imx: pfd: convert from round_rate() to determine_rate() clk: imx: frac-pll: convert from round_rate() to determine_rate() clk: imx: fracn-gppll: convert from round_rate() to determine_rate() clk: imx: fixup-div: convert from round_rate() to determine_rate() clk: imx: cpu: convert from round_rate() to determine_rate() clk: imx: busy: convert from round_rate() to determine_rate() clk: imx: composite-93: remove round_rate() in favor of determine_rate() clk: imx: composite-8m: remove round_rate() in favor of determine_rate() clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls clk: imx: Remove redundant pm_runtime_mark_last_busy() calls ...
2025-07-07reset: spacemit: add support for SpacemiT CCU resetsAlex Elder
Implement reset support for SpacemiT CCUs. A SpacemiT reset controller device is an auxiliary device associated with a clock controller (CCU). This patch defines the reset controllers for the MPMU, APBC, and MPMU CCUs, which already define clock controllers. It also adds RCPU, RCPU2, and ACPB2 CCUs, which only define resets. Signed-off-by: Alex Elder <elder@riscstar.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Yixun Lan <dlan@gentoo.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20250702113709.291748-6-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-07-01reset: brcmstb: Enable reset drivers for ARCH_BCM2835Peter Robinson
The BRCMSTB and BRCMSTB_RESCAL reset drivers are also used in the BCM2712, AKA the RPi5. The RPi platforms have typically used the ARCH_BCM2835, and the PCIe support for this SoC can use this config which depends on these drivers so enable building them when just that arch option is enabled to ensure the platform works as expected. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250630175301.846082-1-pbrobinson@gmail.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-06-27reset: thead: Fix TH1520 typoDrew Fustini
Fix trivial typo in the Kconfig entry for RESET_TH1520. Fixes: 4a65326311ab ("reset: thead: Add TH1520 reset controller driver") Signed-off-by: Drew Fustini <drew@pdp7.com> Link: https://lore.kernel.org/r/20250601181000.166088-1-drew@pdp7.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-06-27reset: canaan: add reset driver for Kendryte K230Junhui Liu
Add support for the resets on Canaan Kendryte K230 SoC. The driver support CPU0, CPU1, L2 cache flush, hardware auto clear and software clear resets. Tested-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Link: https://lore.kernel.org/r/20250613-k230-reset-v4-2-e5266d2be440@pigmoral.tech Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-05-05reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)Lad Prabhakar
Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC. Enable control of USB2.0 PHY reset and power-down operations, including assert and deassert functionalities for the PHY. Leverage device tree (OF) data to support future SoCs with similar USB2PHY hardware but varying register configurations. Define initialization values and control register settings to ensure flexibility for upcoming platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Link: https://lore.kernel.org/r/20250415195131.281060-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-04-07reset: thead: Add TH1520 reset controller driverMichal Wilczynski
Add reset controller driver for the T-HEAD TH1520 SoC that manages hardware reset lines for various subsystems. The driver currently implements support for GPU reset control, with infrastructure in place to extend support for NPU and Watchdog Timer resets in future updates. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Link: https://lore.kernel.org/r/20250303152511.494405-3-m.wilczynski@samsung.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2025-03-13reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QMFrank Li
Add System Controller Firmware(SCU) reset driver for i.MX8QM and i.MX8QXP. SCU Manage resets for peripherals such as MIPI CSI. Currently, support two reset sources: IMX_SC_R_CSI_0 and IMX_SC_R_CSI_1. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250210-8qxp_camera-v3-2-324f5105accc@nxp.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-11-22Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The core framework gained a clk provider helper, a clk consumer helper, and some unit tests for the assigned clk rates feature in DeviceTree. On the vendor driver side, we gained a whole pile of SoC driver support detailed below. The majority in the diffstat is Qualcomm, but there's also quite a few Samsung and Mediatek clk driver additions in here as well. The top vendors is quite common, but the sheer amount of new drivers is uncommon, so I'm anticipating a larger number of fixes for clk drivers this cycle. Core: - devm_clk_bulk_get_all_enabled() to return number of clks acquired - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers - KUnit tests for clk-assigned-rates{,-u64} New Drivers: - Marvell PXA1908 SoC clks - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver - TWL6030 clk driver - Nuvoton Arbel BMC NPCM8XX SoC clks - MediaTek MT6735 SoC clks - MediaTek MT7620, MT7628 and MT7688 MMC clks - Add a driver for gated fixed rate clocks - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs - Camera, display and video clock controllers for Qualcomm SA8775P SoCs - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm SAR2130P - Global, camera, display, GPU, and video clock controllers for Qualcomm SM8475 SoCs - RTC power domain and Battery Backup Function (VBATTB) clock support for the Renesas RZ/G3S SoC - Qualcomm IPQ9574 alpha PLLs - Support for i.MX91 CCM in the i.MX93 driver - Microchip LAN969X SoC clks - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and reset on Renesas RZ/V2H(P) - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1 - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP Updates: - Convert more clk bindings to YAML - Various clk driver cleanups: NULL checks, add const, etc. - Remove END/NUM #defines that count number of clks in various binding headers - Continue moving reset drivers to drivers/reset via auxiliary bus" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits) clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access clk: Fix invalid execution of clk_set_rate clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider clk: lan966x: make it selectable for ARCH_LAN969X clk: eyeq: add EyeQ6H west fixed factor clocks clk: eyeq: add EyeQ6H central fixed factor clocks clk: eyeq: add EyeQ5 fixed factor clocks clk: eyeq: add fixed factor clocks infrastructure clk: eyeq: require clock index with phandle in all cases clk: fixed-factor: add clk_hw_register_fixed_factor_index() function dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles clk: clk-axi-clkgen: make sure to enable the AXI bus clock dt-bindings: clock: axi-clkgen: include AXI clk clk: mmp: Add Marvell PXA1908 MPMU driver clk: mmp: Add Marvell PXA1908 APMU driver clk: mmp: Add Marvell PXA1908 APBCP driver clk: mmp: Add Marvell PXA1908 APBC driver dt-bindings: clock: Add Marvell PXA1908 clock bindings clk: mmp: Switch to use struct u32_fract instead of custom one ...
2024-11-18Merge branches 'clk-samsung', 'clk-microchip', 'clk-imx', 'clk-amlogic' and ↵Stephen Boyd
'clk-allwinner' into clk-next * clk-samsung: clk: samsung: Introduce Exynos8895 clock driver clk: samsung: clk-pll: Add support for pll_{1051x,1052x} dt-bindings: clock: samsung: Add Exynos8895 SoC clk: samsung: gs101: make all ufs related clocks critical clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions clk: samsung: Fix out-of-bound access of of_match_node() dt-bindings: clock: samsung: remove define with number of clocks for FSD clk: samsung: fsd: do not define number of clocks in bindings clk: samsung: Fix errors reported by checkpatch clk: samsung: Fix block comment style warnings reported by checkpatch * clk-microchip: clk: lan966x: add support for lan969x SoC clock driver clk: lan966x: prepare driver for lan969x support clk: lan966x: make clk_names const char * const dt-bindings: clock: add support for lan969x * clk-imx: clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains() clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restore clk: imx: clk-scu: fix clk enable state save and restore clk: imx: fracn-gppll: fix pll power up clk: imx: fracn-gppll: correct PLL initialization flow clk: imx: lpcg-scu: SW workaround for errata (e10858) clk: imx: add i.MX91 clk dt-bindings: clock: Add i.MX91 clock support dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition clk: imx93: Move IMX93_CLK_END macro to clk driver clk: imx95-blk-ctl: Add one clock gate for HSIO block dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL * clk-amlogic: clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX clk: amlogic: axg-audio: use the auxiliary reset driver reset: amlogic: Fix small whitespace issue reset: amlogic: add auxiliary reset driver support reset: amlogic: split the device core and platform probe reset: amlogic: move drivers to a dedicated directory reset: amlogic: add reset status support reset: amlogic: use reset number instead of register count reset: amlogic: add driver parameters reset: amlogic: make parameters unsigned reset: amlogic: use generic data matching function reset: amlogic: convert driver to regmap dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema clk: meson: meson8b: remove spinlock clk: meson: mpll: Delete a useless spinlock from the MPLL clk: meson: s4: pll: fix frac maximum value for hifi_pll clk: meson: c3: pll: fix frac maximum value for hifi_pll clk: meson: Support PLL with fixed fractional denominators clk: meson: s4: pll: hifi_pll support fractional multiplier * clk-allwinner: clk: sunxi-ng: Use of_property_present() for non-boolean properties clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset clk: sunxi-ng: Constify struct ccu_reset_map clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL
2024-10-24reset: mchp: sparx5: Allow building as a moduleClément Léger
This reset controller can be used by the LAN966x PCI device. The LAN966x PCI device driver can be built as a module and this reset controller driver has no reason to be a builtin driver in that case. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20241014124636.24221-6-herve.codina@bootlin.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-10-24reset: mchp: sparx5: Add MCHP_LAN966X_PCI dependencyHerve Codina
The sparx5 reset controller depends on the SPARX5 architecture or the LAN966x SoC. This reset controller can be used by the LAN966x PCI device and so it needs to be available when the LAN966x PCI device is enabled. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20241014124636.24221-5-herve.codina@bootlin.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-10-17reset: npcm: register npcm8xx clock auxiliary bus deviceTomer Maimon
Add NPCM8xx clock controller auxiliary bus device registration. The NPCM8xx clock controller is registered as an aux device because the reset and the clock controller share the same register region. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Benjamin Fair <benjaminfair@google.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240912191038.981105-3-tmaimon77@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-01reset: amlogic: move drivers to a dedicated directoryJerome Brunet
The meson reset driver will be split in two part, one implemeting the ops, the other providing the platform driver support. This will be done to facilitate the addition of the auxiliary bus support. To avoid making a mess in drivers/reset/ while doing so, move the amlogic reset drivers to a dedicated directory. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240910-meson-rst-aux-v5-7-60be62635d3e@baylibre.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-10-01reset: amlogic: convert driver to regmapJerome Brunet
To allow using the same driver for the main reset controller and the auxiliary ones embedded in the clock controllers, convert the the Amlogic reset driver to regmap. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240910-meson-rst-aux-v5-1-60be62635d3e@baylibre.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-09-02reset: eyeq: add platform driverThéo Lebrun
Add Mobileye EyeQ reset controller driver, for EyeQ5, EyeQ6L and EyeQ6H SoCs. Instances belong to a shared register region called OLB and gets spawned as auxiliary device to the platform driver for clock. There is one OLB instance for EyeQ5 and EyeQ6L. There are seven OLB instances on EyeQ6H; three have a reset controller embedded: - West and east get handled by the same compatible. - Acc (accelerator) is another one. Each instance vary in the number and types of reset domains. Instances with single domain expect a single cell, others two. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20240730-mbly-reset-v2-2-00b870a6a2ff@bootlin.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-07-16Merge tag 'soc-drivers-6.11' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "The updates to the mediatek, allwinner, ti, tegra, microchip, stm32, samsung, imx, zynq and amlogic platoforms are fairly small maintenance changes, either addressing minor mistakes or enabling additional hardware. The qualcomm platform changes add a number of features and are larger than the other ones combined, introducing the use of linux/cleanup.h across several drivers, adding support for Snapdragon X1E and other SoCs in platform drivers, a new "protection domain mapper" driver, and a "shared memory bridge" driver. The cznic "turris omnia" router based on Marvell Armada gets a platform driver that talks to the board specific microcontroller. The reset and cache subsystems get a few minor updates to SoC specific drivers, while the ff-a, scmi and optee firmware drivers get some code refactoring and new features" * tag 'soc-drivers-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (122 commits) firmware: turris-mox-rwtm: Initialize completion before mailbox firmware: turris-mox-rwtm: Fix checking return value of wait_for_completion_timeout() firmware: turris-mox-rwtm: Do not complete if there are no waiters MAINTAINERS: drop riscv list from cache controllers platform: cznic: turris-omnia-mcu: fix Kconfig dependencies bus: sunxi-rsb: Constify struct regmap_bus soc: sunxi: sram: Constify struct regmap_config platform: cznic: turris-omnia-mcu: Depend on WATCHDOG platform: cznic: turris-omnia-mcu: Depend on OF soc: samsung: exynos-pmu: add support for PMU_ALIVE non atomic registers arm64: stm32: enable scmi regulator for stm32 firmware: qcom: tzmem: blacklist more platforms for SHM Bridge soc: qcom: wcnss: simplify with cleanup.h soc: qcom: pdr: simplify with cleanup.h soc: qcom: ocmem: simplify with cleanup.h soc: qcom: mdt_loader: simplify with cleanup.h soc: qcom: llcc: simplify with cleanup.h firmware: qcom: tzmem: simplify returning pointer without cleanup soc: qcom: socinfo: Add PM6350 PMIC arm64: dts: renesas: rz-smarc: Replace fixed regulator for USB VBUS ...
2024-06-25reset: RESET_IMX8MP_AUDIOMIX should depend on ARCH_MXCGeert Uytterhoeven
The i.MX8MP AudioMix reset controller is only present on Freescale i.MX8 SoCs. Hence add a dependency on ARCH_MXC, to prevent asking the user about this driver when configuring a kernel without i.MX SoC support. Fixes: fe125601d17cc1ea ("reset: imx8mp-audiomix: Add AudioMix Block Control reset driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/6d8116a56186fbf468229e823c7c8dfcd9488959.1719316665.git.geert+renesas@glider.be Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-06-24reset: zynqmp: allow building under COMPILE_TESTPhilipp Zabel
The ZynqMP reset driver can be compiled without ARCH_ZYNQMP being enabled. Allow it to be built under COMPILE_TEST. Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20240621-reset-compile-zynqmp-v1-1-ede43ab18101@pengutronix.de Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-06-24reset: imx8mp-audiomix: Add AudioMix Block Control reset driverShengjiu Wang
Add support for the resets on i.MX8MP Audio Block Control module, which includes the EARC PHY software reset and EARC controller software reset. The reset controller is created using the auxiliary device framework and set up in the clock driver. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/1719200345-32006-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-06-21reset: gpio: Fix missing gpiolib dependency for GPIO reset controllerMark Brown
The GPIO reset controller uses gpiolib but there is no Kconfig dependency reflecting this fact, add one. With the addition of the controller to the arm64 defconfig this is causing build breaks for arm64 virtconfig in -next: aarch64-linux-gnu-ld: drivers/reset/core.o: in function `__reset_add_reset_gpio_lookup': /build/stage/linux/drivers/reset/core.c:861:(.text+0xccc): undefined reference to `gpio_device_find_by_fwnode' Fixes: cee544a40e44 ("reset: gpio: Add GPIO-based reset controller") Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20240325-reset-gpiolib-deps-v2-1-3ed2517f5f53@kernel.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-04-05reset: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210Yangyu Chen
Since SOC_FOO should be deprecated from patch [1], and cleanup for other SoCs is already in the mailing list [2,3,4,5], we remove the use of SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers, Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select when it has the symbol SOC_CANAAN_K210. [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/ [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/ [5] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-02-21reset: gpio: Add GPIO-based reset controllerKrzysztof Kozlowski
Add a simple driver to control GPIO-based resets using the reset controller API for the cases when the GPIOs are shared and reset should be coordinated. The driver is expected to be used by reset core framework for ad-hoc reset controllers. Cc: Bartosz Golaszewski <brgl@bgdev.pl> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240129115216.96479-4-krzysztof.kozlowski@linaro.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2024-02-21reset: simple: add support for Sophgo SG2042Chen Wang
Reuse reset-simple driver for the Sophgo SG2042 reset generator. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/1cfd7b3ba447942784c4f7aa595e962399e9f617.1706577450.git.unicorn_wang@outlook.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2023-06-29Merge tag 'soc-drivers-6.5' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "Nothing surprising in the SoC specific drivers, with the usual updates: - Added or improved SoC driver support for Tegra234, Exynos4121, RK3588, as well as multiple Mediatek and Qualcomm chips - SCMI firmware gains support for multiple SMC/HVC transport and version 3.2 of the protocol - Cleanups amd minor changes for the reset controller, memory controller, firmware and sram drivers - Minor changes to amd/xilinx, samsung, tegra, nxp, ti, qualcomm, amlogic and renesas SoC specific drivers" * tag 'soc-drivers-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (118 commits) dt-bindings: interrupt-controller: Convert Amlogic Meson GPIO interrupt controller binding MAINTAINERS: add PHY-related files to Amlogic SoC file list drivers: meson: secure-pwrc: always enable DMA domain tee: optee: Use kmemdup() to replace kmalloc + memcpy soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer dt-bindings: sram: qcom,imem: document qdu1000 soc: qcom: icc-bwmon: Fix MSM8998 count unit dt-bindings: soc: qcom,rpmh-rsc: Require power-domains soc: qcom: socinfo: Add Soc ID for IPQ5300 dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300 soc: qcom: Fix a IS_ERR() vs NULL bug in probe soc: qcom: socinfo: Add support for new fields in revision 19 soc: qcom: socinfo: Add support for new fields in revision 18 dt-bindings: firmware: scm: Add compatible for SDX75 soc: qcom: mdt_loader: Fix split image detection dt-bindings: memory-controllers: drop unneeded quotes soc: rockchip: dtpm: use C99 array init syntax firmware: tegra: bpmp: Add support for DRAM MRQ GSCs soc/tegra: pmc: Use devm_clk_notifier_register() soc/tegra: pmc: Simplify debugfs initialization ...
2023-06-06reset: RESET_NUVOTON_MA35D1 should depend on ARCH_MA35Geert Uytterhoeven
The Nuvoton MA35D1 reset controller is only present on Nuvoton MA35 SoCs. Hence add a dependency on ARCH_MA35, to prevent asking the user about this driver when configuring a kernel without MA35 SoC support. Also, do not enable the driver by default when merely compile-testing. While at it, fix a misspelling of "Nuvoton". Fixes: e4bb55d6ccf0f774 ("reset: Add Nuvoton ma35d1 reset driver support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-05reset: Add Nuvoton ma35d1 reset driver supportJacky Huang
This driver supports individual IP reset for the MA35D1. The reset control registers are a subset of the system control registers. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-05-08reset: mpfs: select AUXILIARY_BUSPhilipp Zabel
CONFIG_AUXILIARY_BUS is not a user-visible symbol, replace 'depends on' with 'select'. Cc: Daire McNamara <daire.mcnamara@microchip.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20230502102041.1418397-1-p.zabel@pengutronix.de Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2023-05-08reset: oxnas: remove obsolete reset driverNeil Armstrong
Due to lack of maintainance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 peripheral reset. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Daniel Golle <daniel@makrotopia.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230331-topic-oxnas-upstream-remove-v1-17-5bd58fd1dd1f@linaro.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2023-04-05reset: Create subdirectory for StarFive driversEmil Renner Berthing
This moves the StarFive JH7100 reset driver to a new subdirectory in preparation for adding more StarFive reset drivers. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVEHal Feng
Using ARCH_FOO symbol is preferred than SOC_FOO. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-01-03reset: ti-sci: honor TI_SCI_PROTOCOL setting when not COMPILE_TESTRandy Dunlap
There is a build error when COMPILE_TEST=y, TI_SCI_PROTOCOL=m, and RESET_TI_SCI=y: drivers/reset/reset-ti-sci.o: in function `ti_sci_reset_probe': reset-ti-sci.c:(.text+0x22c): undefined reference to `devm_ti_sci_get_handle' Fix this by making RESET_TI_SCI honor the Kconfig setting of TI_SCI_PROTOCOL when COMPILE_TEST is not set. When COMPILE_TEST is set, TI_SCI_PROTOCOL must be disabled (=n). Fixes: a6af504184c9 ("reset: ti-sci: Allow building under COMPILE_TEST") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Nishanth Menon <nm@ti.com> Cc: Tero Kristo <kristo@kernel.org> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221030055636.3139-1-rdunlap@infradead.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2022-10-08Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have some late breaking reports that a patch series to rework clk rate range support broke boot on some devices, so I've left that branch out of this. Hopefully we can get to that next week, or punt on it and let it bake another cycle. That means we don't really have any changes to the core framework this time around besides a few typo fixes. Instead this is all clk driver updates and fixes. The usual suspects are here (again), with Qualcomm dominating the diffstat. We look to have gained support for quite a few new Qualcomm SoCs and Dmitry worked on updating many of the existing Qualcomm drivers to use clk_parent_data. After that we have MediaTek drivers getting some much needed updates, in particular to support GPU DVFS. There are also quite a few Samsung clk driver patches, but that's mostly because there was a maintainer change and so last release we missed some of those patches. Overall things look normal, but I'm slowly reviewing core framework code nowadays and that shows given the rate range patches had to be yanked last minute. Let's hope this situation changes soon. New Drivers: - Support for Renesas VersaClock7 clock generator family - Add Spreadtrum UMS512 SoC clk support - New clock drivers for MediaTek Helio X10 MT6795 - Display clks for Qualcomm SM6115, SM8450 - GPU clks for Qualcomm SC8280XP - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers Deleted Drivers: - Remove DaVinci DM644x and DM646x clk driver support Updates: - Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - More devm helpers for fixed rate registration - Various PXA168 clk driver fixes - Add resets for MediaTek MT8195 PCIe and USB - Miscellaneous of_node_put() fixes - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock - Convert gpio-clk-gate binding to YAML - Various fixes to AMD/Xilinx Zynqmp clk driver - Graduate AMD/Xilinx "clocking wizard" driver from staging - Add missing DPI1_HDMI clock in MT8195 VDOSYS1 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195 - Fix GPU clock topology on MT8195 - Propogate rate changes from GPU clock gate up the tree - Clock mux notifiers for GPU-related PLLs - Conversion of more "simple" drivers to mtk_clk_simple_probe() - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers - Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek - Shrink MT8192 clock driver by deduplicating clock parent lists - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk' clocks for i.MX8MP - Drop unnecessary newline in i.MX8MM dt-bindings - Add more MU1 and SAI clocks dt-bindings Ids - Introduce slice busy bit check for i.MX93 composite clock - Introduce white list bit check for i.MX93 composite clock - Add new i.MX93 clock gate - Add MU1 and MU2 clocks to i.MX93 clock provider - Add SAI IPG clocks to i.MX93 clock provider - add generic clocks for U(S)ART available on SAMA5D2 SoCs - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8 - Add I2C clocks and resets on RZ/V2M - Document clock support for the RZ/Five SoC - mux-variant clock using the table variant to select parents - clock controller for the rv1126 soc - conversion of rk3128 to yaml and relicensing of the yaml bindings to gpl2+MIT (following dt-binding guildelines) - Exynos7885: add FSYS, TREX and MFC clock controllers - Exynos850: add IS and AUD (audio) clock controllers with bindings - ExynosAutov9: add FSYS clock controllers with bindings - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock controllers, due to duplicated entries. This is an acceptable ABI break: recently developed/added platform so without legacies, acked by known users/developers - ExynosAutov9: add few missing Peric 0/1 gates - ExynosAutov9: correct register offsets of few Peric 0/1 clocks - Minor code improvements (use of_device_get_match_data() helper, code style) - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he already maintainers that architecture/platform - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration - Qualcomm SDM660 SDCC1 moved to floor clk ops - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was added/fixed - The Qualcomm MSM8996 CPU clocks are updated with support for ACD - Support for Qualcomm SDM670 GCC and RPMh clks was added - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for num_parents was done for many Qualcomm SoCs - Support for per-reset defined delay on Qualcomm was introduced" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: allow building lan966x as a module clk: clk-xgene: simplify if-if to if-else clk: ast2600: BCLK comes from EPLL clk: clocking-wizard: Depend on HAS_IOMEM clk: clocking-wizard: Use dev_err_probe() helper clk: nxp: fix typo in comment clk: pxa: add a check for the return value of kzalloc() clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975 dt-bindings: clock: vc5: Add 5P49V6975 clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe clk: Renesas versaclock7 ccf device driver dt-bindings: Renesas versaclock7 device tree bindings clk: ti: Balance of_node_get() calls for of_find_node_by_name() clk: imx: scu: fix memleak on platform_device_add() fails clk: vc5: Use regmap_{set,clear}_bits() where appropriate ...
2022-09-14reset: add polarfire soc reset supportConor Dooley
Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is created using the aux device framework & set up in the clock driver. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-6-conor.dooley@microchip.com
2022-08-15arm64: bcmbca: Make BCM4908 drivers depend on ARCH_BCMBCAWilliam Zhang
With Broadcom Broadband arch ARCH_BCMBCA supported in the kernel, this patch series migrate the ARCH_BCM4908 symbol to ARCH_BCMBCA. Hence replace ARCH_BCM4908 with ARCH_BCMBCA in subsystem Kconfig files. Signed-off-by: William Zhang <william.zhang@broadcom.com> Acked-by: Guenter Roeck <linux@roeck-us.net> (for watchdog) Acked-by: Bjorn Helgaas <bhelgaas@google.com> (for drivers/pci) Acked-by: Wolfram Sang <wsa@kernel.org> (for i2c) Acked-by: Philipp Zabel <p.zabel@pengutronix.de> (for reset) Link: https://lore.kernel.org/r/20220803175455.47638-7-william.zhang@broadcom.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-08-05Merge tag 'arm-late-6.0' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull more ARM SoC updates from Arnd Bergmann: "These updates came in after I had already tagged the branches, but they still seem appropriate for 6.0 and most of them were part of linux-next through other trees. - The reset controller tree adds one new driver for the TI TPS380x power management chip and a few minor changes in other drivers - Apple M1 now has a DT entry for the NVMe controller after the driver was merged, and has a new mailing list in the MAINTAINERS file. - Fixes for USB on the Socionext Uniphier platforms and the network controller on Intel Cyclone5" * tag 'arm-late-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: uniphier: Fix USB interrupts for PXs3 SoC ARM: dts: uniphier: Fix USB interrupts for PXs2 SoC arm64: dts: apple: t8103: Add ANS2 NVMe nodes reset: tps380x: Fix spelling mistake "Voltags" -> "Voltage" reset: tps380x: Add TPS380x device driver supprt dt-bindings: reset: Add TPS380x documentation dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G2UL USBPHY Control bindings ARM: dts: add EMAC AXI settings for Cyclone5 reset: reset-simple should depends on HAS_IOMEM Revert "reset: microchip-sparx5: allow building as a module" reset: a10sr: allow building under COMPILE_TEST reset: allow building of reset simple driver if expert config selected reset: microchip-sparx5: allow building as a module arm64: dts: apple: Re-parent ANS2 power domains MAINTAINERS: add ARM/APPLE MACHINE mailing list
2022-07-27reset: tps380x: Add TPS380x device driver supprtMarco Felsch
The TI TPS380x family [1] is a voltage supervisor with a dedicated manual reset (mr) line input and a reset output. The chip(s) have a build in reset delay, depending on the chip partnumber. This simple driver addresses this so the cosumer don't need to care about it. [1] https://www.ti.com/product/TPS3801 Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> [p.zabel@pengutronix.de: drop Todo comment about min/typ/max reset time] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220530092226.748644-2-m.felsch@pengutronix.de
2022-07-20reset: reset-simple should depends on HAS_IOMEMBen Dooks
The reset-simple driver does not build on all architecuters as it requires devm_ioremap_resource() which is only built when CONFIG_HAS_IOMEM is enabled in the kenrel. Fix the following error by depending on CONFIG_HAS_IOMEM: drivers/reset/reset-simple.o: in function `reset_simple_probe': reset-simple.c:(.text+0x3aa): undefined reference to `devm_ioremap_resource' Fixes: 18d1909be345 ("reset: allow building of reset simple driver if expert config selected") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220719085200.203688-1-ben.dooks@sifive.com
2022-07-13Revert "reset: microchip-sparx5: allow building as a module"Philipp Zabel
This reverts commit b6b9585876da018bdde2d5f15d206a689c0d70f3. This breaks MDIO on kswitch-d10, presumably because the global switch reset is not released early enough anymore. Reported-by: Michael Walle <michael@walle.cc> Cc: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220713084010.168720-1-p.zabel@pengutronix.de
2022-07-11reset: a10sr: allow building under COMPILE_TESTPhilipp Zabel
This driver can be built under COMPILE_TEST. Allow it. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220711130624.1217599-1-p.zabel@pengutronix.de
2022-07-11reset: allow building of reset simple driver if expert config selectedBen Dooks
If CONFIG_EXPERT is selected, allow selection of CONFIG_RESET_SIMPLE if needed by the user. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220708165656.269507-1-ben.dooks@sifive.com
2022-07-08reset: Add Sunplus SP7021 reset driverQin Jian
Add reset driver for Sunplus SP7021 SoC. Signed-off-by: Qin Jian <qinjian@cqplus1.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-06-29reset: microchip-sparx5: allow building as a moduleClément Léger
Set RESET_MCHP_SPARX5 as a tristate and add MODULE_DEVICE_TABLE() to allow building this driver as a module. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220617103730.490588-1-clement.leger@bootlin.com
2022-05-09Merge tag 'ti-driver-soc-for-v5.19' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/drivers TI Driver updates for v5.19 * wkup_m3: io isolation, voltage scaling, vtt regulator and a debug option to stop m3 in suspend. * tisci: support for polled mode for system suspend, reset driver is now enabled for COMPILE_TEST * knav, dma.. misc cleanups for IS_ERR, pm_run_time*, and various other fixups. * tag 'ti-driver-soc-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: soc: ti: wkup_m3_ipc: Add debug option to halt m3 in suspend soc: ti: wkup_m3_ipc: Add support for i2c voltage scaling soc: ti: wkup_m3_ipc: Add support for IO Isolation soc: ti: knav_qmss_queue: Use IS_ERR instead of IS_ERR_OR_NULL when checking knav_queue_open() result soc: ti: pm33xx: using pm_runtime_resume_and_get instead of pm_runtime_get_sync firmware: ti_sci: Switch transport to polled mode during system suspend soc: ti: wkup_m3_ipc: Add support for toggling VTT regulator soc: ti: knav_qmss_queue: Use pm_runtime_resume_and_get instead of pm_runtime_get_sync soc: ti: knav_dma: Use pm_runtime_resume_and_get instead of pm_runtime_get_sync reset: ti-sci: Allow building under COMPILE_TEST soc: ti: ti_sci_pm_domains: Check for null return of devm_kcalloc soc: ti: omap_prm: Use of_device_get_match_data() soc: ti: pruss: using pm_runtime_resume_and_get instead of pm_runtime_get_sync soc: ti: replace usage of found with dedicated list iterator variable soc: ti: wkup_m3_ipc: fix platform_get_irq.cocci warning Link: https://lore.kernel.org/r/20220507163424.pvqnwrxpoo73lmp2@debtless Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-03reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2LLad Prabhakar
The USBPHY Control block is identical on Renesas RZ/G2L and RZ/V2L SoC's, so instead of adding dependency for each SoC's add dependency on ARCH_RZG2L. The ARCH_RZG2L config option is already selected by ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220406071647.14037-1-prabhakar.mahadev-lad.rj@bp.renesas.com
2022-04-15reset: ti-sci: Allow building under COMPILE_TESTPhilipp Zabel
Since commit 043cfff99a18 ("firmware: ti_sci: Fix compilation failure when CONFIG_TI_SCI_PROTOCOL is not defined") it is possible to build reset-ti-sci under CONFIG_COMPILE_TEST. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20220404094500.2708816-1-p.zabel@pengutronix.de
2022-02-25reset: Add Delta TN48M CPLD reset controllerRobert Marko
Delta TN48M CPLD exposes resets for the following: * 88F7040 SoC * 88F6820 SoC * 98DX3265 switch MAC-s * 88E1680 PHY-s * 88E1512 PHY * PoE PSE controller Controller supports only self clearing resets. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20220131133049.77780-5-robert.marko@sartura.hr Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-12-16reset: starfive-jh7100: Add StarFive JH7100 reset driverEmil Renner Berthing
Add a driver for the StarFive JH7100 reset controller. Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-11-03Merge tag 'drivers-5.16' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "These are all the driver updates for SoC specific drivers. There are a couple of subsystems with individual maintainers picking up their patches here: - The reset controller subsystem add support for a few new SoC variants to existing drivers, along with other minor improvements - The OP-TEE subsystem gets a driver for the ARM FF-A transport - The memory controller subsystem has improvements for Tegra, Mediatek, Renesas, Freescale and Broadcom specific drivers. - The tegra cpuidle driver changes get merged through this tree this time. There are only minor changes, but they depend on other tegra driver updates here. - The ep93xx platform finally moves to using the drivers/clk/ subsystem, moving the code out of arch/arm in the process. This depends on a small sound driver change that is included here as well. - There are some minor updates for Qualcomm and Tegra specific firmware drivers. The other driver updates are mainly for drivers/soc, which contains a mixture of vendor specific drivers that don't really fit elsewhere: - Mediatek drivers gain more support for MT8192, with new support for hw-mutex and mmsys routing, plus support for reset lines in the mmsys driver. - Qualcomm gains a new "sleep stats" driver, and support for the "Generic Packet Router" in the APR driver. - There is a new user interface for routing the UARTS on ASpeed BMCs, something that apparently nobody else has needed so far. - More drivers can now be built as loadable modules, in particular for Broadcom and Samsung platforms. - Lots of improvements to the TI sysc driver for better suspend/resume support" Finally, there are lots of minor cleanups and new device IDs for amlogic, renesas, tegra, qualcomm, mediateka, samsung, imx, layerscape, allwinner, broadcom, and omap" * tag 'drivers-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (179 commits) optee: Fix spelling mistake "reclain" -> "reclaim" Revert "firmware: qcom: scm: Add support for MC boot address API" qcom: spm: allow compile-testing firmware: arm_ffa: Remove unused 'compat_version' variable soc: samsung: exynos-chipid: add exynosautov9 SoC support firmware: qcom: scm: Don't break compile test on non-ARM platforms soc: qcom: smp2p: Add of_node_put() before goto soc: qcom: apr: Add of_node_put() before return soc: qcom: qcom_stats: Fix client votes offset soc: qcom: rpmhpd: fix sm8350_mxc's peer domain dt-bindings: arm: cpus: Document qcom,msm8916-smp enable-method ARM: qcom: Add qcom,msm8916-smp enable-method identical to MSM8226 firmware: qcom: scm: Add support for MC boot address API soc: qcom: spm: Add 8916 SPM register data dt-bindings: soc: qcom: spm: Document qcom,msm8916-saw2-v3.0-cpu soc: qcom: socinfo: Add PM8150C and SMB2351 models firmware: qcom_scm: Fix error retval in __qcom_scm_is_call_available() soc: aspeed: Add UART routing support soc: fsl: dpio: rename the enqueue descriptor variable soc: fsl: dpio: use an explicit NULL instead of 0 ...
2021-10-18reset: mchp: sparx5: Extend support for lan966xHoratiu Vultur
This patch extends sparx5 driver to support also the lan966x. The process to reset the switch is the same only it has different offsets. Therefore make the driver more generic and add support for lan966x. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20211018091522.1113510-3-horatiu.vultur@microchip.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
generated by cgit (git 2.34.1) at 2025-09-28 22:40:27 +0000